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-rw-r--r--doc/README.ARC27
-rw-r--r--doc/README.b4860qds4
-rw-r--r--doc/README.designware_eth25
3 files changed, 29 insertions, 27 deletions
diff --git a/doc/README.ARC b/doc/README.ARC
new file mode 100644
index 0000000..5f414fb
--- /dev/null
+++ b/doc/README.ARC
@@ -0,0 +1,27 @@
+Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs
+that SoC designers can optimize for a wide range of uses, from deeply embedded
+to high-performance host applications.
+
+More information on ARC cores avaialble here:
+http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx
+
+Designers can differentiate their products by using patented configuration
+technology to tailor each ARC processor instance to meet specific performance,
+power and area requirements.
+
+The DesignWare ARC processors are also extendable, allowing designers to add
+their own custom instructions that dramatically increase performance.
+
+Synopsys' ARC processors have been used by over 170 customers worldwide who
+collectively ship more than 1 billion ARC-based chips annually.
+
+All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent
+performance and code density for embedded and host SoC applications.
+
+The RISC microprocessors are synthesizable and can be implemented in any foundry
+or process, and are supported by a complete suite of development tools.
+
+The ARC GNU toolchain with support for all ARC Processors can be downloaded
+from here (available pre-built toolchains as well):
+
+https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases
diff --git a/doc/README.b4860qds b/doc/README.b4860qds
index f8a79db..3da77d9 100644
--- a/doc/README.b4860qds
+++ b/doc/README.b4860qds
@@ -230,14 +230,14 @@ NOR Flash memory Map on B4860 and B4420QDS
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
-0xEF300000 0xEFF3FFFF rootfs (alternate bank) 12MB + 256KB
+0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB
0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
0xEDF40000 0xEDFFFFFF u-boot (alternate bank) 768KB
0xEDF20000 0xEDF3FFFF u-boot env (alternate bank) 128KB
0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
-0xED300000 0xEDF3FFFF rootfs (current bank) 12MB+256MB
+0xED300000 0xEDEFFFFF rootfs (current bank) 12MB
0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
0xEC000000 0xEC01FFFF RCW (current bank) 128KB
diff --git a/doc/README.designware_eth b/doc/README.designware_eth
deleted file mode 100644
index 25ec6bd..0000000
--- a/doc/README.designware_eth
+++ /dev/null
@@ -1,25 +0,0 @@
-This driver supports Designware Ethernet Controller provided by Synopsis.
-
-The driver is enabled by CONFIG_DESIGNWARE_ETH.
-
-The driver has been developed and tested on SPEAr platforms. By default, the
-MDIO interface works at 100/Full. #defining the below options in board
-configuration file changes this behavior.
-
-Call an subroutine from respective board/.../board.c
-designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
-
-The various options suported by the driver are
-1. CONFIG_DW_ALTDESCRIPTOR
- Define this to use the Alternate/Enhanced Descriptor configurations.
-1. CONFIG_DW_AUTONEG
- Define this to autonegotiate with the host before proceeding with mac
- level configuration. This obviates the definitions of CONFIG_DW_SPEED10M
- and CONFIG_DW_DUPLEXHALF.
-2. CONFIG_DW_SPEED10M
- Define this to change the default behavior from 100Mbps to 10Mbps.
-3. CONFIG_DW_DUPLEXHALF
- Define this to change the default behavior from Full Duplex to Half.
-4. CONFIG_DW_SEARCH_PHY
- Define this to search the phy address. This would overwrite the value
- passed as 3rd arg from designware_initialize routine.