diff options
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.SPL | 62 | ||||
| -rw-r--r-- | doc/README.at91-soc | 22 | ||||
| -rw-r--r-- | doc/README.fsl-hwconfig | 25 | ||||
| -rw-r--r-- | doc/README.m68k | 4 | ||||
| -rw-r--r-- | doc/README.mergerbox | 59 | ||||
| -rw-r--r-- | doc/README.nand | 10 | ||||
| -rw-r--r-- | doc/README.p1023rds | 101 | ||||
| -rw-r--r-- | doc/README.p2041rdb | 123 | ||||
| -rw-r--r-- | doc/README.qemu_mips | 2 | ||||
| -rw-r--r-- | doc/README.scrapyard | 3 | ||||
| -rw-r--r-- | doc/README.ublimage | 141 | ||||
| -rw-r--r-- | doc/README.update | 5 |
12 files changed, 531 insertions, 26 deletions
diff --git a/doc/README.SPL b/doc/README.SPL new file mode 100644 index 0000000..ce8e19f --- /dev/null +++ b/doc/README.SPL @@ -0,0 +1,62 @@ +Generic SPL framework +===================== + +Overview +-------- + +To unify all existing implementations for a secondary program loader (SPL) +and to allow simply adding of new implementations this generic SPL framework +has been created. With this framework almost all source files for a board +can be reused. No code duplication or symlinking is necessary anymore. + + +How it works +------------ + +There is a new directory TOPDIR/spl which contains only a Makefile. +The object files are built separately for SPL and placed in this directory. +The final binaries which are generated are u-boot-spl, u-boot-spl.bin and +u-boot-spl.map. + +During the SPL build a variable named CONFIG_SPL_BUILD is exported +in the make environment and also appended to CPPFLAGS with -DCONFIG_SPL_BUILD. +Source files can therefore be compiled for SPL with different settings. +ARM-based boards have previously used the option CONFIG_PRELOADER for it. + +For example: + +ifeq ($(CONFIG_SPL_BUILD),y) +COBJS-y += board_spl.o +else +COBJS-y += board.o +endif + +COBJS-$(CONFIG_SPL_BUILD) += foo.o + +#ifdef CONFIG_SPL_BUILD + foo(); +#endif + + +The building of SPL images can be with: + +#define CONFIG_SPL + +Because SPL images normally have a different text base, one have to be +configured by defining CONFIG_SPL_TEXT_BASE. The linker script have to be +defined with CONFIG_SPL_LDSCRIPT. + +To support generic U-Boot libraries and drivers in the SPL binary one can +optionally define CONFIG_SPL_XXX_SUPPORT. Currently following options +are supported: + +CONFIG_SPL_LIBCOMMON_SUPPORT (common/libcommon.o) +CONFIG_SPL_LIBDISK_SUPPORT (disk/libdisk.o) +CONFIG_SPL_I2C_SUPPORT (drivers/i2c/libi2c.o) +CONFIG_SPL_GPIO_SUPPORT (drivers/gpio/libgpio.o) +CONFIG_SPL_MMC_SUPPORT (drivers/mmc/libmmc.o) +CONFIG_SPL_SERIAL_SUPPORT (drivers/serial/libserial.o) +CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o) +CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o) +CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o) +CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o) diff --git a/doc/README.at91-soc b/doc/README.at91-soc index 425fc58..ed6e76a 100644 --- a/doc/README.at91-soc +++ b/doc/README.at91-soc @@ -40,25 +40,3 @@ The method for updating 4. Convert arch, driver and boards file to new SoC 5. remove legacy code, if all boards and drives are ready - Join AT91 and AT91RM9200 SoC -============================== - -Approximately 95 percent of AT91 and AT91RM9200 SoC parts are the same. -So, we should use the chance, to join both archs togetter. - -To do this follow step needed: - -1. change Makefile - @$(MKCONFIG) $(@:_config=) arm arm920t board vendor at91rm9200 - to - @$(MKCONFIG) $(@:_config=) arm arm920t board vendor at91 -2. remove CONFIG_AT91_LEGACY in board config -3. convert boards file to new SoC access -4. convert or change drivers - -To support the joining process, a new SoC dir (at91) has been adding to -arm920t arch directory. This directory contains files like at91rm9200 dir, but -uses the new c structure Soc access. The advantage of this is, we don't merge -old Soc access code and new code while the board are not converted. -Finally we can delete the whole at91rm9200 dir, if all board support the -new AT91-SoC access. diff --git a/doc/README.fsl-hwconfig b/doc/README.fsl-hwconfig index 03fea74..e752505 100644 --- a/doc/README.fsl-hwconfig +++ b/doc/README.fsl-hwconfig @@ -19,3 +19,28 @@ audclk 'audclk:12' Select the 12.288MHz clock + +usb + Specific to boards have USB controller + + This option specifies the following for a USB controller: + + - which controller mode to use + - which USB PHY to use + + This is used by generic USB device-tree fixup function to update + modified values of phy type and controller mode. + + Also used for configuring multiple USB controllers such that + 'usbN' (where N is 1, 2, etc. refers to controller no.) + + 'phy_type' + Select USB phy type: 'utmi' OR 'ulpi' + + 'dr_mode' + Select USB controller mode: 'host', 'peripheral' OR 'otg' + + Examples: + usb1:dr_mode=host;usb2:dr_mode=peripheral' + + usb1:dr_mode=host,phy_type=utmi;usb2:dr_mode=host' diff --git a/doc/README.m68k b/doc/README.m68k index 3766b33..c85febc 100644 --- a/doc/README.m68k +++ b/doc/README.m68k @@ -111,7 +111,7 @@ CONFIG_SYS_MBAR -- defines the base address of the MCF5272 configuration registe CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5272 internal SRAM CONFIG_SYS_ENET_BD_BASE - -- defines the base addres of the FEC buffer descriptors + -- defines the base address of the FEC buffer descriptors CONFIG_SYS_SCR -- defines the contents of the System Configuration Register CONFIG_SYS_SPR -- defines the contents of the System Protection Register @@ -138,7 +138,7 @@ CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_INT_FLASH_BASE -- defines the base address of the MCF5282 internal Flash memory CONFIG_SYS_ENET_BD_BASE - -- defines the base addres of the FEC buffer descriptors + -- defines the base address of the FEC buffer descriptors CONFIG_SYS_MFD -- defines the PLL Multiplication Factor Devider diff --git a/doc/README.mergerbox b/doc/README.mergerbox new file mode 100644 index 0000000..1994b65 --- /dev/null +++ b/doc/README.mergerbox @@ -0,0 +1,59 @@ +Matrix Vision MergerBox +----------------------- + +1. Board Description + + The MergerBox is a 120x160mm single board computing platform + for 3D Full-HD digital video processing. + + Power Supply is 10-32VDC. + +2 System Components + +2.1 CPU + Freescale MPC8377 CPU running at 800MHz core and 333MHz csb. + 256 MByte DDR-II memory @ 333MHz data rate. + 64 MByte Nor Flash on local bus. + 1 GByte Nand Flash on FCM. + 1 Vitesse VSC8601 RGMII ethernet Phys. + 1 USB host controller over ULPI I/F with 4-Port hub. + 2 serial ports. Console running on ttyS0 @ 115200 8N1. + 1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt. + 2 PCIe x1 busses on local mPCIe and cutom expansion connector. + 2 SATA host ports. + System configuration (HRCW) is taken from I2C EEPROM. + +2.2 Graphics + SM107 emebedded video controller driving a 5" 800x480 TFT panel. + Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory. + +2.3 FPGA + Altera Cyclone-IV EP4C115 with several PCI DMA engines. + Connects to 7x Gennum 3G-SDI transceivers as video interconnect + as well as a HDMI v1.4 compliant output for 3D monitoring. + Utilizes two more DDR-II controllers providing 256MB memory. + +2.4 I2C + Bus1: + AD7418 @ 0x50 for voltage/temp. monitoring. + SX8650 @ 0x90 touch controller for HMI. + EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. + Bus2: + mPCIe SMBus + SiI9022A @ 0x72/0xC0 HDMI transmitter. + TCA6416A @ 0x40 + 0x42 16-Bit I/O expander. + LMH1983 @ 0xCA video PLL. + DS1338C @ 0xD0 real-time clock with embedded crystal. + 9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock. + +3 Flash layout. + + reset vector is 0x00000100, i.e. low boot. + + 00000000 u-boot binary. + 00100000 FPGA raw bit file. + 00300000 FIT image holding kernel, dtb and rescue squashfs. + 03d00000 u-boot environment. + 03e00000 splash image + + mtd partitions are propagated to linux kernel via device tree blob. diff --git a/doc/README.nand b/doc/README.nand index 8eedb6c..751b693 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -78,6 +78,16 @@ Commands: should work well, but loading an image copied from another flash is going to be trouble if there are any bad blocks. + nand write.trimffs addr ofs|partition size + Enabled by the CONFIG_CMD_NAND_TRIMFFS macro. This command will write to + the NAND flash in a manner identical to the 'nand write' command + described above -- with the additional check that all pages at the end + of eraseblocks which contain only 0xff data will not be written to the + NAND flash. This behaviour is required when flashing UBI images + containing UBIFS volumes as per the UBI FAQ[1]. + + [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo + nand write.oob addr ofs|partition size Write `size' bytes from `addr' to the out-of-band data area corresponding to `ofs' in NAND flash. This is limited to the 16 bytes diff --git a/doc/README.p1023rds b/doc/README.p1023rds new file mode 100644 index 0000000..685f5da --- /dev/null +++ b/doc/README.p1023rds @@ -0,0 +1,101 @@ +Overview +-------- +The P1023 process includes a performance optimized implementation of the +QorIQ data Path Acceleration Architecture (DPAA). This architecture +provides the infrastructure to support simplified sharing of networking +interfaces and accelerators by multiple CPU cores. P1023 is an e500 based +dual core SOC. + +P1023RDS board is a Low End Dual core platform supporting the P1023 +processor of QorIQ series. + +Building U-boot +--------------- +To build the u-boot for P1023RDS: +Configure to NOR boot: + make P1023RDS_config +Configure to NAND boot: + make P1023RDS_NAND_config +Build: + make + +Board Switches +-------------- +Most switches on the board should not be changed. The most frequent +user-settable switches on the board are used to configure +the flash banks. + +J4: all open + +Default NOR flash boot switch setting: + Sw3[1:8]: off on on off on on off off + Sw4[1:8]: off off off on off off off off + Sw6[1:8]: off on off on off on on off + Sw7[1:8]: off on off off on off off off + Sw8[1:8]: on off off off off off off off + +For NAND flash boot,set +Sw4[1:4]: off on on on + +The default native ethernet setting is for RGMII mode. +To use SGMII mode, set +SW8[1:2]: OFF OFF +SW7[6:7]: ON ON + +Memory Map +---------- +0x0000_0000 0x7fff_ffff DDR 2G Cacheable +0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable +0xc000_0000 0xdfff_ffff PCI 512M non-cacheable +0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable + +0xe000_0000 0xe003_ffff BCSR 256K BCSR +0xee00_0000 0xefff_ffff NOR flash 32M NOR flash +0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M +0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable +0xffa0_0000 0xffaf_ffff NAND FLASH 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + +Flashing u-boot Images +--------------- +To program the image in the boot flash bank: +NOR flash boot: + => tftp 1000000 u-boot.bin + => protect off all + => erase eff80000 efffffff + => cp.b 1000000 eff80000 80000 + +NAND flash boot: + => tftp 1000000 u-boot-nand.bin + => nand erase 0 80000 + => nand write 1000000 0 80000 + +Firmware ucode location +--------------------------------- +Microcode(ucode) to FMAN's IRAM is needed to make FMAN Ethernet work. +u-boot loads ucode FLASH. The location for ucode: +NOR Flash: 0xfe000000 +NAND Flash: 0x1f00000 + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb p1023rds.dts > p1023rds.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/p1023rds.dts +or + make p1023rds.dtb ARCH=powerpc +in linux-2.6 directory. + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 p1023rds.dtb + bootm 1000000 2000000 c00000 diff --git a/doc/README.p2041rdb b/doc/README.p2041rdb new file mode 100644 index 0000000..292d0d3 --- /dev/null +++ b/doc/README.p2041rdb @@ -0,0 +1,123 @@ +Overview +========= +The P2041 Processor combines four Power Architecture processor cores +with high-performance datapath acceleration architecture(DPAA), CoreNet +fabric infrastructure, as well as network and peripheral bus interfaces +required for networking, telecom/datacom, wireless infrastructure, and +military/aerospace applications. + +P2041RDB board is a quad core platform supporting the P2041 processor +of QorIQ DPAA series. + +Boot from NOR flash +=================== +1. Build image + make P2041RDB_config + make all + +2. Program image + => tftp 1000000 u-boot.bin + => protect off all + => erase eff80000 efffffff + => cp.b 1000000 eff80000 80000 + +3. Program RCW + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => protect off all + => erase ef000000 ef0fffff + => cp.b 1000000 ef000000 2000 + +5. Change DIP-switch + SW1[1-5] = 10110 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SDCard +=================== +1. Build image + make P2041RDB_SDCARD_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SDCard which contains RCW and U-Boot image. + +3. Program the PBL image to SDCard + => tftp 1000000 pbl_sd.bin + => mmcinfo + => mmc write 1000000 8 441 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => mmc write 1000000 46a 10 + +5. Change DIP-switch + SW1[1-5] = 01100 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SPI flash +=================== +1. Build image + make P2041RDB_SPIFLASH_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SPI flash which contains RCW and U-Boot image. + +3. Program the PBL image to SPI flash + => tftp 1000000 pbl_spi.bin + => spi probe 0 + => sf erase 0 100000 + => sf write 1000000 0 $filesize + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => sf erase 110000 10000 + => sf write 1000000 110000 $filesize + +5. Change DIP-switch + SW1[1-5] = 10100 + Note: 1 stands for 'on', 0 stands for 'off' + +CPLD command +============ +The CPLD is used to control the power sequence and some serdes lane +mux function. + +cpld reset - hard reset to default bank +cpld reset altbank - reset to alternate bank +cpld lane_mux <lane> <mux_value> - set multiplexed lane pin + lane 6: 0 -> slot1 (Default) + 1 -> SGMII + lane a: 0 -> slot2 (Default) + 1 -> AURORA + lane c: 0 -> slot2 (Default) + 1 -> SATA0 + lane d: 0 -> slot2 (Default) + 1 -> SATA1 + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this: + dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb + +Or use the following command: + {linux-2.6}/make p2041rdb.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory: + {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb + +Booting Linux +============= +Place a linux uImage in the TFTP disk area. + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp 3000000 p2041rdb.dtb + bootm 1000000 2000000 3000000 diff --git a/doc/README.qemu_mips b/doc/README.qemu_mips index 3985264..e6a3855 100644 --- a/doc/README.qemu_mips +++ b/doc/README.qemu_mips @@ -24,7 +24,7 @@ you can downland #config to build the kernel qemu_mips_defconfig -#patch to fix mips interupt init on 2.6.24.y kernel +#patch to fix mips interrupt init on 2.6.24.y kernel qemu_mips_kernel.patch initrd.gz vmlinux diff --git a/doc/README.scrapyard b/doc/README.scrapyard index d7bf9a7..4cb727f 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,11 +11,12 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +trab arm S3C2400 - 2011-05-01 Gary Jennejohn <garyj@denx.de> xsengine ARM PXA2xx 4262a7c 2010-10-20 wepep250 ARM PXA2xx 7369478 2010-10-20 Peter Figuli <peposh@etc.sk> delta ARM PXA2xx 75e2035 2010-10-20 mp2usb ARM AT91RM2900 ee986e2 2011-01-25 Eric Bénard <eric@eukrea.com> -barco powerpc MPC8245 - 2010-11-23 Marc Leeman <marc.leeman@barco.com> +barco powerpc MPC8245 afaa27b 2010-11-23 Marc Leeman <marc.leeman@barco.com> ERIC powerpc 405GP d9ba451 2010-11-21 Swen Anderson <sand@peppercon.de> VoVPN-GW_100MHz powerpc MPC8260 26fe3d2 2010-10-24 Juergen Selent <j.selent@elmeg.de> NC650 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk <wd@denx.de> diff --git a/doc/README.ublimage b/doc/README.ublimage new file mode 100644 index 0000000..add24d6 --- /dev/null +++ b/doc/README.ublimage @@ -0,0 +1,141 @@ +--------------------------------------------- +UBL image Boot Image generation using mkimage +--------------------------------------------- + +This document describes how to set up an U-Boot image that can be directly +booted by a DaVinci processor via NAND boot mode, using an UBL header, +but without need for UBL. + +For more details see section 11.2 "ARM ROM Boot Modes" of +http://focus.ti.com/lit/ug/sprufg5a/sprufg5a.pdf + +Command syntax: +-------------- +./tools/mkimage -l <u-boot_file> + to list the UBL image file details + +./tools/mkimage -T ublimage \ + -n <board specific configuration file> \ + -d <u-boot binary> <output image file> + +For example, for the davinci dm365evm board: +./tools/mkimage -n ./board/davinci/dm365evm/ublimage.cfg \ + -T ublimage \ + -d u-boot-nand.bin u-boot.ubl + +You can generate the image directly when you compile u-boot with: + +$ make u-boot.ubl + +The output image can be flashed into the NAND. + +Please check the DaVinci documentation for further details. + +Board specific configuration file specifications: +------------------------------------------------- +1. This file must present in the $(BOARDDIR) and the name should be + ublimage.cfg (since this is used in Makefile). +2. This file can have empty lines and lines starting with "#" as first + character to put comments. +3. This file can have configuration command lines as mentioned below, + any other information in this file is treated as invalid. + +Configuration command line syntax: +--------------------------------- +1. Each command line must have two strings, first one command or address + and second one data string +2. Following are the valid command strings and associated data strings:- + Command string data string + -------------- ----------- + MODE UBL special mode, on of: + safe + Example: + MODE safe + + ENTRY Entry point address for the user + bootloader (absolute address) = TEXT_BASE + nand_spl loader. + Example: + ENTRY 0x00000020 + + PAGES Number of pages (size of user bootloader + in number of pages) + Example: + PAGES 27 + + START_BLOCK Block number where user bootloader is present + Example: + START_BLOCK 5 + + START_PAGE Page number where user bootloader is present + (for RBL always 0) + Example: + START_PAGE 0 + +------------------------------------------------ + +Structure of the u-boot.ubl binary: + +compile steps: + +1) nand_spl code compile, with pad_to = (TEXT_BASE + + (CONFIG_SYS_NROF_PAGES_NAND_SPL * pagesize)) + Example: cam_enc_4xx pad_to = 0x20 + (6 * 0x800) = 0x3020 = 12320 + -> u-boot-spl-16k.bin + + !! TEXT_BASE = 0x20, as the RBL starts at 0x20 + +2) compile u-boot.bin ("normal" u-boot) + -> u-boot.bin + +3) create u-boot-nand.bin = u-boot-spl-16k.bin + u-boot.bin + +4) create u-boot.ubl, size = 1 page size NAND + create UBL header and paste it before u-boot.bin + +This steps are done automagically if you do a "make all" + +-> You get an u-boot.ubl binary, which you can flash + into your NAND. + +Structure of this binary (Example for the cam_enc_4xx board with a NAND +page size = 0x800): + +offset : 0x00000 | 0x800 | 0x3800 +content: UBL | nand_spl | u-boot code + Header | code | + +The NAND layout looks for example like this: + +(Example for the cam_enc_4xx board with a NAND page size = 0x800, block +size = 0x20000 and CONFIG_SYS_NROF_UBL_HEADER 5): + +offset : 0x80000 | 0xa0000 | 0xa3000 +content: UBL | nand_spl | u-boot code + Header | code | + ^ ^ + ^ 0xa0000 = CONFIG_SYS_NROF_UBL_HEADER * 0x20000 + ^ + 0x80000 = Block 4 * 0x20000 + +If the cpu starts in NAND boot mode, it checks the UBL descriptor +starting with block 1 (page 0). When a valid UBL signature is found, +the corresponding block number (from 1 to 24) is written to the last 32 +bits of ARM internal memory (0x7ffc-0x8000). This feature is provided +as a basic debug mechanism. If not found, it continues with block 2 +... last possible block is 24 + +If a valid UBL descriptor is found, the UBL descriptor is read and +processed. The descriptor gives the information required for loading +and control transfer to the nand_spl code. The nand_spl code is then +read and processed. + +Once the user-specified start-up conditions are set, the RBL copies the +nand_spl into ARM internal RAM, starting at address 0x0000: 0020. + ^^^^ + +The nand_spl code itself now does necessary intializations, and at least, +copies the u-boot code from NAND into RAM, and jumps to it ... + +------------------------------------------------ +Author: Heiko Schocher <hs@denx.de> diff --git a/doc/README.update b/doc/README.update index 48f03b7..a7f4d9e 100644 --- a/doc/README.update +++ b/doc/README.update @@ -51,6 +51,11 @@ the mkimage tool. dtc tool with support for binary includes, e.g. in version to be prepared. Refer to the doc/uImage.FIT/ directory for more details on FIT images. +This mechanism can be also triggered by the commmand "fitupd". +If an optional, non-zero address is provided as argument, the TFTP transfer +is skipped and the image at this address is used. +The fitupd command is enabled by CONFIG_CMD_FITUPD. + Example .its files ------------------ |