diff options
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.AVR32-port-muxing | 4 | ||||
| -rw-r--r-- | doc/README.PXA_CF | 56 | ||||
| -rw-r--r-- | doc/README.SNTP | 2 | ||||
| -rw-r--r-- | doc/README.Sandpoint8240 | 6 | ||||
| -rw-r--r-- | doc/README.at91 | 6 | ||||
| -rw-r--r-- | doc/README.commands.spl | 31 | ||||
| -rw-r--r-- | doc/README.ebony | 2 | ||||
| -rw-r--r-- | doc/README.fsl-ddr | 4 | ||||
| -rw-r--r-- | doc/README.mpc832xemds | 2 | ||||
| -rw-r--r-- | doc/README.mpc8360emds | 2 | ||||
| -rw-r--r-- | doc/README.mpc837xemds | 2 | ||||
| -rw-r--r-- | doc/README.mpc8544ds | 2 | ||||
| -rw-r--r-- | doc/README.mpc8572ds | 4 | ||||
| -rw-r--r-- | doc/README.mpc85xxads | 2 | ||||
| -rw-r--r-- | doc/README.mvbc_p | 2 | ||||
| -rw-r--r-- | doc/README.mvblm7 | 4 | ||||
| -rw-r--r-- | doc/README.mvsmr | 2 | ||||
| -rw-r--r-- | doc/README.mx6qsabrelite | 12 | ||||
| -rw-r--r-- | doc/README.ocotea | 2 | ||||
| -rw-r--r-- | doc/README.p2020rdb | 4 | ||||
| -rw-r--r-- | doc/README.sh7757lcr | 1 | ||||
| -rw-r--r-- | doc/SPL/README.omap3 | 74 | ||||
| -rw-r--r-- | doc/device-tree-bindings/README | 17 | ||||
| -rw-r--r-- | doc/device-tree-bindings/clock/nvidia,tegra20-car.txt | 207 | ||||
| -rw-r--r-- | doc/device-tree-bindings/i2c/tegra20-i2c.txt | 23 | ||||
| -rw-r--r-- | doc/device-tree-bindings/usb/tegra-usb.txt | 25 |
26 files changed, 412 insertions, 86 deletions
diff --git a/doc/README.AVR32-port-muxing b/doc/README.AVR32-port-muxing index b53799d..8c1718c 100644 --- a/doc/README.AVR32-port-muxing +++ b/doc/README.AVR32-port-muxing @@ -91,7 +91,7 @@ of the flags are the same on all implementations. PORTMUX_DIR_OUTPUT PORTMUX_DIR_INPUT -These mutually-exlusive flags configure the initial direction of the +These mutually-exclusive flags configure the initial direction of the pins. PORTMUX_DIR_OUTPUT means that the pins are driven by the CPU, while PORTMUX_DIR_INPUT means that the pins are tristated by the CPU. These flags are ignored by portmux_select_peripheral(). @@ -125,7 +125,7 @@ PORTMUX_PULL_UP. PORTMUX_DRIVE_HIGH PORTMUX_DRIVE_MAX -These mutually-exlusive flags determine the drive strength of the +These mutually-exclusive flags determine the drive strength of the pins. PORTMUX_DRIVE_MIN will give low power-consumption, but may cause corruption of high-speed signals. PORTMUX_DRIVE_MAX will give high power-consumption, but may be necessary on pins toggling at very high diff --git a/doc/README.PXA_CF b/doc/README.PXA_CF deleted file mode 100644 index 1d76b32..0000000 --- a/doc/README.PXA_CF +++ /dev/null @@ -1,56 +0,0 @@ - -These are brief instructions on how to add support for CF adapters to -custom designed PXA boards. You need to set the parameters in the -config file. This should work for most implementations especially if you -follow the connections of the standard lubbock. Anyway just the block -marked memory configuration should be touched since the other parameters -are imposed by the PXA architecture. - -EDIT 2010-07-01: in common/cmd_ide.c, having CONFIG_PXA_PCMCIA defined -would cause looping on inw()/outw() rather than using insw()/outsw(), -thus making sure IDE / ATA bytes are properly swapped. This behaviour -is now controlled by CONFIG_IDE_SWAP_IO, therefore PXA boards with -PCMCIA should #define CONFIG_IDE_SWAP_IO. - -#define CONFIG_IDE_SWAP_IO - -#define CONFIG_PXA_PCMCIA 1 -#define CONFIG_PXA_IDE 1 - -#define CONFIG_PCMCIA_SLOT_A 1 -/* just to keep build system happy */ - -#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x28000000 -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000000 - -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00004204 -#define CONFIG_SYS_MCMEM1_VAL 0x00000000 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00000000 -#define CONFIG_SYS_MCIO0_VAL 0x00008407 -#define CONFIG_SYS_MCIO1_VAL 0x00000000 -/* memory configuration */ - -#define CONFIG_SYS_IDE_MAXBUS 1 -/* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 -/* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000 - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x1f0 - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x1f0 - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x3f0 - - -Another important point is that maybe you have to power the pcmcia -subsystem. This is very board specific, for an example on how to -do it please search for CONFIG_EXADRON1 in cmd_pcmcia.c diff --git a/doc/README.SNTP b/doc/README.SNTP index 9edc957..da9ec45 100644 --- a/doc/README.SNTP +++ b/doc/README.SNTP @@ -6,7 +6,7 @@ syncronize RTC of the board. This command needs the command line parameter of server's IP address or environment variable "ntpserverip". The network time is sent as UTC. So if you want to set local time to RTC, set the offset in second from UTC to the -enviroment variable "time offset". +environment variable "time offset". If the DHCP server provides time server's IP or time offset, you don't need to set the above environment variables yourself. diff --git a/doc/README.Sandpoint8240 b/doc/README.Sandpoint8240 index a41b69a..fa846dc 100644 --- a/doc/README.Sandpoint8240 +++ b/doc/README.Sandpoint8240 @@ -236,7 +236,7 @@ PART 10) => setenv serverip 192.168.0.10 => setenv gatewayip=192.168.0.1 => saveenv -Saving Enviroment to Flash... +Saving Environment to Flash... Un-Protected 1 sectors Erasing Flash... done @@ -296,7 +296,7 @@ Erase Flash Bank # 2 - missing => cp.b 0x100000 FFF00000 1f28c Copy to Flash... done => saveenv -Saving Enviroment to Flash... +Saving Environment to Flash... Un-Protected 1 sectors Erasing Flash... done @@ -330,7 +330,7 @@ Erase Flash from 0xfff00000 to 0xfff3ffff done Erased 7 sectors Copy to Flash... done -Saving Enviroment to Flash... +Saving Environment to Flash... Un-Protected 1 sectors Erasing Flash... done diff --git a/doc/README.at91 b/doc/README.at91 index 84b5595..b51df00 100644 --- a/doc/README.at91 +++ b/doc/README.at91 @@ -62,16 +62,16 @@ Environment variables U-Boot environment variables can be stored at different places: - Dataflash on SPI chip select 0 (dataflash card) - Nand flash. - - Nor falsh (not populate by default) + - Nor flash (not populate by default) You can choose your storage location at config step (here for at91sam9260ek) : make at91sam9263ek_config - use data flash (spi cs0) (default) make at91sam9263ek_nandflash_config - use nand flash make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0) - make at91sam9263ek_norflash_config - use nor falsh + make at91sam9263ek_norflash_config - use nor flash You can choose to boot directly from U-Boot at config step - make at91sam9263ek_norflash_boot_config - boot from nor falsh + make at91sam9263ek_norflash_boot_config - boot from nor flash ------------------------------------------------------------------------------ diff --git a/doc/README.commands.spl b/doc/README.commands.spl new file mode 100644 index 0000000..ac33273 --- /dev/null +++ b/doc/README.commands.spl @@ -0,0 +1,31 @@ +The spl command is used to export a boot parameter image to RAM. Later +it may implement more functions connected to the SPL. + +SUBCOMMAND EXPORT +To execute the command everything has to be in place as if bootm should be +used. (kernel image, initrd-image, fdt-image etc.) + +export has two subcommands: + atags: exports the ATAGS + fdt: exports the FDT + +Call is: +spl export <ftd|atags> [kernel_addr] [initrd_addr] [fdt_addr if fdt] + + +TYPICAL CALL + +on OMAP3: +nandecc hw +nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ +spl export atags /* export ATAGS */ +nand erase 0x680000 0x20000 /* erase - one page */ +nand write 0x80000100 0x680000 0x20000 /* write the image - one page */ + +call with FDT: +nandecc hw +nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ +tftpboot 0x80000100 devkit8000.dtb /* Read fdt */ +spl export fdt 0x82000000 - 0x80000100 /* export FDT */ +nand erase 0x680000 0x20000 /* erase - one page */ +nand write <adress shown by spl export> 0x680000 0x20000 diff --git a/doc/README.ebony b/doc/README.ebony index a8479a4..4df00b3 100644 --- a/doc/README.ebony +++ b/doc/README.ebony @@ -4,7 +4,7 @@ ======================================================================= This file contains some handy info regarding U-Boot and the AMCC -Ebony evalutation board. See the README.ppc440 for additional +Ebony evaluation board. See the README.ppc440 for additional information. diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 1d50153..5e21658 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -250,7 +250,7 @@ print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs] c<n> - the controller number, eg. c0, c1 d<n> - the DIMM number, eg. d0, d1 spd - print SPD data - dimmparms - DIMM paramaters, calcualted from SPD + dimmparms - DIMM parameters, calculated from SPD commonparms - lowest common parameters for all DIMMs opts - options addresses - address assignment (not implemented yet) @@ -260,7 +260,7 @@ edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value> c<n> - the controller number, eg. c0, c1 d<n> - the DIMM number, eg. d0, d1 spd - print SPD data - dimmparms - DIMM paramaters, calcualted from SPD + dimmparms - DIMM parameters, calculated from SPD commonparms - lowest common parameters for all DIMMs opts - options addresses - address assignment (not implemented yet) diff --git a/doc/README.mpc832xemds b/doc/README.mpc832xemds index 688bdbb..4142aa9 100644 --- a/doc/README.mpc832xemds +++ b/doc/README.mpc832xemds @@ -15,7 +15,7 @@ Freescale MPC832XEMDS Board "On" == 0 SW3 is switch 18 as silk-screened onto the board. - SW4[8] is the bit labled 8 on Switch 4. + SW4[8] is the bit labeled 8 on Switch 4. SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5. SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6. SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" diff --git a/doc/README.mpc8360emds b/doc/README.mpc8360emds index 2b39160..6afa753 100644 --- a/doc/README.mpc8360emds +++ b/doc/README.mpc8360emds @@ -15,7 +15,7 @@ Freescale MPC8360EMDS Board "On" == 0 SW18 is switch 18 as silk-screened onto the board. - SW4[8] is the bit labled 8 on Switch 4. + SW4[8] is the bit labeled 8 on Switch 4. SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3. SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" diff --git a/doc/README.mpc837xemds b/doc/README.mpc837xemds index aa767ae..faf21c9 100644 --- a/doc/README.mpc837xemds +++ b/doc/README.mpc837xemds @@ -14,7 +14,7 @@ Freescale MPC837xEMDS Board "Off" == 1 "On" == 0 - SW4[8] is the bit labled 8 on Switch 4. + SW4[8] is the bit labeled 8 on Switch 4. SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On" and bits labeled 8 is set as "Off". diff --git a/doc/README.mpc8544ds b/doc/README.mpc8544ds index bf257a0..b49c3c0 100644 --- a/doc/README.mpc8544ds +++ b/doc/README.mpc8544ds @@ -22,7 +22,7 @@ boot bank at 0xfff8_0000. Memory Map ---------- -0xff80_0000 - 0xffbf_ffff Alernate bank 4MB +0xff80_0000 - 0xffbf_ffff Alternate bank 4MB 0xffc0_0000 - 0xffff_ffff Boot bank 4MB 0xffb8_0000 Alternate image start 512KB diff --git a/doc/README.mpc8572ds b/doc/README.mpc8572ds index 06dab59..57fd2ad 100644 --- a/doc/README.mpc8572ds +++ b/doc/README.mpc8572ds @@ -19,7 +19,7 @@ Booting is always from the boot bank at 0xec00_0000. Memory Map ---------- -0xe800_0000 - 0xebff_ffff Alernate bank 64MB +0xe800_0000 - 0xebff_ffff Alternate bank 64MB 0xec00_0000 - 0xefff_ffff Boot bank 64MB 0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB @@ -115,7 +115,7 @@ Implementing AMP(Asymmetric MultiProcessing) - Select "Advanced setup" -> " Prompt for advanced kernel configuration options" - Select "Set physical address where the kernel is loaded" and - set it to 0x20000000, asssuming core1 will start from 512MB. + set it to 0x20000000, assuming core1 will start from 512MB. - Select "Set custom page offset address" - Select "Set custom kernel base address" - Select "Set maximum low memory" diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index d059a97..28bbcbe 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -35,7 +35,7 @@ Updated 13-July-2004 Jon Loeliger "On" == 0 SW18 is switch 18 as silk-screened onto the board. - SW4[8] is the bit labled 8 on Switch 4. + SW4[8] is the bit labeled 8 on Switch 4. SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2 SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3 diff --git a/doc/README.mvbc_p b/doc/README.mvbc_p index e3fcb4e..a691137 100644 --- a/doc/README.mvbc_p +++ b/doc/README.mvbc_p @@ -33,7 +33,7 @@ Matrix Vision mvBlueCOUGAR-P (mvBC-P) 2.4 I2C LM75 @ 0x90 for temperature monitoring. EEPROM @ 0xA0 for vendor specifics. - image sensor interface (slave adresses depend on sensor) + image sensor interface (slave addresses depend on sensor) 3 Flash layout. diff --git a/doc/README.mvblm7 b/doc/README.mvblm7 index 3ee9396..a0686f7 100644 --- a/doc/README.mvblm7 +++ b/doc/README.mvblm7 @@ -40,10 +40,10 @@ Matrix Vision mvBlueLYNX-M7 (mvBL-M7) MAX5381 DAC @ 0x60 for 1st digital input threshold. LM75 @ 0x90 for temperature monitoring. EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. - 1st image sensor interface (slave adresses depend on sensor) + 1st image sensor interface (slave addresses depend on sensor) Bus2: MAX5381 DAC @ 0x60 for 2nd digital input threshold. - 2nd image sensor interface (slave adresses depend on sensor) + 2nd image sensor interface (slave addresses depend on sensor) 3 Flash layout. diff --git a/doc/README.mvsmr b/doc/README.mvsmr index d729ea6..8e34cb7 100644 --- a/doc/README.mvsmr +++ b/doc/README.mvsmr @@ -23,7 +23,7 @@ Matrix Vision mvSMR 2.4 I2C EEPROM @ 0xA0 for vendor specifics. - image sensor interface (slave adresses depend on sensor) + image sensor interface (slave addresses depend on sensor) 3 Flash layout. diff --git a/doc/README.mx6qsabrelite b/doc/README.mx6qsabrelite index 4add2bf..0498cba 100644 --- a/doc/README.mx6qsabrelite +++ b/doc/README.mx6qsabrelite @@ -7,20 +7,24 @@ i.MX6q SabreLite board. --------------------------------- The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports -boot from SD card only. However, by default, the early version of SabreLite +boot from SD card only. However, by default, the SabreLite boards boot from the SPI NOR flash. These boards need to be reflashed with a small SD card loader to support boot from SD card. This small SD card loader will be flashed into the SPI NOR. The board will still boot from SPI NOR, but the loader will in turn request the BootROM to load the U-Boot from SD card. -At the moment of writing, please check with Freescale on the availablity of -this small SD loader binary. + +The SD card loader is available from + +https://wiki.linaro.org/Boards/MX6QSabreLite + +under a open-source 3-clause BSD license. To update the SPI-NOR on the SabreLite board without the Freescale manufacturing tool use the following procedure: 1. Write this SD card loader onto a large SD card using: - sudo dd if=MX6_SPI_to_SD_loader.bin of=/dev/sXx + sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx Note: Replace sXx with the device representing the SD card in your system. diff --git a/doc/README.ocotea b/doc/README.ocotea index 9ac3a18..be79b03 100644 --- a/doc/README.ocotea +++ b/doc/README.ocotea @@ -4,7 +4,7 @@ ======================================================================= This file contains some handy info regarding U-Boot and the AMCC -Ocotea 440gx evalutation board. See the README.ppc440 for additional +Ocotea 440gx evaluation board. See the README.ppc440 for additional information. diff --git a/doc/README.p2020rdb b/doc/README.p2020rdb index 8a2302f..cb664a5 100644 --- a/doc/README.p2020rdb +++ b/doc/README.p2020rdb @@ -17,7 +17,7 @@ Booting by default is always from the boot bank at 0xef00_0000. Memory Map ---------- -0xef00_0000 - 0xef7f_ffff Alernate bank 8MB +0xef00_0000 - 0xef7f_ffff Alternate bank 8MB 0xe800_0000 - 0xefff_ffff Boot bank 8MB 0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB @@ -89,7 +89,7 @@ Implementing AMP(Asymmetric MultiProcessing) "Prompt for advanced kernel configuration options" - Select "Set physical address where the kernel is loaded" - and set it to 0x20000000, asssuming core1 will + and set it to 0x20000000, assuming core1 will start from 512MB. - Select "Set custom page offset address" - Select "Set custom kernel base address" diff --git a/doc/README.sh7757lcr b/doc/README.sh7757lcr index 37c1a7a..3e9c1c1 100644 --- a/doc/README.sh7757lcr +++ b/doc/README.sh7757lcr @@ -12,6 +12,7 @@ The R0P7757LC0030RL(board config name:sh7757lcr) has the following device: - SPI ROM 8MB - 2D Graphic controller - Ethernet controller + - eMMC 2GB configuration for This board: diff --git a/doc/SPL/README.omap3 b/doc/SPL/README.omap3 new file mode 100644 index 0000000..cc5d5c0 --- /dev/null +++ b/doc/SPL/README.omap3 @@ -0,0 +1,74 @@ +Overview of SPL on OMAP3 devices +================================ + +Introduction +------------ + +This document provides an overview of how SPL functions on OMAP3 (and related +such as am35x and am37x) processors. + +Methodology +----------- + +On these platforms the ROM supports trying a sequence of boot devices. Once +one has been used successfully to load SPL this information is stored in memory +and the location stored in a register. We will read this to determine where to +read U-Boot from in turn. + +Memory Map +---------- + +This is an example of a typical setup. See top-level README for documentation +of which CONFIG variables control these values. For a given board and the +amount of DRAM available to it different values may need to be used. +Note that the size of the SPL text rodata and data is enforced with a CONFIG +option and growing over that size results in a link error. The SPL stack +starts at the top of SRAM (which is configurable) and grows downward. The +space between the top of SRAM and the enforced upper bound on the size of the +SPL text, data and rodata is considered the safe stack area. Details on +confirming this behavior are shown below. + +A portion of the system memory map looks as follows: +SRAM: 0x40200000 - 0x4020FFFF +DDR1: 0x80000000 - 0xBFFFFFFF + +Option 1 (SPL only): +0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata +0x4020BC00 - 0x4020FFFC: Area for the SPL stack. +0x80000000 - 0x8007FFFF: Area for the SPL BSS. +0x80100000: CONFIG_SYS_TEXT_BASE of U-Boot +0x80208000 - 0x80307FFF: malloc() pool available to SPL. + +Option 2 (SPL or X-Loader): +0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata +0x4020BC00 - 0x4020FFFC: Area for the SPL stack. +0x80008000: CONFIG_SYS_TEXT_BASE of U-Boot +0x87000000 - 0x8707FFFF: Area for the SPL BSS. +0x87080000 - 0x870FFFFF: malloc() pool available to SPL. + +For the areas that reside within DDR1 they must not be used prior to s_init() +completing. Note that CONFIG_SYS_TEXT_BASE must be clear of the areas that SPL +uses while running. This is why we have two versions of the memory map that +only vary in where the BSS and malloc pool reside. + +Estimating stack usage +---------------------- + +With gcc 4.6 (and later) and the use of GNU cflow it is possible to estimate +stack usage at various points in run sequence of SPL. The -fstack-usage option +to gcc will produce '.su' files (such as arch/arm/cpu/armv7/syslib.su) that +will give stack usage information and cflow can construct program flow. + +Must have gcc 4.6 or later, which supports -fstack-usage + +1) Build normally +2) Perform the following shell command to generate a list of C files used in +SPL: +$ find spl -name '*.su' | sed -e 's:^spl/::' -e 's:[.]su$:.c:' > used-spl.list +3) Execute cflow: +$ cflow --main=board_init_r `cat used-spl.list` 2>&1 | $PAGER + +cflow will spit out a number of warnings as it does not parse +the config files and picks functions based on #ifdef. Parsing the '.i' +files instead introduces another set of headaches. These warnings are +not usually important to understanding the flow, however. diff --git a/doc/device-tree-bindings/README b/doc/device-tree-bindings/README new file mode 100644 index 0000000..2ea3439 --- /dev/null +++ b/doc/device-tree-bindings/README @@ -0,0 +1,17 @@ +Device Tree Bindings Staging Area +================================= + +This directory contains device tree bindings for U-Boot. + +These follow along with Linux kernel bindings, with a few additions. By +adding the files here, U-Boot patches can clearly show thees additions. +This makes it easier for device tree people to review these additions in +patches sent to the U-Boot mailing list. + +The intent IS to commit these files to U-Boot. Hopefully at some point +the files will be stored in another repo (shared with Linux) which is +brought in as needed. Changes here are intended to mirror changes in the +Linux Documentation/devicetree/bindings/ directory. + +sjg@chromium.org +17-Jan-12 diff --git a/doc/device-tree-bindings/clock/nvidia,tegra20-car.txt b/doc/device-tree-bindings/clock/nvidia,tegra20-car.txt new file mode 100644 index 0000000..5c07fca --- /dev/null +++ b/doc/device-tree-bindings/clock/nvidia,tegra20-car.txt @@ -0,0 +1,207 @@ +NVIDIA Tegra20 Clock And Reset Controller + +This binding uses the common clock binding: +Documentation/devicetree/bindings/clock/clock-bindings.txt + +The CAR (Clock And Reset) Controller on Tegra is the HW module responsible +for muxing and gating Tegra's clocks, and setting their rates. + +Required properties : +- compatible : Should be "nvidia,tegra20-car" +- reg : Should contain CAR registers location and length +- clocks : Should contain phandle and clock specifiers for two clocks: + the 32 KHz "32k_in", and the board-specific oscillator "osc". +- #clock-cells : Should be 1. + In clock consumers, this cell represents the clock ID exposed by the CAR. + + The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + registers. These IDs often match those in the CAR's RST_DEVICES registers, + but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + this case, those clocks are assigned IDs above 95 in order to highlight + this issue. Implementations that interpret these clock IDs as bit values + within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + explicitly handle these special cases. + + The balance of the clocks controlled by the CAR are assigned IDs of 96 and + above. + + 0 cpu + 1 unassigned + 2 unassigned + 3 ac97 + 4 rtc + 5 tmr + 6 uart1 + 7 unassigned (register bit affects uart2 and vfir) + 8 gpio + 9 sdmmc2 + 10 unassigned (register bit affects spdif_in and spdif_out) + 11 i2s1 + 12 i2c1 + 13 ndflash + 14 sdmmc1 + 15 sdmmc4 + 16 twc + 17 pwm + 18 i2s2 + 19 epp + 20 unassigned (register bit affects vi and vi_sensor) + 21 2d + 22 usbd + 23 isp + 24 3d + 25 ide + 26 disp2 + 27 disp1 + 28 host1x + 29 vcp + 30 unassigned + 31 cache2 + + 32 mem + 33 ahbdma + 34 apbdma + 35 unassigned + 36 kbc + 37 stat_mon + 38 pmc + 39 fuse + 40 kfuse + 41 sbc1 + 42 snor + 43 spi1 + 44 sbc2 + 45 xio + 46 sbc3 + 47 dvc + 48 dsi + 49 unassigned (register bit affects tvo and cve) + 50 mipi + 51 hdmi + 52 csi + 53 tvdac + 54 i2c2 + 55 uart3 + 56 unassigned + 57 emc + 58 usb2 + 59 usb3 + 60 mpe + 61 vde + 62 bsea + 63 bsev + + 64 speedo + 65 uart4 + 66 uart5 + 67 i2c3 + 68 sbc4 + 69 sdmmc3 + 70 pcie + 71 owr + 72 afi + 73 csite + 74 unassigned + 75 avpucq + 76 la + 77 unassigned + 78 unassigned + 79 unassigned + 80 unassigned + 81 unassigned + 82 unassigned + 83 unassigned + 84 irama + 85 iramb + 86 iramc + 87 iramd + 88 cram2 + 89 audio_2x a/k/a audio_2x_sync_clk + 90 clk_d + 91 unassigned + 92 sus + 93 cdev1 + 94 cdev2 + 95 unassigned + + 96 uart2 + 97 vfir + 98 spdif_in + 99 spdif_out + 100 vi + 101 vi_sensor + 102 tvo + 103 cve + 104 osc + 105 clk_32k a/k/a clk_s + 106 clk_m + 107 sclk + 108 cclk + 109 hclk + 110 pclk + 111 blink + 112 pll_a + 113 pll_a_out0 + 114 pll_c + 115 pll_c_out1 + 116 pll_d + 117 pll_d_out0 + 118 pll_e + 119 pll_m + 120 pll_m_out1 + 121 pll_p + 122 pll_p_out1 + 123 pll_p_out2 + 124 pll_p_out3 + 125 pll_p_out4 + 126 pll_s + 127 pll_u + 128 pll_x + 129 cop a/k/a avp + 130 audio a/k/a audio_sync_clk + +Example SoC include file: + +/ { + tegra_car: clock@60006000 { + compatible = "nvidia,tegra20-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + + usb@c5004000 { + clocks = <&tegra_car 58>; /* usb2 */ + }; +}; + +Example board file: + +/ { + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + }; + + i2c@7000d000 { + pmic@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + + clk_32k: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + }; + + &tegra_car { + clocks = <&clk_32k> <&osc>; + }; +}; diff --git a/doc/device-tree-bindings/i2c/tegra20-i2c.txt b/doc/device-tree-bindings/i2c/tegra20-i2c.txt new file mode 100644 index 0000000..d601c17 --- /dev/null +++ b/doc/device-tree-bindings/i2c/tegra20-i2c.txt @@ -0,0 +1,23 @@ +(Placeholder note while we locate the kernel Tegra20 bindings) + +Added in U-Boot: + +Required properties: + - clocks : Two clocks must be given, each as a phandle to the Tegra's + CAR node and the clock number as a parameter: + - the I2C clock to use for the peripheral + - the pll_p_out3 clock, which can be used for fast operation. This + does not change and is the same for all I2C nodes. + +Example: +(TODO: merge with existing example): + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + interrupts = < 116 >; + /* PERIPH_ID_I2C2, PLL_P_OUT3 */ + clocks = <&tegra_car 54>, <&tegra_car 124>; + }; diff --git a/doc/device-tree-bindings/usb/tegra-usb.txt b/doc/device-tree-bindings/usb/tegra-usb.txt new file mode 100644 index 0000000..5282d44 --- /dev/null +++ b/doc/device-tree-bindings/usb/tegra-usb.txt @@ -0,0 +1,25 @@ +Tegra SOC USB controllers + +The device node for a USB controller that is part of a Tegra +SOC is as described in the document "Open Firmware Recommended +Practice : Universal Serial Bus" with the following modifications +and additions : + +Required properties : + - compatible : Should be "nvidia,tegra20-ehci" for USB controllers + used in host mode. + - phy_type : Should be one of "ulpi" or "utmi". + - nvidia,vbus-gpio : If present, specifies a gpio that needs to be + activated for the bus to be powered. + +Optional properties: + - dr_mode : dual role mode. Indicates the working mode for + nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral", + or "otg". Default to "host" if not defined for backward compatibility. + host means this is a host controller + peripheral means it is device controller + otg means it can operate as either ("on the go") + - nvidia,has-legacy-mode : boolean indicates whether this controller can + operate in legacy mode (as APX 2500 / 2600). In legacy mode some + registers are accessed through the APB_MISC base address instead of + the USB controller. |