diff options
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.JFFS2 | 2 | ||||
| -rw-r--r-- | doc/README.PIP405 | 14 | ||||
| -rw-r--r-- | doc/README.SNTP | 4 | ||||
| -rw-r--r-- | doc/README.bedbug | 10 | ||||
| -rw-r--r-- | doc/README.generic_usb_ohci | 60 | ||||
| -rw-r--r-- | doc/README.mpc8323erdb | 71 | ||||
| -rw-r--r-- | doc/README.mpc8360emds | 23 | ||||
| -rw-r--r-- | doc/README.mpc83xx.ddrecc (renamed from doc/README.mpc8349emds.ddrecc) | 60 | ||||
| -rw-r--r-- | doc/README.nand | 4 | ||||
| -rw-r--r-- | doc/README.ppc440 | 13 | ||||
| -rw-r--r-- | doc/README.sha1 | 57 | ||||
| -rw-r--r-- | doc/README.usb | 6 |
12 files changed, 261 insertions, 63 deletions
diff --git a/doc/README.JFFS2 b/doc/README.JFFS2 index 270da90..c5d67fd 100644 --- a/doc/README.JFFS2 +++ b/doc/README.JFFS2 @@ -2,7 +2,7 @@ JFFS2 options and usage. ----------------------- JFFS2 in U-Boot is a read only implementation of the file system in -Linux with the same name. To use JFFS2 define CFG_CMD_JFFS2. +Linux with the same name. To use JFFS2 define CONFIG_CMD_JFFS2. The module adds three new commands. fsload - load binary file from a file system image diff --git a/doc/README.PIP405 b/doc/README.PIP405 index c5ccf18..610ff21 100644 --- a/doc/README.PIP405 +++ b/doc/README.PIP405 @@ -32,10 +32,8 @@ Changed files: - include/cmd_bsp.h added PIP405 commands definitions - include/cmd_condefs.h added Floppy and SCSI support - include/cmd_disk.h changed to work with block device description -- include/config_LANTEC.h excluded CFG_CMD_FDC and CFG_CMD_SCSI from - CONFIG_CMD_FULL -- include/config_hymod.h excluded CFG_CMD_FDC and CFG_CMD_SCSI from - CONFIG_CMD_FULL +- include/config_LANTEC.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI +- include/config_hymod.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI - include/flash.h added INTEL_ID_28F320C3T 0x88C488C4 - include/i2c.h added "defined(CONFIG_PIP405)" - include/image.h added IH_OS_U_BOOT, IH_TYPE_FIRMWARE @@ -88,8 +86,8 @@ section "Changes". New Commands: ------------- -CFG_CMD_SCSI SCSI Support -CFG_CMF_FDC Floppy disk support +CONFIG_CMD_SCSI SCSI Support +CONFIG_CMF_FDC Floppy disk support IDE additions: -------------- @@ -172,8 +170,8 @@ Added Devices: Floppy support: --------------- Support of a standard floppy disk controller at address CFG_ISA_IO_BASE_ADDRESS -+ 0x3F0. Enabled with define CFG_CMD_FDC. Reads a unformated floppy disk with a -image header (see: mkimage). No interrupts and no DMA are used for this. ++ 0x3F0. Enabled with define CONFIG_CMD_FDC. Reads a unformated floppy disk +with a image header (see: mkimage). No interrupts and no DMA are used for this. Added files: - common/cmd_fdc.c - include/cmd_fdc.h diff --git a/doc/README.SNTP b/doc/README.SNTP index fd6f209..9edc957 100644 --- a/doc/README.SNTP +++ b/doc/README.SNTP @@ -1,5 +1,5 @@ -To use SNTP support, add a define CFG_CMD_SNTP to CONFIG_COMMANDS in -the configuration file of the board. +To use SNTP support, add define CONFIG_CMD_SNTP to the +configuration file of the board. The "sntp" command gets network time from NTP time server and syncronize RTC of the board. This command needs the command line diff --git a/doc/README.bedbug b/doc/README.bedbug index 9cfb421..2616acc 100644 --- a/doc/README.bedbug +++ b/doc/README.bedbug @@ -31,12 +31,6 @@ can be easily implemented. if it is an illegal instruction, privileged instruction or a trap. Also added debug trap handler. -./include/cmd_confdefs.h - Added definition of CFG_CMD_BEDBUG. - -./include/config_WALNUT405.h - Added CFG_CMD_BEDBUG to the CONFIG_COMMANDS for the WALNUT. - ./include/ppc_asm.tmpl Added code to handle critical exceptions @@ -78,10 +72,6 @@ Changes: cpu/mpc8xx/traps.c Added new routine DebugException() - include/config_MBX.h - Added CFG_CMD_BEDBUG to CONFIG_COMMANDS define - - New Files: cpu/mpc8xx/bedbug_860.c diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci new file mode 100644 index 0000000..c343dfd --- /dev/null +++ b/doc/README.generic_usb_ohci @@ -0,0 +1,60 @@ +Notes on the the generic USB-OHCI driver +======================================== + +This driver (drivers/usb_ohci.[ch]) is the result of the merge of +various existing OHCI drivers that were basically identical beside +cpu/board dependant initalization. This initalization has been moved +into cpu/board directories and are called via the hooks below. + +Configuration options +---------------------- + + CONFIG_USB_OHCI_NEW: enable the new OHCI driver + + CFG_USB_OHCI_BOARD_INIT: call the board dependant hooks: + + - extern int usb_board_init(void); + - extern int usb_board_stop(void); + - extern int usb_cpu_init_fail(void); + + CFG_USB_OHCI_CPU_INIT: call the cpu dependant hooks: + + - extern int usb_cpu_init(void); + - extern int usb_cpu_stop(void); + - extern int usb_cpu_init_fail(void); + + CFG_USB_OHCI_REGS_BASE: defines the base address of the OHCI + registers + + CFG_USB_OHCI_SLOT_NAME: slot name + + CFG_USB_OHCI_MAX_ROOT_PORTS: maximal number of ports of the + root hub. + + +Endianness issues +------------------ + +The USB bus operates in little endian, but unfortunately there are +OHCI controllers that operate in big endian such as ppc4xx and +mpc5xxx. For these the config option + + CFG_OHCI_BE_CONTROLLER + +needs to be defined. + + +PCI Controllers +---------------- + +You'll need to define + + CONFIG_PCI_OHCI + +PCI Controllers need to do byte swapping on register accesses, so they +should to define: + + CFG_OHCI_SWAP_REG_ACCESS + + + diff --git a/doc/README.mpc8323erdb b/doc/README.mpc8323erdb new file mode 100644 index 0000000..6f89829 --- /dev/null +++ b/doc/README.mpc8323erdb @@ -0,0 +1,71 @@ +Freescale MPC8323ERDB Board +----------------------------------------- + +1. Memory Map + The memory map looks like this: + + 0x0000_0000 0x03ff_ffff DDR 64M + 0x8000_0000 0x8fff_ffff PCI MEM 256M + 0x9000_0000 0x9fff_ffff PCI_MMIO 256M + 0xe000_0000 0xe00f_ffff IMMR 1M + 0xd000_0000 0xd3ff_ffff PCI IO 64M + 0xfe00_0000 0xfeff_ffff NOR FLASH (CS0) 16M + +2. Compilation + + Assuming you're using BASH (or similar) as your shell: + + export CROSS_COMPILE=your-cross-compiler-prefix- + make distclean + make MPC8323ERDB_config + make + +3. Downloading and Flashing Images + +3.1 Reflash U-boot Image using U-boot + + N.b, have an alternate means of programming + the flash available if the new u-boot doesn't boot. + + First try a: + + tftpboot $loadaddr $uboot + + to make sure that the TFTP load will succeed before + an erase goes ahead and wipes out your current firmware. + Then do a: + + run tftpflash + + which is a shorter version of the manual sequence: + + tftp $loadaddr u-boot.bin + protect off fe000000 +$filesize + erase fe000000 +$filesize + cp.b $loadaddr fe000000 $filesize + + To keep your old u-boot's environment variables, do a: + + saveenv + + prior to resetting the board. + +3.2 Downloading and Booting Linux Kernel + + Ensure that all networking-related environment variables are set + properly (including ipaddr, serverip, gatewayip (if needed), + netmask, ethaddr, eth1addr, rootpath (if using NFS root), + fdtfile, and bootfile). + + Then, do one of the following, depending on whether you + want an NFS root or a ramdisk root: + + run nfsboot + + or + + run ramboot + +4 Notes + + The console baudrate for MPC8323ERDB is 115200bps. diff --git a/doc/README.mpc8360emds b/doc/README.mpc8360emds index c87469f..5f20247 100644 --- a/doc/README.mpc8360emds +++ b/doc/README.mpc8360emds @@ -21,7 +21,13 @@ Freescale MPC8360EMDS Board SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" and bits labeled 8 is set as "Off". -1.1 For the MPC8360E PB PROTO Board +1.1 There are three type boards for MPC8360E silicon up to now, They are + + * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE) + * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT) + * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE) + +1.2 For all the MPC8360EMDS Board First, make sure the board default setting is consistent with the document shipped with your board. Then apply the following setting: @@ -33,6 +39,21 @@ Freescale MPC8360EMDS Board JP6 1-2 on board Oscillator: 66M +1.3 Since different board/chip rev. combinations have AC timing issues, + u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default + by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers). + + When the rev2.x silicon mount on these boards, and if you are using + u-boot version after this patch, to make the ethernet interfaces usable, + and to enable RGMII-ID on your board, you have to setup the jumpers + correctly. + + * MPC8360E-MDS-PB PROTO + nothing to do + * MPC8360E-MDS-PB PILOT + JP9 and JP8 should be ON + * MPC8360EA-MDS-PB PROTO + JP2 and JP3 should be ON 2. Memory Map diff --git a/doc/README.mpc8349emds.ddrecc b/doc/README.mpc83xx.ddrecc index eb249c3..0029f08 100644 --- a/doc/README.mpc8349emds.ddrecc +++ b/doc/README.mpc83xx.ddrecc @@ -15,10 +15,10 @@ IMPORTANT NOTICE: enabling injecting multiple-bit errors is potentially dangerous as such errors are NOT corrected by the controller. Therefore caution should be taken when enabling the injection of multiple-bit errors: it is only safe when used on a carefully selected memory area and used under control of -the 'ecc test' command (see example 'Injecting Multiple-Bit Errors' below). In -particular, when you simply set the multiple-bit errors in inject mask and -enable injection, U-Boot is very likely to hang quickly as the errors will be -injected when it accesses its code, data etc. +the 'ecc testdw' 'ecc testword' command (see example 'Injecting Multiple-Bit +Errors' below). In particular, when you simply set the multiple-bit errors in +inject mask and enable injection, U-Boot is very likely to hang quickly as the +errors will be injected when it accesses its code, data etc. Use cases for DDR 'ecc' command: @@ -40,7 +40,7 @@ Injecting Single-Bit Errors 2. Run test over some memory region -=> ecc test 200000 10 +=> ecc testdw 200000 10 3. Check ECC status @@ -61,57 +61,57 @@ Memory Error Detect: 16 errors were generated, Single-Bit Error flag was not set as Single Bit Error Counter did not reach Single-Bit Error Threshold. -4. Make sure used memory region got re-initialized with 0xcafecafe pattern +4. Make sure used memory region got re-initialized with 0x0123456789abcdef => md 200000 -00200000: cafecafe cafecafe cafecafe cafecafe ................ -00200010: cafecafe cafecafe cafecafe cafecafe ................ -00200020: cafecafe cafecafe cafecafe cafecafe ................ -00200030: cafecafe cafecafe cafecafe cafecafe ................ -00200040: cafecafe cafecafe cafecafe cafecafe ................ -00200050: cafecafe cafecafe cafecafe cafecafe ................ -00200060: cafecafe cafecafe cafecafe cafecafe ................ -00200070: cafecafe cafecafe cafecafe cafecafe ................ +00200000: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200010: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200020: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200030: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200040: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200050: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200060: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200070: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... 00200080: deadbeef deadbeef deadbeef deadbeef ................ 00200090: deadbeef deadbeef deadbeef deadbeef ................ - Injecting Multiple-Bit Errors ----------------------------- 1. Set more than 1 bit in Data Path Error Inject Mask -=> ecc injectdatahi 5 +=> ecc injectdatahi 1 +=> ecc injectdatalo 1 2. Run test over some memory region -=> ecc test 200000 10 +=> ecc testword 200000 1 3. Check ECC status => ecc status ... -Memory Data Path Error Injection Mask High/Low: 00000005 00000000 +Memory Data Path Error Injection Mask High/Low: 00000001 00000001 ... Memory Error Detect: - Multiple Memory Errors: 1 + Multiple Memory Errors: 0 Multiple-Bit Error: 1 Single-Bit Error: 0 ... -Observe that both Multiple Memory Errors and Multiple-Bit Error flags are set. +The Multiple Memory Errors flags not set and Multiple-Bit Error flags are set. -4. Make sure used memory region got re-initialized with 0xcafecafe pattern +4. Make sure used memory region got re-initialized with 0x0123456789abcdef => md 200000 -00200000: cafecafe cafecafe cafecafe cafecafe ................ -00200010: cafecafe cafecafe cafecafe cafecafe ................ -00200020: cafecafe cafecafe cafecafe cafecafe ................ -00200030: cafecafe cafecafe cafecafe cafecafe ................ -00200040: cafecafe cafecafe cafecafe cafecafe ................ -00200050: cafecafe cafecafe cafecafe cafecafe ................ -00200060: cafecafe cafecafe cafecafe cafecafe ................ -00200070: cafecafe cafecafe cafecafe cafecafe ................ +00200000: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200010: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200020: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200030: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200040: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200050: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200060: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200070: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... 00200080: deadbeef deadbeef deadbeef deadbeef ................ 00200090: deadbeef deadbeef deadbeef deadbeef ................ @@ -140,7 +140,7 @@ Test Single-Bit Error Counter and Threshold ... Memory Single-Bit Error Management (0..255): Single-Bit Error Threshold: 255 - Single Bit Error Counter: 60 + Single Bit Error Counter: 199 Memory Error Detect: Multiple Memory Errors: 1 diff --git a/doc/README.nand b/doc/README.nand index 5c31845..c5c5ef2 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -93,8 +93,8 @@ Commands: Configuration Options: - CFG_CMD_NAND - A good one to add to CONFIG_COMMANDS since it enables NAND support. + CONFIG_CMD_NAND + Enables NAND support and commmands. CONFIG_MTD_NAND_ECC_JFFS2 Define this if you want the Error Correction Code information in diff --git a/doc/README.ppc440 b/doc/README.ppc440 index 08f34f5..2e04aba 100644 --- a/doc/README.ppc440 +++ b/doc/README.ppc440 @@ -146,12 +146,13 @@ that maps in a single PCI I/O space and PCI memory space. The I/O space begins at PCI I/O address 0 and the PCI memory space is 256 MB starting at PCI address CFG_PCI_TARGBASE. After the pci_controller structure is initialized, the cpu-specific code will -call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is -defined. This routine is implemented by board-specific code & is where -the board can over-ride/extend the default pci_controller structure -settings and do other pre-initialization tasks. If pci_pre_init() -returns a value of zero, PCI initialization is aborted; otherwise the -controller structure is registered and initialization continues. +call the routine pci_pre_init(). This routine is implemented by +board-specific code & is where the board can over-ride/extend the +default pci_controller structure settings and exspecially provide +a routine to map the PCI interrupts and do other pre-initialization +tasks. If pci_pre_init() returns a value of zero, PCI initialization +is aborted; otherwise the controller structure is registered and +initialization continues. The default 440GP PCI target configuration is minimal -- it assumes that the strapping registers are set as necessary. Since the strapping bits diff --git a/doc/README.sha1 b/doc/README.sha1 new file mode 100644 index 0000000..7992f7f --- /dev/null +++ b/doc/README.sha1 @@ -0,0 +1,57 @@ +SHA1 usage: +----------- + +In the U-Boot Image for the pcs440ep board is a SHA1 checksum integrated. +This SHA1 sum is used, to check, if the U-Boot Image in Flash is not +corrupted. + +The following command is available: + +=> help sha1 +sha1 address len [addr] calculate the SHA1 sum [save at addr] + -p calculate the SHA1 sum from the U-Boot image in flash and print + -c check the U-Boot image in flash + +"sha1 -p" + calculates and prints the SHA1 sum, from the Image stored in Flash + +"sha1 -c" + check, if the SHA1 sum from the Image stored in Flash is correct + + +It is possible to calculate a SHA1 checksum from a memoryrange with: + +"sha1 address len" + +If you want to store a new Image in Flash for the pcs440ep board, +which has no SHA1 sum, you can do the following: + +a) cp the new Image on a position in RAM (here 0x300000) + (for this example we use the Image from Flash, stored at 0xfffa0000 and + 0x60000 Bytes long) + +"cp.b fffa0000 300000 60000" + +b) Initialize the SHA1 sum in the Image with 0x00 + The SHA1 sum is stored in Flash at: + CFG_MONITOR_BASE + CFG_MONITOR_LEN + SHA1_SUM_POS + for the pcs440ep Flash: 0xfffa0000 + 0x60000 + -0x20 + = 0xffffffe0 + for the example in RAM: 0x300000 + 0x60000 + -0x20 + = 0x35ffe0 + + note: a SHA1 checksum is 20 bytes long. + +"mw.b 35ffe0 0 14" + +c) now calculate the SHA1 sum from the memoryrange and write + the calculated checksum at the right place: + +"sha1 300000 60000 35ffe0" + +Now you have a U-Boot-Image for the pcs440ep board with the correct SHA1 sum. + +If you do a "./MAKEALL pcs440ep" or a "make all" to get the U-Boot image, +the correct SHA1 sum will be automagically included in the U-Boot image. + +Heiko Schocher, 11 Jul 2007 diff --git a/doc/README.usb b/doc/README.usb index 41f76f4..b3bcb91 100644 --- a/doc/README.usb +++ b/doc/README.usb @@ -73,8 +73,8 @@ Storage USB Commands: Config Switches: ---------------- -CFG_CMD_USB enables basic USB support and the usb command -CONFIG_USB_UHCI defines the lowlevel part.A lowlevel part must be defined if - using CFG_CMD_USB +CONFIG_CMD_USB enables basic USB support and the usb command +CONFIG_USB_UHCI defines the lowlevel part.A lowlevel part must be defined + if using CONFIG_CMD_USB CONFIG_USB_KEYBOARD enables the USB Keyboard CONFIG_USB_STORAGE enables the USB storage devices |