diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/ppc4xx/cpu.c | 20 | ||||
| -rw-r--r-- | cpu/ppc4xx/ndfc.c | 39 |
2 files changed, 40 insertions, 19 deletions
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 94478db..f4a7208 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -192,6 +192,7 @@ int checkcpu (void) char buf[32]; #if !defined(CONFIG_IOP480) + char addstr[64] = ""; sys_info_t sys_info; puts ("CPU: "); @@ -308,19 +309,23 @@ int checkcpu (void) #endif /* CONFIG_440 */ case PVR_440EPX1_RA: - puts("EPx Rev. A - Security/Kasumi support"); + puts("EPx Rev. A"); + strcpy(addstr, "Security/Kasumi support"); break; case PVR_440EPX2_RA: - puts("EPx Rev. A - No Security/Kasumi support"); + puts("EPx Rev. A"); + strcpy(addstr, "No Security/Kasumi support"); break; case PVR_440GRX1_RA: - puts("GRx Rev. A - Security/Kasumi support"); + puts("GRx Rev. A"); + strcpy(addstr, "Security/Kasumi support"); break; case PVR_440GRX2_RA: - puts("GRx Rev. A - No Security/Kasumi support"); + puts("GRx Rev. A"); + strcpy(addstr, "No Security/Kasumi support"); break; case PVR_440SP_RA: @@ -349,13 +354,16 @@ int checkcpu (void) sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, FREQ_EBC / 1000000); + if (addstr[0] != 0) + printf(" %s\n", addstr); + #if defined(I2C_BOOTROM) printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); #if defined(SDR0_PINSTP_SHIFT) printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A'); printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); -#endif -#endif +#endif /* SDR0_PINSTP_SHIFT */ +#endif /* I2C_BOOTROM */ #if defined(CONFIG_PCI) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index 183ab5e..2c44111 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -66,7 +66,7 @@ static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; if (hwctl & 0x1) out8(base + NDFC_CMD, byte); @@ -79,7 +79,7 @@ static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) static u_char ndfc_read_byte(struct mtd_info *mtdinfo) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; return (in8(base + NDFC_DATA)); } @@ -87,7 +87,7 @@ static u_char ndfc_read_byte(struct mtd_info *mtdinfo) static int ndfc_dev_ready(struct mtd_info *mtdinfo) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY)) ; @@ -111,30 +111,30 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo) static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; uint32_t *p = (uint32_t *) buf; - for(;len > 0; len -= 4) + for (;len > 0; len -= 4) *p++ = in32(base + NDFC_DATA); } static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; uint32_t *p = (uint32_t *) buf; - for(; len > 0; len -= 4) + for (; len > 0; len -= 4) out32(base + NDFC_DATA, *p++); } static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; uint32_t *p = (uint32_t *) buf; - for(; len > 0; len -= 4) + for (; len > 0; len -= 4) if (*p++ != in32(base + NDFC_DATA)) return -1; @@ -142,8 +142,20 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len } #endif /* #ifndef CONFIG_NAND_SPL */ +void board_nand_select_device(struct nand_chip *nand, int chip) +{ + ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc; + + /* Set NandFlash Core Configuration Register */ + /* 1col x 2 rows */ + out32(base + NDFC_CCR, 0x00000000 | (chip << 24)); +} + void board_nand_init(struct nand_chip *nand) { + int chip = (ulong)nand->IO_ADDR_W & 0x00000003; + ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc; + nand->eccmode = NAND_ECC_SOFT; nand->hwcontrol = ndfc_hwcontrol; @@ -166,10 +178,11 @@ void board_nand_init(struct nand_chip *nand) mtebc(pb0ap, CFG_EBC_PB0AP); #endif - /* Set NandFlash Core Configuration Register */ - /* Chip select 3, 1col x 2 rows */ - out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24)); - out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222); + /* + * Select required NAND chip in NDFC + */ + board_nand_select_device(nand, chip); + out32(base + NDFC_BCFG0 + (chip << 2), 0x80002222); } #endif |