diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/ppc4xx/44x_spd_ddr2.c | 7 | ||||
| -rw-r--r-- | cpu/pxa/start.S | 6 |
2 files changed, 6 insertions, 7 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 5b5de48..ec76b71 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -1,7 +1,10 @@ /* * cpu/ppc4xx/44x_spd_ddr2.c * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a - * DDR2 controller (non Denali Core). Those are 440SP/SPe. + * DDR2 controller (non Denali Core). Those currently are: + * + * 405: 405EX + * 440/460: 440SP/440SPe/460EX/460GT * * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. @@ -2078,7 +2081,7 @@ static void program_bxcf(unsigned long *dimm_populated, if (num_banks == 4) ind = 0; else - ind = 5; + ind = 5 << 8; switch (num_col_addr) { case 0x08: mode |= (SDRAM_BXCF_M_AM_0 + ind); diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index 31f408d..1cdb709 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -166,17 +166,13 @@ _start_armboot: .word start_armboot /* */ /****************************************************************************/ /* mk@tbd: Fix this! */ -#if defined(CONFIG_PXA250) || defined(CONFIG_CPU_MONAHANS) +#undef RCSR #undef ICMR #undef OSMR3 #undef OSCR #undef OWER #undef OIER -#endif /* CONFIG_PXA250 || CONFIG_CPU_MONAHANS */ -#ifdef CONFIG_PXA250 -#undef RCSR #undef CCCR -#endif /* CONFIG_PXA250 */ /* Interrupt-Controller base address */ IC_BASE: .word 0x40d00000 |