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-rw-r--r--cpu/arm920t/s3c24x0/usb_ohci.c4
-rw-r--r--cpu/arm926ejs/davinci/timer.c70
-rw-r--r--cpu/mpc5xxx/usb_ohci.c4
-rw-r--r--cpu/mpc83xx/start.S11
-rw-r--r--cpu/mpc85xx/cpu.c13
-rw-r--r--cpu/mpc85xx/fdt.c2
-rw-r--r--cpu/mpc85xx/speed.c31
-rw-r--r--cpu/ppc4xx/usb_ohci.c4
8 files changed, 70 insertions, 69 deletions
diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c
index 4075f2e..96e43d0 100644
--- a/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/cpu/arm920t/s3c24x0/usb_ohci.c
@@ -58,8 +58,8 @@
#define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-#define readl(a) (*((vu_long *)(a)))
-#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
+#define readl(a) (*((volatile u32 *)(a)))
+#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c
index 8bb8b45..6c670f0 100644
--- a/cpu/arm926ejs/davinci/timer.c
+++ b/cpu/arm926ejs/davinci/timer.c
@@ -42,9 +42,9 @@
typedef volatile struct {
u_int32_t pid12;
- u_int32_t emumgt_clksped;
- u_int32_t gpint_en;
- u_int32_t gpdir_dat;
+ u_int32_t emumgt;
+ u_int32_t na1;
+ u_int32_t na2;
u_int32_t tim12;
u_int32_t tim34;
u_int32_t prd12;
@@ -52,21 +52,12 @@ typedef volatile struct {
u_int32_t tcr;
u_int32_t tgcr;
u_int32_t wdtcr;
- u_int32_t tlgc;
- u_int32_t tlmr;
} davinci_timer;
davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE;
#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ)
-#define READ_TIMER timer->tim34
-
-/*
- * Timer runs with CFG_HZ_CLOCK, currently 27MHz. To avoid wrap
- * around of timestamp already after min ~159s, divide it, e.g. by 16.
- * timestamp will then wrap around all min ~42min
- */
-#define DIV(x) ((x) >> 4)
+#define TIM_CLK_DIV 16
static ulong timestamp;
static ulong lastinc;
@@ -76,63 +67,51 @@ int timer_init(void)
/* We are using timer34 in unchained 32-bit mode, full speed */
timer->tcr = 0x0;
timer->tgcr = 0x0;
- timer->tgcr = 0x06;
+ timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8);
timer->tim34 = 0x0;
timer->prd34 = TIMER_LOAD_VAL;
lastinc = 0;
- timer->tcr = 0x80 << 16;
timestamp = 0;
+ timer->tcr = 2 << 22;
return(0);
}
void reset_timer(void)
{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- return(get_timer_masked() - base);
-}
-
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
-void udelay(unsigned long usec)
-{
- udelay_masked(usec);
-}
-
-void reset_timer_masked(void)
-{
- lastinc = DIV(READ_TIMER);
+ timer->tcr = 0x0;
+ timer->tim34 = 0;
+ lastinc = 0;
timestamp = 0;
+ timer->tcr = 2 << 22;
}
-ulong get_timer_raw(void)
+static ulong get_timer_raw(void)
{
- ulong now = DIV(READ_TIMER);
+ ulong now = timer->tim34;
if (now >= lastinc) {
/* normal mode */
timestamp += now - lastinc;
} else {
/* overflow ... */
- timestamp += now + DIV(TIMER_LOAD_VAL) - lastinc;
+ timestamp += now + TIMER_LOAD_VAL - lastinc;
}
lastinc = now;
return timestamp;
}
-ulong get_timer_masked(void)
+ulong get_timer(ulong base)
+{
+ return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base);
+}
+
+void set_timer(ulong t)
{
- return(get_timer_raw() / DIV(TIMER_LOAD_VAL));
+ timestamp = t;
}
-void udelay_masked(unsigned long usec)
+void udelay(unsigned long usec)
{
ulong tmo;
ulong endtime;
@@ -140,7 +119,7 @@ void udelay_masked(unsigned long usec)
tmo = CFG_HZ_CLOCK / 1000;
tmo *= usec;
- tmo /= 1000;
+ tmo /= (1000 * TIM_CLK_DIV);
endtime = get_timer_raw() + tmo;
@@ -165,8 +144,5 @@ unsigned long long get_ticks(void)
*/
ulong get_tbclk(void)
{
- ulong tbclk;
-
- tbclk = CFG_HZ;
- return(tbclk);
+ return CFG_HZ;
}
diff --git a/cpu/mpc5xxx/usb_ohci.c b/cpu/mpc5xxx/usb_ohci.c
index c774da3..2ad12b2 100644
--- a/cpu/mpc5xxx/usb_ohci.c
+++ b/cpu/mpc5xxx/usb_ohci.c
@@ -56,8 +56,8 @@
#define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-#define readl(a) (*((vu_long *)(a)))
-#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
+#define readl(a) (*((volatile u32 *)(a)))
+#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index fdf9d35..309eb30 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -172,11 +172,8 @@ boot_warm: /* time t 5 */
/* there and deflate the flash size back to minimal size */
/*------------------------------------------------------------*/
bl map_flash_by_law1
-
- GET_GOT /* initialize GOT access */
- lwz r4, GOT(_start)
- addi r4, r4, -EXC_OFF_SYS_RESET
-
+ lis r4, (CFG_MONITOR_BASE)@h
+ ori r4, r4, (CFG_MONITOR_BASE)@l
addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r5
blr
@@ -875,8 +872,8 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lwz r4, GOT(_start)
- addi r4, r4, -EXC_OFF_SYS_RESET
+ lis r4, CFG_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CFG_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index dcd8817..74b210c 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -116,22 +116,21 @@ int checkcpu (void)
get_sys_info(&sysinfo);
puts("Clock Configuration:\n");
- printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
- printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
-
+ printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
+ printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
switch (ddr_ratio) {
case 0x0:
printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
- sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000);
+ DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
break;
case 0x7:
printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
- sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000);
+ DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
break;
default:
printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
- sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000);
+ DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
break;
}
@@ -154,7 +153,7 @@ int checkcpu (void)
clkdiv *= 2;
#endif
printf("LBC:%4lu MHz\n",
- sysinfo.freqSystemBus / 1000000 / clkdiv);
+ DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
} else {
printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
}
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index bde6d1e..bb87740 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -52,7 +52,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
if (*reg == id) {
fdt_setprop_string(blob, off, "status", "okay");
} else {
- u32 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
+ u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
val = cpu_to_fdt32(val);
fdt_setprop_string(blob, off, "status",
"disabled");
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index d90d397..699441b4 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -65,6 +65,9 @@ void get_sys_info (sys_info_t * sysInfo)
int get_clocks (void)
{
sys_info_t sys_info;
+#ifdef CONFIG_MPC8544
+ volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR;
+#endif
#if defined(CONFIG_CPM2)
volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
uint sccr, dfbrg;
@@ -78,8 +81,34 @@ int get_clocks (void)
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
gd->mem_clk = sys_info.freqDDRBus;
+
+ /*
+ * The base clock for I2C depends on the actual SOC. Unfortunately,
+ * there is no pattern that can be used to determine the frequency, so
+ * the only choice is to look up the actual SOC number and use the value
+ * for that SOC. This information is taken from application note
+ * AN2919.
+ */
+#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+ defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
gd->i2c1_clk = sys_info.freqSystemBus;
- gd->i2c2_clk = sys_info.freqSystemBus;
+#elif defined(CONFIG_MPC8544)
+ /*
+ * On the 8544, the I2C clock is the same as the SEC clock. This can be
+ * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
+ * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
+ * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
+ * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
+ */
+ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
+ gd->i2c1_clk = sys_info.freqSystemBus / 3;
+ else
+ gd->i2c1_clk = sys_info.freqSystemBus / 2;
+#else
+ /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
+ gd->i2c1_clk = sys_info.freqSystemBus / 2;
+#endif
+ gd->i2c2_clk = gd->i2c1_clk;
#if defined(CONFIG_CPM2)
gd->vco_out = 2*sys_info.freqSystemBus;
diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c
index c71a6a9..7dbb288 100644
--- a/cpu/ppc4xx/usb_ohci.c
+++ b/cpu/ppc4xx/usb_ohci.c
@@ -56,8 +56,8 @@
#define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-#define readl(a) (*((vu_long *)(a)))
-#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
+#define readl(a) (*((volatile u32 *)(a)))
+#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
generated by cgit v1.1 at 2024-11-01 16:53:32 +0000