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-rw-r--r--cpu/mpc83xx/cpu_init.c7
-rw-r--r--cpu/mpc83xx/speed.c10
-rw-r--r--cpu/mpc85xx/Makefile2
-rw-r--r--cpu/mpc85xx/cpu_init.c38
-rw-r--r--cpu/mpc85xx/spd_sdram.c28
-rw-r--r--cpu/mpc85xx/start.S147
-rw-r--r--cpu/mpc85xx/tlb.c93
-rw-r--r--cpu/sh3/Makefile49
-rw-r--r--cpu/sh3/cache.c112
-rw-r--r--cpu/sh3/config.mk31
-rw-r--r--cpu/sh3/cpu.c84
-rw-r--r--cpu/sh3/interrupts.c42
-rw-r--r--cpu/sh3/start.S77
-rw-r--r--cpu/sh3/time.c103
-rw-r--r--cpu/sh3/watchdog.c33
15 files changed, 739 insertions, 117 deletions
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 3337d8c..e643037 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -73,11 +73,6 @@ void cpu_init_f (volatile immap_t * im)
(CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
#endif
-#ifdef CFG_SPCR_TSECEP
- /* eTSEC Emergency priority */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
-#endif
-
#ifdef CFG_ACR_RPTCNT
/* Arbiter repeat count */
im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
@@ -85,7 +80,7 @@ void cpu_init_f (volatile immap_t * im)
#endif
#ifdef CFG_SPCR_TSECEP
- /* all TSEC's Emergency priority */
+ /* all eTSEC's Emergency priority */
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
(CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
#endif
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 61c9379..f598699 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -367,17 +367,17 @@ int get_clocks(void)
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
- switch ((sccr & SCCR_SATACM) >> SCCR_SATACM_SHIFT) {
- case SCCR_SATACM_0:
+ switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
+ case 0:
sata_clk = 0;
break;
- case SCCR_SATACM_1:
+ case 1:
sata_clk = csb_clk;
break;
- case SCCR_SATACM_2:
+ case 2:
sata_clk = csb_clk / 2;
break;
- case SCCR_SATACM_3:
+ case 3:
sata_clk = csb_clk / 3;
break;
default:
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index d179d70..2205dca 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -30,7 +30,7 @@ LIB = $(obj)lib$(CPU).a
START = start.o resetvec.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
-COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
+COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \
$(COBJS-y)
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index fdb9ecb..c0ff1d5 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -31,6 +31,8 @@
#include <asm/processor.h>
#include <ioports.h>
#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -122,6 +124,34 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
}
#endif
+/* We run cpu_init_early_f in AS = 1 */
+void cpu_init_early_f(void)
+{
+ set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 1, 0, BOOKE_PAGESZ_4K, 0);
+
+ /* set up CCSR if we want it moved */
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ {
+ u32 temp;
+
+ set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 1, 1, BOOKE_PAGESZ_4K, 0);
+
+ temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT);
+ out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR >> 12);
+
+ temp = in_be32((volatile u32 *)CFG_CCSRBAR);
+ }
+#endif
+
+ init_laws();
+ invalidate_tlb(0);
+ init_tlbs();
+}
+
/*
* Breathe some life into the CPU...
*
@@ -134,13 +164,15 @@ void cpu_init_f (void)
volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
extern void m8560_cpm_reset (void);
+ disable_tlb(14);
+ disable_tlb(15);
+
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
-
#ifdef CONFIG_CPM2
config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
#endif
@@ -222,11 +254,15 @@ void cpu_init_f (void)
int cpu_init_r(void)
{
#ifdef CONFIG_CLEAR_LAW0
+#ifdef CONFIG_FSL_LAW
+ disable_law(0);
+#else
volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
/* clear alternate boot location LAW (used for sdram, or ddr bank) */
ecm->lawar0 = 0;
#endif
+#endif
#if defined(CONFIG_L2_CACHE)
volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index adc9c4d..abc63c4 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -27,6 +27,7 @@
#include <i2c.h>
#include <spd.h>
#include <asm/mmu.h>
+#include <asm/fsl_law.h>
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
@@ -1022,7 +1023,6 @@ spd_sdram(void)
static unsigned int
setup_laws_and_tlbs(unsigned int memsize)
{
- volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
unsigned int tlb_size;
unsigned int law_size;
unsigned int ram_tlb_index;
@@ -1071,19 +1071,9 @@ setup_laws_and_tlbs(unsigned int memsize)
ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
while (ram_tlb_address < (memsize * 1024 * 1024)
&& ram_tlb_index < 16) {
- mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
- mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
- mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0));
- mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR)));
- asm volatile("isync;msync;tlbwe;isync");
-
- debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
- debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
- debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0));
- debug("DDR: MAS3=0x%08x\n",
- FSL_BOOKE_MAS3(ram_tlb_address, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR)));
+ set_tlb(1, ram_tlb_address, ram_tlb_address,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, ram_tlb_index, tlb_size, 1);
ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
ram_tlb_index++;
@@ -1098,12 +1088,10 @@ setup_laws_and_tlbs(unsigned int memsize)
/*
* Set up LAWBAR for all of DDR.
*/
- ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
- ecm->lawar1 = (LAWAR_EN
- | LAWAR_TRGT_IF_DDR
- | (LAWAR_SIZE & law_size));
- debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1);
- debug("DDR: LARAR1=0x%08x\n", ecm->lawar1);
+
+#ifdef CONFIG_FSL_LAW
+ set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
+#endif
/*
* Confirm that the requested amount of memory was mapped.
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index b489d2f..e8e5eb2 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -143,84 +143,8 @@ _start_e500:
li r1,0x0f00
mtspr IVOR15,r1 /* 15: Debug */
-
- /*
- * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
- * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
- * region before we can access any CCSR registers such as L2
- * registers, Local Access Registers,etc. We will also re-allocate
- * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
- *
- * Please refer to board-specif directory for TLB1 entry configuration.
- * (e.g. board/<yourboard>/init.S)
- *
- */
- bl tlb1_entry
- mr r5,r0
- lwzu r4,0(r5) /* how many TLB1 entries we actually use */
- mtctr r4
-
-0: lwzu r6,4(r5)
- lwzu r7,4(r5)
- lwzu r8,4(r5)
- lwzu r9,4(r5)
- mtspr MAS0,r6
- mtspr MAS1,r7
- mtspr MAS2,r8
- mtspr MAS3,r9
- isync
- msync
- tlbwe
- isync
- bdnz 0b
-
-1:
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
- /* Special sequence needed to update CCSRBAR itself */
- lis r4,CFG_CCSRBAR_DEFAULT@h
- ori r4,r4,CFG_CCSRBAR_DEFAULT@l
-
- lis r5,CFG_CCSRBAR@h
- ori r5,r5,CFG_CCSRBAR@l
- srwi r6,r5,12
- stw r6,0(r4)
- isync
-
- lis r5,0xffff
- ori r5,r5,0xf000
- lwz r5,0(r5)
- isync
-
- lis r3,CFG_CCSRBAR@h
- lwz r5,CFG_CCSRBAR@l(r3)
- isync
-#endif
-
-
- /* set up local access windows, defined at board/<boardname>/init.S */
- lis r7,CFG_CCSRBAR@h
- ori r7,r7,CFG_CCSRBAR@l
-
- bl law_entry
- mr r6,r0
- lwzu r5,0(r6) /* how many windows we actually use */
- mtctr r5
-
- li r2,0x0c28 /* the first pair is reserved for */
- li r1,0x0c30 /* boot-over-rio-or-pci */
-
-0: lwzu r4,4(r6)
- lwzu r3,4(r6)
- stwx r4,r7,r2
- stwx r3,r7,r1
- addi r2,r2,0x0020
- addi r1,r1,0x0020
- bdnz 0b
-
/* Clear and set up some registers. */
- li r0,0
- mtmsr r0
- li r0,0x0000
+ li r0,0x0000
lis r1,0xffff
mtspr DEC,r0 /* prevent dec exceptions */
mttbl r0 /* prevent fit & wdt exceptions */
@@ -230,18 +154,13 @@ _start_e500:
mtspr ESR,r0 /* clear exception syndrome register */
mtspr MCSR,r0 /* machine check syndrome register */
mtxer r0 /* clear integer exception register */
- lis r1,0x0002 /* set CE bit (Critical Exceptions) */
- ori r1,r1,0x1200 /* set ME/DE bit */
- mtmsr r1 /* change MSR */
- isync
/* Enable Time Base and Select Time Base Clock */
lis r0,HID0_EMCP@h /* Enable machine check */
#if defined(CONFIG_ENABLE_36BIT_PHYS)
- ori r0,r0,(HID0_TBEN|HID0_ENMAS7)@l /* Enable Timebase & MAS7 */
-#else
- ori r0,r0,HID0_TBEN@l /* enable Timebase */
+ ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
#endif
+ ori r0,r0,HID0_TBEN@l /* Enable Timebase */
mtspr HID0,r0
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
@@ -262,6 +181,58 @@ _start_e500:
mtspr DBCR0,r0
#endif
+ /* create a temp mapping in AS=1 to the boot window */
+ lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
+ ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
+
+ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h
+ ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l
+
+ lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
+ ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
+
+ lis r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori r9,r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+
+ mtspr MAS0,r6
+ mtspr MAS1,r7
+ mtspr MAS2,r8
+ mtspr MAS3,r9
+ isync
+ msync
+ tlbwe
+
+ /* create a temp mapping in AS=1 to the stack */
+ lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
+ ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
+
+ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
+ ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
+
+ lis r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@h
+ ori r8,r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@l
+
+ lis r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori r9,r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+
+ mtspr MAS0,r6
+ mtspr MAS1,r7
+ mtspr MAS2,r8
+ mtspr MAS3,r9
+ isync
+ msync
+ tlbwe
+
+ lis r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h
+ ori r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l
+ lis r7,switch_as@h
+ ori r7,r7,switch_as@l
+
+ mtspr SPRN_SRR0,r7
+ mtspr SPRN_SRR1,r6
+ rfi
+
+switch_as:
/* L1 DCache is used for initial RAM */
/* Allocate Initial RAM in data cache.
@@ -321,6 +292,14 @@ _start_cont:
stw r0,+12(r1) /* Save return addr (underflow vect) */
GET_GOT
+ bl cpu_init_early_f
+
+ /* switch back to AS = 0 */
+ lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
+ ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
+ mtmsr r3
+ isync
+
bl cpu_init_f
bl board_init_f
isync
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
new file mode 100644
index 0000000..b2c799a
--- /dev/null
+++ b/cpu/mpc85xx/tlb.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+void set_tlb(u8 tlb, u32 epn, u64 rpn,
+ u8 perms, u8 wimge,
+ u8 ts, u8 esel, u8 tsize, u8 iprot)
+{
+ u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+
+ _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
+ _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
+ _mas2 = FSL_BOOKE_MAS2(epn, wimge);
+ _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
+ _mas7 = rpn >> 32;
+
+ mtspr(MAS0, _mas0);
+ mtspr(MAS1, _mas1);
+ mtspr(MAS2, _mas2);
+ mtspr(MAS3, _mas3);
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+ mtspr(MAS7, _mas7);
+#endif
+ asm volatile("isync;msync;tlbwe;isync");
+}
+
+void disable_tlb(u8 esel)
+{
+ u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+
+ _mas0 = FSL_BOOKE_MAS0(1, esel, 0);
+ _mas1 = 0;
+ _mas2 = 0;
+ _mas3 = 0;
+ _mas7 = 0;
+
+ mtspr(MAS0, _mas0);
+ mtspr(MAS1, _mas1);
+ mtspr(MAS2, _mas2);
+ mtspr(MAS3, _mas3);
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+ mtspr(MAS7, _mas7);
+#endif
+ asm volatile("isync;msync;tlbwe;isync");
+}
+
+void invalidate_tlb(u8 tlb)
+{
+ if (tlb == 0)
+ mtspr(MMUCSR0, 0x4);
+ if (tlb == 1)
+ mtspr(MMUCSR0, 0x2);
+}
+
+void init_tlbs(void)
+{
+ int i;
+
+ for (i = 0; i < num_tlb_entries; i++) {
+ set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn,
+ tlb_table[i].perms, tlb_table[i].wimge,
+ tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize,
+ tlb_table[i].iprot);
+ }
+
+ return ;
+}
+
diff --git a/cpu/sh3/Makefile b/cpu/sh3/Makefile
new file mode 100644
index 0000000..7679248
--- /dev/null
+++ b/cpu/sh3/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# (C) Copyright 2007
+# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).a
+
+START = start.o
+OBJS = cpu.o interrupts.o watchdog.o time.o cache.o
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/cpu/sh3/cache.c b/cpu/sh3/cache.c
new file mode 100644
index 0000000..c294a2b
--- /dev/null
+++ b/cpu/sh3/cache.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * (C) Copyright 2007
+ * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+/*
+ * Jump to P2 area.
+ * When handling TLB or caches, we need to do it from P2 area.
+ */
+#define jump_to_P2() \
+ do { \
+ unsigned long __dummy; \
+ __asm__ __volatile__( \
+ "mov.l 1f, %0\n\t" \
+ "or %1, %0\n\t" \
+ "jmp @%0\n\t" \
+ " nop\n\t" \
+ ".balign 4\n" \
+ "1: .long 2f\n" \
+ "2:" \
+ : "=&r" (__dummy) \
+ : "r" (0x20000000)); \
+ } while (0)
+
+/*
+ * Back to P1 area.
+ */
+#define back_to_P1() \
+ do { \
+ unsigned long __dummy; \
+ __asm__ __volatile__( \
+ "nop;nop;nop;nop;nop;nop;nop\n\t" \
+ "mov.l 1f, %0\n\t" \
+ "jmp @%0\n\t" \
+ " nop\n\t" \
+ ".balign 4\n" \
+ "1: .long 2f\n" \
+ "2:" \
+ : "=&r" (__dummy)); \
+ } while (0)
+
+#define CACHE_VALID 1
+#define CACHE_UPDATED 2
+
+static inline void cache_wback_all(void)
+{
+ unsigned long addr, data, i, j;
+
+ jump_to_P2();
+ for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
+ for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
+ addr = CACHE_OC_ADDRESS_ARRAY
+ | (j << CACHE_OC_WAY_SHIFT)
+ | (i << CACHE_OC_ENTRY_SHIFT);
+ data = inl(addr);
+ if (data & CACHE_UPDATED) {
+ data &= ~CACHE_UPDATED;
+ outl(data, addr);
+ }
+ }
+ }
+ back_to_P1();
+}
+
+
+#define CACHE_ENABLE 0
+#define CACHE_DISABLE 1
+
+int cache_control(unsigned int cmd)
+{
+ unsigned long ccr;
+
+ jump_to_P2();
+ ccr = inl(CCR);
+
+ if (ccr & CCR_CACHE_ENABLE)
+ cache_wback_all();
+
+ if (cmd == CACHE_DISABLE)
+ outl(CCR_CACHE_STOP, CCR);
+ else
+ outl(CCR_CACHE_INIT, CCR);
+ back_to_P1();
+
+ return 0;
+}
diff --git a/cpu/sh3/config.mk b/cpu/sh3/config.mk
new file mode 100644
index 0000000..f2da368
--- /dev/null
+++ b/cpu/sh3/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# (C) Copyright 2007
+# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+PLATFORM_CPPFLAGS += -m3
+PLATFORM_RELFLAGS += -ffixed-r13
diff --git a/cpu/sh3/cpu.c b/cpu/sh3/cpu.c
new file mode 100644
index 0000000..8261d29
--- /dev/null
+++ b/cpu/sh3/cpu.c
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+int checkcpu(void)
+{
+ puts("CPU: SH3\n");
+ return 0;
+}
+
+int cpu_init(void)
+{
+ return 0;
+}
+
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+ return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ disable_interrupts();
+ reset_cpu(0);
+ return 0;
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+
+}
+
+void icache_enable(void)
+{
+}
+
+void icache_disable(void)
+{
+}
+
+int icache_status(void)
+{
+ return 0;
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+ return 0;
+}
diff --git a/cpu/sh3/interrupts.c b/cpu/sh3/interrupts.c
new file mode 100644
index 0000000..55284cc
--- /dev/null
+++ b/cpu/sh3/interrupts.c
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int interrupt_init(void)
+{
+ return 0;
+}
+
+void enable_interrupts(void)
+{
+
+}
+
+int disable_interrupts(void)
+{
+ return 0;
+}
diff --git a/cpu/sh3/start.S b/cpu/sh3/start.S
new file mode 100644
index 0000000..ee0bcdf
--- /dev/null
+++ b/cpu/sh3/start.S
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+ .text
+ .align 2
+
+ .global _start
+_start:
+ mov.l ._lowlevel_init, r0
+100: bsrf r0
+ nop
+
+ bsr 1f
+ nop
+1: sts pr, r5
+ mov.l ._reloc_dst, r4
+ add #(_start-1b), r5
+ mov.l ._reloc_dst_end, r6
+
+2: mov.l @r5+, r1
+ mov.l r1, @r4
+ add #4, r4
+ cmp/hs r6, r4
+ bf 2b
+
+ mov.l ._bss_start, r4
+ mov.l ._bss_end, r5
+ mov #0, r1
+
+3: mov.l r1, @r4 /* bss clear */
+ add #4, r4
+ cmp/hs r5, r4
+ bf 3b
+
+ mov.l ._gd_init, r13 /* global data */
+ mov.l ._stack_init, r15 /* stack */
+
+ mov.l ._sh_generic_init, r0
+ jsr @r0
+ nop
+
+loop:
+ bra loop
+
+ .align 2
+
+._lowlevel_init: .long (lowlevel_init - (100b + 4))
+._reloc_dst: .long reloc_dst
+._reloc_dst_end: .long reloc_dst_end
+._bss_start: .long bss_start
+._bss_end: .long bss_end
+._gd_init: .long (_start - CFG_GBL_DATA_SIZE)
+._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16)
+._sh_generic_init: .long sh_generic_init
diff --git a/cpu/sh3/time.c b/cpu/sh3/time.c
new file mode 100644
index 0000000..0c273dd
--- /dev/null
+++ b/cpu/sh3/time.c
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * (C) Copyright 2007
+ * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#define TMU_MAX_COUNTER (~0UL)
+
+static void tmu_timer_start(unsigned int timer)
+{
+ if (timer > 2)
+ return;
+
+ outb(inb(TSTR) | (1 << timer), TSTR);
+}
+
+static void tmu_timer_stop(unsigned int timer)
+{
+ u8 val = inb(TSTR);
+
+ if (timer > 2)
+ return;
+ outb(val & ~(1 << timer), TSTR);
+}
+
+int timer_init(void)
+{
+ /* Divide clock by 4 */
+ outw(0, TCR0);
+
+ tmu_timer_stop(0);
+ tmu_timer_start(0);
+ return 0;
+}
+
+/*
+ In theory we should return a true 64bit value (ie something that doesn't
+ overflow). However, we don't. Therefore if TMU runs at fastest rate of
+ 6.75 MHz this value will wrap after u-boot has been running for approx
+ 10 minutes.
+*/
+unsigned long long get_ticks(void)
+{
+ return (0 - inl(TCNT0));
+}
+
+unsigned long get_timer(unsigned long base)
+{
+ return ((0 - inl(TCNT0)) - base);
+}
+
+void set_timer(unsigned long t)
+{
+ outl(0 - t, TCNT0);
+}
+
+void reset_timer(void)
+{
+ tmu_timer_stop(0);
+ set_timer(0);
+ tmu_timer_start(0);
+}
+
+void udelay(unsigned long usec)
+{
+ unsigned int start = get_timer(0);
+ unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000));
+
+ while (get_timer(0) < end)
+ continue;
+}
+
+unsigned long get_tbclk(void)
+{
+ return CFG_HZ;
+}
diff --git a/cpu/sh3/watchdog.c b/cpu/sh3/watchdog.c
new file mode 100644
index 0000000..92bea74
--- /dev/null
+++ b/cpu/sh3/watchdog.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+int watchdog_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(unsigned long ignored)
+{
+ while (1)
+ ;
+}
generated by cgit v1.1 at 2025-01-03 15:40:39 +0000