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-rw-r--r--cpu/mpc512x/diu.c1
-rw-r--r--cpu/mpc85xx/Makefile4
-rw-r--r--cpu/mpc85xx/release.S12
-rw-r--r--cpu/mpc85xx/start.S14
-rw-r--r--cpu/mpc8xxx/cpu.c10
-rw-r--r--cpu/mpc8xxx/ddr/ctrl_regs.c26
-rw-r--r--cpu/mpc8xxx/ddr/options.c14
-rw-r--r--cpu/mpc8xxx/pci_cfg.c30
8 files changed, 88 insertions, 23 deletions
diff --git a/cpu/mpc512x/diu.c b/cpu/mpc512x/diu.c
index ca459a1..c2453c6 100644
--- a/cpu/mpc512x/diu.c
+++ b/cpu/mpc512x/diu.c
@@ -27,7 +27,6 @@
#include <command.h>
#include <asm/io.h>
-#include "../../board/freescale/common/pixis.h"
#include "../../board/freescale/common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index 56de7eb..f064fee 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -50,7 +50,11 @@ COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
COBJS-$(CONFIG_P1011) += ddr-gen3.o
+COBJS-$(CONFIG_P1012) += ddr-gen3.o
+COBJS-$(CONFIG_P1013) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
+COBJS-$(CONFIG_P1021) += ddr-gen3.o
+COBJS-$(CONFIG_P1022) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index dab784e..0b5b9da 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
* Kumar Gala <kumar.gala@freescale.com>
*
* See file CREDITS for list of people who contributed to this
@@ -57,11 +57,19 @@ __secondary_start_page:
#ifndef CONFIG_E500MC
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
+ mfspr r0,PVR
+ andi. r0,r0,0xff
+ cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
+ blt 1f
+ /* Set MBDD bit also */
+ ori r3, r3, HID1_MBDD@l
+1:
mtspr SPRN_HID1,r3
#endif
/* Enable branch prediction */
- li r3,0x201
+ lis r3,BUCSR_ENABLE@h
+ ori r3,r3,BUCSR_ENABLE@l
mtspr SPRN_BUCSR,r3
/* Ensure TB is 0 */
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index af18c1c..b3cb56a 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -1,5 +1,5 @@
/*
- * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc.
*
* See file CREDITS for list of people who contributed to this
@@ -208,13 +208,21 @@ _start_e500:
#ifndef CONFIG_E500MC
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
+ mfspr r3,PVR
+ andi. r3,r3, 0xff
+ cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
+ blt 1f
+ /* Set MBDD bit also */
+ ori r0, r0, HID1_MBDD@l
+1:
mtspr HID1,r0
#endif
/* Enable Branch Prediction */
#if defined(CONFIG_BTB)
- li r0,0x201 /* BBFI = 1, BPEN = 1 */
- mtspr BUCSR,r0
+ lis r0,BUCSR_ENABLE@h
+ ori r0,r0,BUCSR_ENABLE@l
+ mtspr SPRN_BUCSR,r0
#endif
#if defined(CONFIG_SYS_INIT_DBCR)
diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c
index d191263..47842e9 100644
--- a/cpu/mpc8xxx/cpu.c
+++ b/cpu/mpc8xxx/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c.
* Basically this file contains cpu specific common code for 85xx/86xx
@@ -66,8 +66,16 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8572, 8572_E, 2),
CPU_TYPE_ENTRY(P1011, P1011, 1),
CPU_TYPE_ENTRY(P1011, P1011_E, 1),
+ CPU_TYPE_ENTRY(P1012, P1012, 1),
+ CPU_TYPE_ENTRY(P1012, P1012_E, 1),
+ CPU_TYPE_ENTRY(P1013, P1013, 1),
+ CPU_TYPE_ENTRY(P1013, P1013_E, 1),
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1020, P1020_E, 2),
+ CPU_TYPE_ENTRY(P1021, P1021, 2),
+ CPU_TYPE_ENTRY(P1021, P1021_E, 2),
+ CPU_TYPE_ENTRY(P1022, P1022, 2),
+ CPU_TYPE_ENTRY(P1022, P1022_E, 2),
CPU_TYPE_ENTRY(P2010, P2010, 1),
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index adc4f6e..03f9c43 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1,9 +1,10 @@
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
*/
/*
@@ -934,7 +935,8 @@ static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
}
/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
-static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
+static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts)
{
unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
@@ -943,9 +945,15 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
#if defined(CONFIG_FSL_DDR3)
- /* We need set BL/2 + 4 for BC4 or OTF */
- rrt = 4; /* BL/2 + 4 clocks */
- wwt = 4; /* BL/2 + 4 clocks */
+ if (popts->burst_length == DDR_BL8) {
+ /* We set BL/2 for fixed BL8 */
+ rrt = 0; /* BL/2 clocks */
+ wwt = 0; /* BL/2 clocks */
+ } else {
+ /* We need to set BL/2 + 2 to BC4 and OTF */
+ rrt = 2; /* BL/2 + 2 clocks */
+ wwt = 2; /* BL/2 + 2 clocks */
+ }
dll_lock = 1; /* tDLLK = 512 clocks from spec */
#endif
ddr->timing_cfg_4 = (0
@@ -1343,7 +1351,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_ddr_sdram_clk_cntl(ddr, popts);
set_ddr_init_addr(ddr);
set_ddr_init_ext_addr(ddr);
- set_timing_cfg_4(ddr);
+ set_timing_cfg_4(ddr, popts);
set_timing_cfg_5(ddr);
set_ddr_zq_cntl(ddr, zq_en);
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 3dcd33d..46731c8 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -1,9 +1,10 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
*/
#include <common.h>
@@ -109,8 +110,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
/* Choose burst length. */
#if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_E500MC)
+ popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
+ popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
+#else
popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
+#endif
#else
popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
#endif
diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c
index d53781b..9b7181d 100644
--- a/cpu/mpc8xxx/pci_cfg.c
+++ b/cpu/mpc8xxx/pci_cfg.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -25,7 +25,7 @@
#include <pci.h>
struct pci_info {
- u16 cfg;
+ u32 cfg;
};
/* The cfg field is a bit mask in which each bit represents the value of
@@ -153,7 +153,8 @@ static struct pci_info pci_config_info[] =
(1 << 7) | (1 << 0xe) | (1 << 0xf),
},
};
-#elif defined(CONFIG_P1011) || defined(CONFIG_P1020)
+#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
+ defined(CONFIG_P1012) || defined(CONFIG_P1021)
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCIE_1] = {
@@ -163,6 +164,29 @@ static struct pci_info pci_config_info[] =
.cfg = (1 << 0xe),
},
};
+#elif defined(CONFIG_P1013) || defined(CONFIG_P1022)
+static struct pci_info pci_config_info[] =
+{
+ [LAW_TRGT_IF_PCIE_1] = {
+ .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) |
+ (1 << 0xb) | (1 << 0xd) | (1 << 0xe) |
+ (1 << 0xf) | (1 << 0x15) | (1 << 0x16) |
+ (1 << 0x17) | (1 << 0x18) | (1 << 0x19) |
+ (1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) |
+ (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
+ },
+ [LAW_TRGT_IF_PCIE_2] = {
+ .cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) |
+ (1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) |
+ (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
+ (1 << 0x18) | (1 << 0x1c),
+ },
+ [LAW_TRGT_IF_PCIE_3] = {
+ .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) |
+ (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) |
+ (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
+ },
+};
#elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
static struct pci_info pci_config_info[] =
{
generated by cgit v1.1 at 2024-12-03 04:29:22 +0000