summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'cpu')
-rw-r--r--cpu/ixp/npe/npe.c8
-rw-r--r--cpu/mpc85xx/fdt.c5
-rw-r--r--cpu/mpc85xx/spd_sdram.c23
-rw-r--r--cpu/mpc85xx/start.S9
-rw-r--r--cpu/mpc8xx/fec.c4
-rw-r--r--cpu/ppc4xx/4xx_pci.c2
-rw-r--r--cpu/pxa/start.S38
-rw-r--r--cpu/pxa/usb.c16
8 files changed, 63 insertions, 42 deletions
diff --git a/cpu/ixp/npe/npe.c b/cpu/ixp/npe/npe.c
index 7e4af44..a33b956 100644
--- a/cpu/ixp/npe/npe.c
+++ b/cpu/ixp/npe/npe.c
@@ -408,25 +408,25 @@ static int npe_init(struct eth_device *dev, bd_t * bis)
if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback,
(u32)p_npe) != IX_ETH_ACC_SUCCESS) {
printf("can't register RX callback!\n");
- return 0;
+ return -1;
}
if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback,
(u32)p_npe) != IX_ETH_ACC_SUCCESS) {
printf("can't register TX callback!\n");
- return 0;
+ return -1;
}
npe_set_mac_address(dev);
if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) {
printf("can't enable port!\n");
- return 0;
+ return -1;
}
p_npe->active = 1;
- return 1;
+ return 0;
}
#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 737a6c4..0ce17e7 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -43,8 +43,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
#ifdef CONFIG_QE
- do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+ do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
"bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
+ "brg-frequency", bd->bi_busfreq / 2, 1);
+ fdt_fixup_qe_firmware(blob);
#endif
#ifdef CFG_NS16550
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 553f736..adc9c4d 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -1071,22 +1071,19 @@ setup_laws_and_tlbs(unsigned int memsize)
ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
while (ram_tlb_address < (memsize * 1024 * 1024)
&& ram_tlb_index < 16) {
- mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
- mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
- mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
- 0, 0, 0, 0, 0, 0, 0, 0));
- mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
- 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+ mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
+ mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
+ mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0));
+ mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR)));
asm volatile("isync;msync;tlbwe;isync");
- debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
- debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
- debug("DDR: MAS2=0x%08x\n",
- TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
- 0, 0, 0, 0, 0, 0, 0, 0));
+ debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
+ debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
+ debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0));
debug("DDR: MAS3=0x%08x\n",
- TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
- 0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
+ FSL_BOOKE_MAS3(ram_tlb_address, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR)));
ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
ram_tlb_index++;
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index b769ef8..b489d2f 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -268,7 +268,10 @@ _start_e500:
*/
lis r3,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
- li r2,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
+ mfspr r2, L1CFG0
+ andi. r2, r2, 0x1ff
+ /* cache size * 1024 / (2 * L1 line size) */
+ slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
mtctr r2
li r0,0
1:
@@ -1061,7 +1064,9 @@ unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
- li r4,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
+ mfspr r4,L1CFG0
+ andi. r4,r4,0x1ff
+ slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: icbi r0,r3
dcbi r0,r3
diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index da473ca..5a31413 100644
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -727,7 +727,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
if (efis->actual_phy_addr == -1) {
printf ("Unable to discover phy!\n");
- return 0;
+ return -1;
}
#else
efis->actual_phy_addr = -1;
@@ -763,7 +763,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
efis->initialized = 1;
- return 1;
+ return 0;
}
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index a68c419..a5b9690 100644
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -339,7 +339,7 @@ void pci_405gp_init(struct pci_controller *hose)
}
/*
- * drivers/pci.c skips every host bridge but the 405GP since it could
+ * drivers/pci/pci.c skips every host bridge but the 405GP since it could
* be set as an Adapter.
*
* I (Andrew May) don't know what we should do here, but I don't want
diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S
index b922485..31f408d 100644
--- a/cpu/pxa/start.S
+++ b/cpu/pxa/start.S
@@ -57,7 +57,7 @@ _fiq: .word fiq
* Startup Code (reset vector)
*
* do important init only if we don't start from RAM!
- * - relocate armboot to ram
+ * - relocate armboot to RAM
* - setup stack
* - jump to second stage
*/
@@ -90,7 +90,7 @@ IRQ_STACK_START:
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
-#endif
+#endif /* CONFIG_USE_IRQ */
/****************************************************************************/
@@ -100,18 +100,18 @@ FIQ_STACK_START:
/****************************************************************************/
reset:
- mrs r0,cpsr /* set the cpu to SVC32 mode */
+ mrs r0,cpsr /* set the CPU to SVC32 mode */
bic r0,r0,#0x1f /* (superviser mode, M=10011) */
orr r0,r0,#0x13
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
- * not when booting from ram!
+ * not when booting from RAM!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit /* we do sys-critical inits */
-#endif
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
@@ -130,7 +130,7 @@ copy_loop:
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
+#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
@@ -139,7 +139,7 @@ stack_setup:
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
+#endif /* CONFIG_USE_IRQ */
sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss:
@@ -172,11 +172,11 @@ _start_armboot: .word start_armboot
#undef OSCR
#undef OWER
#undef OIER
-#endif
+#endif /* CONFIG_PXA250 || CONFIG_CPU_MONAHANS */
#ifdef CONFIG_PXA250
#undef RCSR
#undef CCCR
-#endif
+#endif /* CONFIG_PXA250 */
/* Interrupt-Controller base address */
IC_BASE: .word 0x40d00000
@@ -197,18 +197,18 @@ OSTIMER_BASE: .word 0x40a00000
#ifdef CONFIG_CPU_MONAHANS
# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
-# endif
+# endif /* !CFG_MONAHANS_RUN_MODE_OSC_RATIO */
# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
-# endif
-#else /* ! CONFIG_CPU_MONAHANS */
+# endif /* !CFG_MONAHANS_TURBO_RUN_MODE_RATIO */
+#else /* !CONFIG_CPU_MONAHANS */
#ifdef CFG_CPUSPEED
CC_BASE: .word 0x41300000
#define CCCR 0x00
cpuspeed: .word CFG_CPUSPEED
-#else
+#else /* !CFG_CPUSPEED */
#error "You have to define CFG_CPUSPEED!!"
-#endif
+#endif /* CFG_CPUSPEED */
#endif /* CONFIG_CPU_MONAHANS */
/* takes care the CP15 update has taken place */
@@ -225,7 +225,7 @@ cpu_init_crit:
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
-#else
+#else /* CONFIG_CPU_MONAHANS */
/* Step 1 - Enable CP6 permission */
mrc p15, 0, r1, c15, c1, 0 @ read CPAR
orr r1, r1, #0x40
@@ -244,14 +244,14 @@ cpu_init_crit:
ldr r1, =CKENB
ldr r2, =(CKENB_6_IRQ)
str r2, [r1]
-#endif
+#endif /* !CONFIG_CPU_MONAHANS */
/* set clock speed */
#ifdef CONFIG_CPU_MONAHANS
ldr r0, =ACCR
ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
str r1, [r0]
-#else /* ! CONFIG_CPU_MONAHANS */
+#else /* !CONFIG_CPU_MONAHANS */
#ifdef CFG_CPUSPEED
ldr r0, CC_BASE
ldr r1, cpuspeed
@@ -451,7 +451,7 @@ fiq:
bl do_fiq /* effiction fiq_save_user_regs */
irq_restore_user_regs
-#else
+#else /* !CONFIG_USE_IRQ */
.align 5
irq:
@@ -465,7 +465,7 @@ fiq:
bad_save_user_regs
bl do_fiq
-#endif
+#endif /* CONFIG_USE_IRQ */
/****************************************************************************/
/* */
diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c
index 72b7dfa..aa6f4b7 100644
--- a/cpu/pxa/usb.c
+++ b/cpu/pxa/usb.c
@@ -89,6 +89,22 @@ int usb_cpu_stop(void)
int usb_cpu_init_fail(void)
{
+ UHCHR |= UHCHR_FHR;
+ udelay(11);
+ UHCHR &= ~UHCHR_FHR;
+
+ UHCCOMS |= 1;
+ udelay(10);
+
+#if defined(CONFIG_CPU_MONAHANS)
+ UHCHR |= UHCHR_SSEP0;
+#endif
+#if defined(CONFIG_PXA27X)
+ UHCHR |= UHCHR_SSEP2;
+#endif
+ UHCHR |= UHCHR_SSEP1;
+ UHCHR |= UHCHR_SSE;
+
return 0;
}
generated by cgit v1.1 at 2024-12-18 15:39:17 +0000