diff options
Diffstat (limited to 'cpu')
66 files changed, 1662 insertions, 1771 deletions
diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c index 9c8998b..ea43c9a 100644 --- a/cpu/74xx_7xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -44,8 +44,9 @@ #include <74xx_7xx.h> #include <asm/cache.h> -#if defined(CONFIG_OF_FLAT_TREE) -#include <ft_build.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#include <fdt_support.h> #endif #ifdef CONFIG_AMIGAONEG3SE @@ -301,29 +302,19 @@ watchdog_reset(void) /* ------------------------------------------------------------------------- */ -#ifdef CONFIG_OF_FLAT_TREE -void -ft_cpu_setup (void *blob, bd_t *bd) +#ifdef CONFIG_OF_LIBFDT +void ft_cpu_setup(void *blob, bd_t *bd) { - u32 *p; - ulong clock; - int len; - - clock = bd->bi_busfreq; + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", bd->bi_busfreq / 4, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", bd->bi_intfreq, 1); - p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len); - if (p != NULL) - *p = cpu_to_be32 (clock); + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -#if defined(CONFIG_TSI108_ETH) - p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6200/address", &len); - memcpy (p, bd->bi_enetaddr, 6); -#endif - -#if defined(CONFIG_HAS_ETH1) - p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6600/address", &len); - memcpy (p, bd->bi_enet1addr, 6); -#endif + fdt_fixup_ethernet(blob, bd); } #endif /* ------------------------------------------------------------------------- */ diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index b5834b9..42b0f72 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -316,7 +316,7 @@ invalidate_bats: mtspr IBAT1U, r0 mtspr IBAT2U, r0 mtspr IBAT3U, r0 -#ifdef CONFIG_750FX +#ifdef CONFIG_HIGH_BATS mtspr IBAT4U, r0 mtspr IBAT5U, r0 mtspr IBAT6U, r0 @@ -327,7 +327,7 @@ invalidate_bats: mtspr DBAT1U, r0 mtspr DBAT2U, r0 mtspr DBAT3U, r0 -#ifdef CONFIG_750FX +#ifdef CONFIG_HIGH_BATS mtspr DBAT4U, r0 mtspr DBAT5U, r0 mtspr DBAT6U, r0 @@ -414,7 +414,7 @@ setup_bats: mtspr DBAT3U, r3 isync -#ifdef CONFIG_750FX +#ifdef CONFIG_HIGH_BATS /* IBAT 4 */ addis r4, r0, CFG_IBAT4L@h ori r4, r4, CFG_IBAT4L@l diff --git a/cpu/arm1136/mx31/serial.c b/cpu/arm1136/mx31/serial.c index 1cad8f9..f498599 100644 --- a/cpu/arm1136/mx31/serial.c +++ b/cpu/arm1136/mx31/serial.c @@ -63,6 +63,7 @@ #define URXD_FRMERR (1<<12) #define URXD_BRK (1<<11) #define URXD_PRERR (1<<10) +#define URXD_RX_DATA (0xFF) #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ @@ -165,7 +166,7 @@ void serial_setbrg (void) int serial_getc (void) { while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); - return __REG(UART_PHYS + URXD); + return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ } void serial_putc (const char c) diff --git a/cpu/arm920t/at91rm9200/lxt972.c b/cpu/arm920t/at91rm9200/lxt972.c index 4edcc9a..260d393 100644 --- a/cpu/arm920t/at91rm9200/lxt972.c +++ b/cpu/arm920t/at91rm9200/lxt972.c @@ -29,6 +29,7 @@ #include <common.h> #include <at91rm9200_net.h> #include <net.h> +#include <miiphy.h> #include <lxt971a.h> #ifdef CONFIG_DRIVER_ETHER @@ -51,8 +52,8 @@ unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac) unsigned short Id1, Id2; at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID1, &Id1); - at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID2, &Id2); + at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR1, &Id1); + at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR2, &Id2); at91rm9200_EmacDisableMDIO (p_mac); if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0)) @@ -169,18 +170,18 @@ UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status) unsigned short value; /* Set lxt972 control register */ - if (!at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_CTRL, &value)) + if (!at91rm9200_EmacReadPhy (p_mac, PHY_BMCR, &value)) return FALSE; /* Restart Auto_negotiation */ - value |= PHY_COMMON_CTRL_RES_AUTO; - if (!at91rm9200_EmacWritePhy (p_mac, PHY_COMMON_CTRL, &value)) + value |= PHY_BMCR_RST_NEG; + if (!at91rm9200_EmacWritePhy (p_mac, PHY_BMCR, &value)) return FALSE; /*check AutoNegotiate complete */ udelay (10000); - at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_STAT, &value); - if (!(value & PHY_COMMON_STAT_AN_COMP)) + at91rm9200_EmacReadPhy(p_mac, PHY_BMSR, &value); + if (!(value & PHY_BMSR_AUTN_COMP)) return FALSE; return (lxt972_GetLinkSpeed (p_mac)); diff --git a/cpu/arm926ejs/at91sam9/config.mk b/cpu/arm926ejs/at91sam9/config.mk index ca2cae1..83040eb 100644 --- a/cpu/arm926ejs/at91sam9/config.mk +++ b/cpu/arm926ejs/at91sam9/config.mk @@ -1,2 +1,3 @@ PLATFORM_CPPFLAGS += -march=armv5te PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) +LDSCRIPT := $(SRCTREE)/cpu/arm926ejs/at91sam9/u-boot.lds diff --git a/cpu/at32ap/pm.c b/cpu/arm926ejs/at91sam9/u-boot.lds index c78d547..996f401 100644 --- a/cpu/at32ap/pm.c +++ b/cpu/arm926ejs/at91sam9/u-boot.lds @@ -1,5 +1,6 @@ /* - * Copyright (C) 2006 Atmel Corporation + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> * * See file CREDITS for list of people who contributed to this * project. @@ -11,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -19,24 +20,38 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#include <common.h> -#ifdef CFG_POWER_MANAGER -#include <asm/errno.h> -#include <asm/io.h> - -#include <asm/arch/memory-map.h> - -#include "sm.h" - - -#ifdef CONFIG_PLL -#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) -#else -#define MAIN_CLK_RATE (CFG_OSC0_HZ) -#endif - -DECLARE_GLOBAL_DATA_PTR; - - -#endif /* CFG_POWER_MANAGER */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/cpu/arm926ejs/at91sam9/usb.c b/cpu/arm926ejs/at91sam9/usb.c index 441349d..2a92f73 100644 --- a/cpu/arm926ejs/at91sam9/usb.c +++ b/cpu/arm926ejs/at91sam9/usb.c @@ -33,7 +33,11 @@ int usb_cpu_init(void) { /* Enable USB host clock. */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP); +#ifdef CONFIG_AT91SAM9261 + at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP | AT91_PMC_HCK0); +#else at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP); +#endif return 0; } @@ -42,7 +46,11 @@ int usb_cpu_stop(void) { /* Disable USB host clock. */ at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP); +#ifdef CONFIG_AT91SAM9261 + at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_HCK0); +#else at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP); +#endif return 0; } diff --git a/cpu/arm926ejs/davinci/lxt972.c b/cpu/arm926ejs/davinci/lxt972.c index 6eeb6e5..8130b48 100644 --- a/cpu/arm926ejs/davinci/lxt972.c +++ b/cpu/arm926ejs/davinci/lxt972.c @@ -27,6 +27,7 @@ #include <common.h> #include <net.h> +#include <miiphy.h> #include <lxt971a.h> #include <asm/arch/emac_defs.h> @@ -36,11 +37,11 @@ int lxt972_is_phy_connected(int phy_addr) { - u_int16_t id1, id2; + u_int16_t id1, id2; - if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID1, &id1)) + if (!dm644x_eth_phy_read(phy_addr, PHY_PHYIDR1, &id1)) return(0); - if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_ID2, &id2)) + if (!dm644x_eth_phy_read(phy_addr, PHY_PHYIDR2, &id2)) return(0); if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0)) @@ -51,8 +52,8 @@ int lxt972_is_phy_connected(int phy_addr) int lxt972_get_link_speed(int phy_addr) { - u_int16_t stat1, tmp; - volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; + u_int16_t stat1, tmp; + volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR; if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1)) return(0); @@ -70,37 +71,23 @@ int lxt972_get_link_speed(int phy_addr) if (!dm644x_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) return(0); - /* Speed doesn't matter, there is no setting for it in EMAC... */ - if (stat1 & PHY_LXT971_STAT2_100BTX) { - if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { - /* set DM644x EMAC for Full Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; - } else { - /*set DM644x EMAC for Half Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; - } - - return(1); + if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { + /* set DM644x EMAC for Full Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | + EMAC_MACCONTROL_FULLDUPLEX_ENABLE; } else { - if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { - /* set DM644x EMAC for Full Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE; - } else { - /*set DM644x EMAC for Half Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; - } - - return(1); + /*set DM644x EMAC for Half Duplex */ + emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; } - return(0); + return(1); } int lxt972_init_phy(int phy_addr) { - int ret = 1; + int ret = 1; if (!lxt972_get_link_speed(phy_addr)) { /* Try another time */ @@ -116,22 +103,21 @@ int lxt972_init_phy(int phy_addr) int lxt972_auto_negotiate(int phy_addr) { - u_int16_t tmp; - + u_int16_t tmp; - if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_CTRL, &tmp)) + if (!dm644x_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) return(0); /* Restart Auto_negotiation */ - tmp |= PHY_COMMON_CTRL_RES_AUTO; - dm644x_eth_phy_write(phy_addr, PHY_COMMON_CTRL, tmp); + tmp |= PHY_BMCR_RST_NEG; + dm644x_eth_phy_write(phy_addr, PHY_BMCR, tmp); /*check AutoNegotiate complete */ udelay (10000); - if (!dm644x_eth_phy_read(phy_addr, PHY_COMMON_STAT, &tmp)) + if (!dm644x_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) return(0); - if (!(tmp & PHY_COMMON_STAT_AN_COMP)) + if (!(tmp & PHY_BMSR_AUTN_COMP)) return(0); return (lxt972_get_link_speed(phy_addr)); diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c index ffc770f..36468e6 100644 --- a/cpu/arm926ejs/davinci/nand.c +++ b/cpu/arm926ejs/davinci/nand.c @@ -240,7 +240,8 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in return 0; case 1: /* Uncorrectable error */ - DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "ECC UNCORRECTED_ERROR 1\n"); return(-1); case 12: /* Correctable error */ @@ -256,7 +257,9 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; - DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit); + MTDDEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC " + "error at offset: %d, bit: %d\n", + find_byte, find_bit); page_data[find_byte] ^= (1 << find_bit); @@ -266,7 +269,8 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0) return(0); } - DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "UNCORRECTED_ERROR default\n"); return(-1); } } diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile index f69b1f3..33dc427 100644 --- a/cpu/at32ap/Makefile +++ b/cpu/at32ap/Makefile @@ -27,13 +27,18 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(CPU).a -START := start.o -SOBJS := entry.o -COBJS := cpu.o hsdramc.o exception.o cache.o -COBJS += interrupts.o pio.o atmel_mci.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) +START-y += start.o + +COBJS-y += cpu.o +COBJS-y += hsdramc.o +COBJS-y += exception.o +COBJS-y += cache.o +COBJS-y += interrupts.o +COBJS-y += pio.o + +SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START-y)) all: $(obj).depend $(START) $(LIB) diff --git a/cpu/at32ap/at32ap700x/Makefile b/cpu/at32ap/at32ap700x/Makefile index d276712..7404235 100644 --- a/cpu/at32ap/at32ap700x/Makefile +++ b/cpu/at32ap/at32ap700x/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(SOC).a -COBJS := gpio.o +COBJS := gpio.o clk.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/at32ap/at32ap700x/clk.c b/cpu/at32ap/at32ap700x/clk.c new file mode 100644 index 0000000..b3aa034 --- /dev/null +++ b/cpu/at32ap/at32ap700x/clk.c @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2005-2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/io.h> + +#include <asm/arch/clk.h> +#include <asm/arch/memory-map.h> + +#include "sm.h" + +void clk_init(void) +{ + uint32_t cksel; + + /* in case of soft resets, disable watchdog */ + sm_writel(WDT_CTRL, SM_BF(KEY, 0x55)); + sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa)); + +#ifdef CONFIG_PLL + /* Initialize the PLL */ + sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES) + | SM_BF(PLLMUL, CFG_PLL0_MUL - 1) + | SM_BF(PLLDIV, CFG_PLL0_DIV - 1) + | SM_BF(PLLOPT, CFG_PLL0_OPT) + | SM_BF(PLLOSC, 0) + | SM_BIT(PLLEN))); + + /* Wait for lock */ + while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ; +#endif + + /* Set up clocks for the CPU and all peripheral buses */ + cksel = 0; + if (CFG_CLKDIV_CPU) + cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1); + if (CFG_CLKDIV_HSB) + cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1); + if (CFG_CLKDIV_PBA) + cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1); + if (CFG_CLKDIV_PBB) + cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1); + sm_writel(PM_CKSEL, cksel); + +#ifdef CONFIG_PLL + /* Use PLL0 as main clock */ + sm_writel(PM_MCCTRL, SM_BIT(PLLSEL)); +#endif +} diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c index 859124a..56ba2f9 100644 --- a/cpu/at32ap/at32ap700x/gpio.c +++ b/cpu/at32ap/at32ap700x/gpio.c @@ -21,8 +21,11 @@ */ #include <common.h> +#include <asm/io.h> + #include <asm/arch/chip-features.h> #include <asm/arch/gpio.h> +#include <asm/arch/memory-map.h> /* * Lots of small functions here. We depend on --gc-sections getting @@ -142,3 +145,55 @@ void gpio_enable_mmci(void) gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */ } #endif + +#ifdef AT32AP700x_CHIP_HAS_SPI +void gpio_enable_spi0(unsigned long cs_mask) +{ + gpio_select_periph_A(GPIO_PIN_PA0, 0); /* MISO */ + gpio_select_periph_A(GPIO_PIN_PA1, 0); /* MOSI */ + gpio_select_periph_A(GPIO_PIN_PA2, 0); /* SCK */ + + /* Set up NPCSx as GPIO outputs, initially high */ + if (cs_mask & (1 << 0)) { + gpio_set_value(GPIO_PIN_PA3, 1); + gpio_select_pio(GPIO_PIN_PA3, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 1)) { + gpio_set_value(GPIO_PIN_PA4, 1); + gpio_select_pio(GPIO_PIN_PA4, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 2)) { + gpio_set_value(GPIO_PIN_PA5, 1); + gpio_select_pio(GPIO_PIN_PA5, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 3)) { + gpio_set_value(GPIO_PIN_PA20, 1); + gpio_select_pio(GPIO_PIN_PA20, GPIOF_OUTPUT); + } +} + +void gpio_enable_spi1(unsigned long cs_mask) +{ + gpio_select_periph_B(GPIO_PIN_PA0, 0); /* MISO */ + gpio_select_periph_B(GPIO_PIN_PB1, 0); /* MOSI */ + gpio_select_periph_B(GPIO_PIN_PB5, 0); /* SCK */ + + /* Set up NPCSx as GPIO outputs, initially high */ + if (cs_mask & (1 << 0)) { + gpio_set_value(GPIO_PIN_PB2, 1); + gpio_select_pio(GPIO_PIN_PB2, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 1)) { + gpio_set_value(GPIO_PIN_PB3, 1); + gpio_select_pio(GPIO_PIN_PB3, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 2)) { + gpio_set_value(GPIO_PIN_PB4, 1); + gpio_select_pio(GPIO_PIN_PB4, GPIOF_OUTPUT); + } + if (cs_mask & (1 << 3)) { + gpio_set_value(GPIO_PIN_PA27, 1); + gpio_select_pio(GPIO_PIN_PA27, GPIOF_OUTPUT); + } +} +#endif diff --git a/cpu/at32ap/sm.h b/cpu/at32ap/at32ap700x/sm.h index 6492c8e..6492c8e 100644 --- a/cpu/at32ap/sm.h +++ b/cpu/at32ap/at32ap700x/sm.h diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c deleted file mode 100644 index f59dfb5..0000000 --- a/cpu/at32ap/atmel_mci.c +++ /dev/null @@ -1,550 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> - -#ifdef CONFIG_MMC - -#include <part.h> -#include <mmc.h> - -#include <asm/io.h> -#include <asm/errno.h> -#include <asm/byteorder.h> -#include <asm/arch/clk.h> -#include <asm/arch/memory-map.h> - -#include "atmel_mci.h" - -#ifdef DEBUG -#define pr_debug(fmt, args...) printf(fmt, ##args) -#else -#define pr_debug(...) do { } while(0) -#endif - -#ifndef CFG_MMC_CLK_OD -#define CFG_MMC_CLK_OD 150000 -#endif - -#ifndef CFG_MMC_CLK_PP -#define CFG_MMC_CLK_PP 5000000 -#endif - -#ifndef CFG_MMC_OP_COND -#define CFG_MMC_OP_COND 0x00100000 -#endif - -#define MMC_DEFAULT_BLKLEN 512 -#define MMC_DEFAULT_RCA 1 - -static unsigned int mmc_rca; -static int mmc_card_is_sd; -static block_dev_desc_t mmc_blkdev; - -block_dev_desc_t *mmc_get_dev(int dev) -{ - return &mmc_blkdev; -} - -static void mci_set_mode(unsigned long hz, unsigned long blklen) -{ - unsigned long bus_hz; - unsigned long clkdiv; - - bus_hz = get_mci_clk_rate(); - clkdiv = (bus_hz / hz) / 2 - 1; - - pr_debug("mmc: setting clock %lu Hz, block size %lu\n", - hz, blklen); - - if (clkdiv & ~255UL) { - clkdiv = 255; - printf("mmc: clock %lu too low; setting CLKDIV to 255\n", - hz); - } - - blklen &= 0xfffc; - mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv) - | MMCI_BF(BLKLEN, blklen) - | MMCI_BIT(RDPROOF) - | MMCI_BIT(WRPROOF))); -} - -#define RESP_NO_CRC 1 -#define R1 MMCI_BF(RSPTYP, 1) -#define R2 MMCI_BF(RSPTYP, 2) -#define R3 (R1 | RESP_NO_CRC) -#define R6 R1 -#define NID MMCI_BF(MAXLAT, 0) -#define NCR MMCI_BF(MAXLAT, 1) -#define TRCMD_START MMCI_BF(TRCMD, 1) -#define TRDIR_READ MMCI_BF(TRDIR, 1) -#define TRTYP_BLOCK MMCI_BF(TRTYP, 0) -#define INIT_CMD MMCI_BF(SPCMD, 1) -#define OPEN_DRAIN MMCI_BF(OPDCMD, 1) - -#define ERROR_FLAGS (MMCI_BIT(DTOE) \ - | MMCI_BIT(RDIRE) \ - | MMCI_BIT(RENDE) \ - | MMCI_BIT(RINDE) \ - | MMCI_BIT(RTOE)) - -static int -mmc_cmd(unsigned long cmd, unsigned long arg, - void *resp, unsigned long flags) -{ - unsigned long *response = resp; - int i, response_words = 0; - unsigned long error_flags; - u32 status; - - pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n", - cmd, arg, flags); - - error_flags = ERROR_FLAGS; - if (!(flags & RESP_NO_CRC)) - error_flags |= MMCI_BIT(RCRCE); - - flags &= ~MMCI_BF(CMDNB, ~0UL); - - if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_48_BIT_RESP) - response_words = 1; - else if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_136_BIT_RESP) - response_words = 4; - - mmci_writel(ARGR, arg); - mmci_writel(CMDR, cmd | flags); - do { - udelay(40); - status = mmci_readl(SR); - } while (!(status & MMCI_BIT(CMDRDY))); - - pr_debug("mmc: status 0x%08lx\n", status); - - if (status & ERROR_FLAGS) { - printf("mmc: command %lu failed (status: 0x%08lx)\n", - cmd, status); - return -EIO; - } - - if (response_words) - pr_debug("mmc: response:"); - - for (i = 0; i < response_words; i++) { - response[i] = mmci_readl(RSPR); - pr_debug(" %08lx", response[i]); - } - pr_debug("\n"); - - return 0; -} - -static int mmc_acmd(unsigned long cmd, unsigned long arg, - void *resp, unsigned long flags) -{ - unsigned long aresp[4]; - int ret; - - /* - * Seems like the APP_CMD part of an ACMD has 64 cycles max - * latency even though the ACMD part doesn't. This isn't - * entirely clear in the SD Card spec, but some cards refuse - * to work if we attempt to use 5 cycles max latency here... - */ - ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp, - R1 | NCR | (flags & OPEN_DRAIN)); - if (ret) - return ret; - if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD) - return -ENODEV; - - ret = mmc_cmd(cmd, arg, resp, flags); - return ret; -} - -static unsigned long -mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, - unsigned long *buffer) -{ - int ret, i = 0; - unsigned long resp[4]; - unsigned long card_status, data; - unsigned long wordcount; - u32 status; - - if (blkcnt == 0) - return 0; - - pr_debug("mmc_bread: dev %d, start %lx, blkcnt %lx\n", - dev, start, blkcnt); - - /* Put the device into Transfer state */ - ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR); - if (ret) goto out; - - /* Set block length */ - ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); - if (ret) goto out; - - pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); - - for (i = 0; i < blkcnt; i++, start++) { - ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, - start * mmc_blkdev.blksz, resp, - (R1 | NCR | TRCMD_START | TRDIR_READ - | TRTYP_BLOCK)); - if (ret) goto out; - - ret = -EIO; - wordcount = 0; - do { - do { - status = mmci_readl(SR); - if (status & (ERROR_FLAGS | MMCI_BIT(OVRE))) - goto read_error; - } while (!(status & MMCI_BIT(RXRDY))); - - if (status & MMCI_BIT(RXRDY)) { - data = mmci_readl(RDR); - /* pr_debug("%x\n", data); */ - *buffer++ = data; - wordcount++; - } - } while(wordcount < (mmc_blkdev.blksz / 4)); - - pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount); - - do { - status = mmci_readl(SR); - } while (!(status & MMCI_BIT(BLKE))); - - putc('.'); - } - -out: - /* Put the device back into Standby state */ - mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); - return i; - -read_error: - mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); - printf("mmc: bread failed, status = %08x, card status = %08x\n", - status, card_status); - goto out; -} - -static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp) -{ - cid->mid = resp[0] >> 24; - cid->oid = (resp[0] >> 8) & 0xffff; - cid->pnm[0] = resp[0]; - cid->pnm[1] = resp[1] >> 24; - cid->pnm[2] = resp[1] >> 16; - cid->pnm[3] = resp[1] >> 8; - cid->pnm[4] = resp[1]; - cid->pnm[5] = resp[2] >> 24; - cid->pnm[6] = 0; - cid->prv = resp[2] >> 16; - cid->psn = (resp[2] << 16) | (resp[3] >> 16); - cid->mdt = resp[3] >> 8; -} - -static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp) -{ - cid->mid = resp[0] >> 24; - cid->oid = (resp[0] >> 8) & 0xffff; - cid->pnm[0] = resp[0]; - cid->pnm[1] = resp[1] >> 24; - cid->pnm[2] = resp[1] >> 16; - cid->pnm[3] = resp[1] >> 8; - cid->pnm[4] = resp[1]; - cid->pnm[5] = 0; - cid->pnm[6] = 0; - cid->prv = resp[2] >> 24; - cid->psn = (resp[2] << 8) | (resp[3] >> 24); - cid->mdt = (resp[3] >> 8) & 0x0fff; -} - -static void mmc_dump_cid(const struct mmc_cid *cid) -{ - printf("Manufacturer ID: %02lX\n", cid->mid); - printf("OEM/Application ID: %04lX\n", cid->oid); - printf("Product name: %s\n", cid->pnm); - printf("Product Revision: %lu.%lu\n", - cid->prv >> 4, cid->prv & 0x0f); - printf("Product Serial Number: %lu\n", cid->psn); - printf("Manufacturing Date: %02lu/%02lu\n", - cid->mdt >> 4, cid->mdt & 0x0f); -} - -static void mmc_dump_csd(const struct mmc_csd *csd) -{ - unsigned long *csd_raw = (unsigned long *)csd; - printf("CSD data: %08lx %08lx %08lx %08lx\n", - csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]); - printf("CSD structure version: 1.%u\n", csd->csd_structure); - printf("MMC System Spec version: %u\n", csd->spec_vers); - printf("Card command classes: %03x\n", csd->ccc); - printf("Read block length: %u\n", 1 << csd->read_bl_len); - if (csd->read_bl_partial) - puts("Supports partial reads\n"); - else - puts("Does not support partial reads\n"); - printf("Write block length: %u\n", 1 << csd->write_bl_len); - if (csd->write_bl_partial) - puts("Supports partial writes\n"); - else - puts("Does not support partial writes\n"); - if (csd->wp_grp_enable) - printf("Supports group WP: %u\n", csd->wp_grp_size + 1); - else - puts("Does not support group WP\n"); - printf("Card capacity: %u bytes\n", - (csd->c_size + 1) * (1 << (csd->c_size_mult + 2)) * - (1 << csd->read_bl_len)); - printf("File format: %u/%u\n", - csd->file_format_grp, csd->file_format); - puts("Write protection: "); - if (csd->perm_write_protect) - puts(" permanent"); - if (csd->tmp_write_protect) - puts(" temporary"); - putc('\n'); -} - -static int mmc_idle_cards(void) -{ - int ret; - - /* Reset and initialize all cards */ - ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0); - if (ret) - return ret; - - /* Keep the bus idle for 74 clock cycles */ - return mmc_cmd(0, 0, NULL, INIT_CMD); -} - -static int sd_init_card(struct mmc_cid *cid, int verbose) -{ - unsigned long resp[4]; - int i, ret = 0; - - mmc_idle_cards(); - for (i = 0; i < 1000; i++) { - ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_MMC_OP_COND, - resp, R3 | NID); - if (ret || (resp[0] & 0x80000000)) - break; - ret = -ETIMEDOUT; - } - - if (ret) - return ret; - - ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID); - if (ret) - return ret; - sd_parse_cid(cid, resp); - if (verbose) - mmc_dump_cid(cid); - - /* Get RCA of the card that responded */ - ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR); - if (ret) - return ret; - - mmc_rca = resp[0] >> 16; - if (verbose) - printf("SD Card detected (RCA %u)\n", mmc_rca); - mmc_card_is_sd = 1; - return 0; -} - -static int mmc_init_card(struct mmc_cid *cid, int verbose) -{ - unsigned long resp[4]; - int i, ret = 0; - - mmc_idle_cards(); - for (i = 0; i < 1000; i++) { - ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_MMC_OP_COND, resp, - R3 | NID | OPEN_DRAIN); - if (ret || (resp[0] & 0x80000000)) - break; - ret = -ETIMEDOUT; - } - - if (ret) - return ret; - - /* Get CID of all cards. FIXME: Support more than one card */ - ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN); - if (ret) - return ret; - mmc_parse_cid(cid, resp); - if (verbose) - mmc_dump_cid(cid); - - /* Set Relative Address of the card that responded */ - ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp, - R1 | NCR | OPEN_DRAIN); - return ret; -} - -static void mci_set_data_timeout(struct mmc_csd *csd) -{ - static const unsigned int dtomul_to_shift[] = { - 0, 4, 7, 8, 10, 12, 16, 20, - }; - static const unsigned int taac_exp[] = { - 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, - }; - static const unsigned int taac_mant[] = { - 0, 10, 12, 13, 15, 60, 25, 30, - 35, 40, 45, 50, 55, 60, 70, 80, - }; - unsigned int timeout_ns, timeout_clks; - unsigned int e, m; - unsigned int dtocyc, dtomul; - unsigned int shift; - u32 dtor; - - e = csd->taac & 0x07; - m = (csd->taac >> 3) & 0x0f; - - timeout_ns = (taac_exp[e] * taac_mant[m] + 9) / 10; - timeout_clks = csd->nsac * 100; - - timeout_clks += (((timeout_ns + 9) / 10) - * ((CFG_MMC_CLK_PP + 99999) / 100000) + 9999) / 10000; - if (!mmc_card_is_sd) - timeout_clks *= 10; - else - timeout_clks *= 100; - - dtocyc = timeout_clks; - dtomul = 0; - while (dtocyc > 15 && dtomul < 8) { - dtomul++; - shift = dtomul_to_shift[dtomul]; - dtocyc = (timeout_clks + (1 << shift) - 1) >> shift; - } - - if (dtomul >= 8) { - dtomul = 7; - dtocyc = 15; - puts("Warning: Using maximum data timeout\n"); - } - - dtor = (MMCI_BF(DTOMUL, dtomul) - | MMCI_BF(DTOCYC, dtocyc)); - mmci_writel(DTOR, dtor); - - printf("mmc: Using %u cycles data timeout (DTOR=0x%x)\n", - dtocyc << shift, dtor); -} - -int mmc_init(int verbose) -{ - struct mmc_cid cid; - struct mmc_csd csd; - unsigned int max_blksz; - int ret; - - /* Initialize controller */ - mmci_writel(CR, MMCI_BIT(SWRST)); - mmci_writel(CR, MMCI_BIT(MCIEN)); - mmci_writel(DTOR, 0x5f); - mmci_writel(IDR, ~0UL); - mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); - - mmc_card_is_sd = 0; - - ret = sd_init_card(&cid, verbose); - if (ret) { - mmc_rca = MMC_DEFAULT_RCA; - ret = mmc_init_card(&cid, verbose); - } - if (ret) - return ret; - - /* Get CSD from the card */ - ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, &csd, R2 | NCR); - if (ret) - return ret; - if (verbose) - mmc_dump_csd(&csd); - - mci_set_data_timeout(&csd); - - /* Initialize the blockdev structure */ - mmc_blkdev.if_type = IF_TYPE_MMC; - mmc_blkdev.part_type = PART_TYPE_DOS; - mmc_blkdev.block_read = mmc_bread; - sprintf((char *)mmc_blkdev.vendor, - "Man %02x%04x Snr %08x", - cid.mid, cid.oid, cid.psn); - strncpy((char *)mmc_blkdev.product, cid.pnm, - sizeof(mmc_blkdev.product)); - sprintf((char *)mmc_blkdev.revision, "%x %x", - cid.prv >> 4, cid.prv & 0x0f); - - /* - * If we can't use 512 byte blocks, refuse to deal with the - * card. Tons of code elsewhere seems to depend on this. - */ - max_blksz = 1 << csd.read_bl_len; - if (max_blksz < 512 || (max_blksz > 512 && !csd.read_bl_partial)) { - printf("Card does not support 512 byte reads, aborting.\n"); - return -ENODEV; - } - mmc_blkdev.blksz = 512; - mmc_blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2)); - - mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz); - -#if 0 - if (fat_register_device(&mmc_blkdev, 1)) - printf("Could not register MMC fat device\n"); -#else - init_part(&mmc_blkdev); -#endif - - return 0; -} - -int mmc_read(ulong src, uchar *dst, int size) -{ - return -ENOSYS; -} - -int mmc_write(uchar *src, ulong dst, int size) -{ - return -ENOSYS; -} - -int mmc2info(ulong addr) -{ - return 0; -} - -#endif /* CONFIG_MMC */ diff --git a/cpu/at32ap/atmel_mci.h b/cpu/at32ap/atmel_mci.h deleted file mode 100644 index 5b4f5c9..0000000 --- a/cpu/at32ap/atmel_mci.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CPU_AT32AP_ATMEL_MCI_H__ -#define __CPU_AT32AP_ATMEL_MCI_H__ - -/* Atmel MultiMedia Card Interface (MCI) registers */ -#define MMCI_CR 0x0000 -#define MMCI_MR 0x0004 -#define MMCI_DTOR 0x0008 -#define MMCI_SDCR 0x000c -#define MMCI_ARGR 0x0010 -#define MMCI_CMDR 0x0014 -#define MMCI_RSPR 0x0020 -#define MMCI_RSPR1 0x0024 -#define MMCI_RSPR2 0x0028 -#define MMCI_RSPR3 0x002c -#define MMCI_RDR 0x0030 -#define MMCI_TDR 0x0034 -#define MMCI_SR 0x0040 -#define MMCI_IER 0x0044 -#define MMCI_IDR 0x0048 -#define MMCI_IMR 0x004c - -/* Bitfields in CR */ -#define MMCI_MCIEN_OFFSET 0 -#define MMCI_MCIEN_SIZE 1 -#define MMCI_MCIDIS_OFFSET 1 -#define MMCI_MCIDIS_SIZE 1 -#define MMCI_PWSEN_OFFSET 2 -#define MMCI_PWSEN_SIZE 1 -#define MMCI_PWSDIS_OFFSET 3 -#define MMCI_PWSDIS_SIZE 1 -#define MMCI_SWRST_OFFSET 7 -#define MMCI_SWRST_SIZE 1 - -/* Bitfields in MR */ -#define MMCI_CLKDIV_OFFSET 0 -#define MMCI_CLKDIV_SIZE 8 -#define MMCI_PWSDIV_OFFSET 8 -#define MMCI_PWSDIV_SIZE 3 -#define MMCI_RDPROOF_OFFSET 11 -#define MMCI_RDPROOF_SIZE 1 -#define MMCI_WRPROOF_OFFSET 12 -#define MMCI_WRPROOF_SIZE 1 -#define MMCI_PDCPADV_OFFSET 14 -#define MMCI_PDCPADV_SIZE 1 -#define MMCI_PDCMODE_OFFSET 15 -#define MMCI_PDCMODE_SIZE 1 -#define MMCI_BLKLEN_OFFSET 16 -#define MMCI_BLKLEN_SIZE 16 - -/* Bitfields in DTOR */ -#define MMCI_DTOCYC_OFFSET 0 -#define MMCI_DTOCYC_SIZE 4 -#define MMCI_DTOMUL_OFFSET 4 -#define MMCI_DTOMUL_SIZE 3 - -/* Bitfields in SDCR */ -#define MMCI_SCDSEL_OFFSET 0 -#define MMCI_SCDSEL_SIZE 4 -#define MMCI_SCDBUS_OFFSET 7 -#define MMCI_SCDBUS_SIZE 1 - -/* Bitfields in ARGR */ -#define MMCI_ARG_OFFSET 0 -#define MMCI_ARG_SIZE 32 - -/* Bitfields in CMDR */ -#define MMCI_CMDNB_OFFSET 0 -#define MMCI_CMDNB_SIZE 6 -#define MMCI_RSPTYP_OFFSET 6 -#define MMCI_RSPTYP_SIZE 2 -#define MMCI_SPCMD_OFFSET 8 -#define MMCI_SPCMD_SIZE 3 -#define MMCI_OPDCMD_OFFSET 11 -#define MMCI_OPDCMD_SIZE 1 -#define MMCI_MAXLAT_OFFSET 12 -#define MMCI_MAXLAT_SIZE 1 -#define MMCI_TRCMD_OFFSET 16 -#define MMCI_TRCMD_SIZE 2 -#define MMCI_TRDIR_OFFSET 18 -#define MMCI_TRDIR_SIZE 1 -#define MMCI_TRTYP_OFFSET 19 -#define MMCI_TRTYP_SIZE 2 - -/* Bitfields in RSPRx */ -#define MMCI_RSP_OFFSET 0 -#define MMCI_RSP_SIZE 32 - -/* Bitfields in SR/IER/IDR/IMR */ -#define MMCI_CMDRDY_OFFSET 0 -#define MMCI_CMDRDY_SIZE 1 -#define MMCI_RXRDY_OFFSET 1 -#define MMCI_RXRDY_SIZE 1 -#define MMCI_TXRDY_OFFSET 2 -#define MMCI_TXRDY_SIZE 1 -#define MMCI_BLKE_OFFSET 3 -#define MMCI_BLKE_SIZE 1 -#define MMCI_DTIP_OFFSET 4 -#define MMCI_DTIP_SIZE 1 -#define MMCI_NOTBUSY_OFFSET 5 -#define MMCI_NOTBUSY_SIZE 1 -#define MMCI_ENDRX_OFFSET 6 -#define MMCI_ENDRX_SIZE 1 -#define MMCI_ENDTX_OFFSET 7 -#define MMCI_ENDTX_SIZE 1 -#define MMCI_RXBUFF_OFFSET 14 -#define MMCI_RXBUFF_SIZE 1 -#define MMCI_TXBUFE_OFFSET 15 -#define MMCI_TXBUFE_SIZE 1 -#define MMCI_RINDE_OFFSET 16 -#define MMCI_RINDE_SIZE 1 -#define MMCI_RDIRE_OFFSET 17 -#define MMCI_RDIRE_SIZE 1 -#define MMCI_RCRCE_OFFSET 18 -#define MMCI_RCRCE_SIZE 1 -#define MMCI_RENDE_OFFSET 19 -#define MMCI_RENDE_SIZE 1 -#define MMCI_RTOE_OFFSET 20 -#define MMCI_RTOE_SIZE 1 -#define MMCI_DCRCE_OFFSET 21 -#define MMCI_DCRCE_SIZE 1 -#define MMCI_DTOE_OFFSET 22 -#define MMCI_DTOE_SIZE 1 -#define MMCI_OVRE_OFFSET 30 -#define MMCI_OVRE_SIZE 1 -#define MMCI_UNRE_OFFSET 31 -#define MMCI_UNRE_SIZE 1 - -/* Constants for DTOMUL */ -#define MMCI_DTOMUL_1_CYCLE 0 -#define MMCI_DTOMUL_16_CYCLES 1 -#define MMCI_DTOMUL_128_CYCLES 2 -#define MMCI_DTOMUL_256_CYCLES 3 -#define MMCI_DTOMUL_1024_CYCLES 4 -#define MMCI_DTOMUL_4096_CYCLES 5 -#define MMCI_DTOMUL_65536_CYCLES 6 -#define MMCI_DTOMUL_1048576_CYCLES 7 - -/* Constants for RSPTYP */ -#define MMCI_RSPTYP_NO_RESP 0 -#define MMCI_RSPTYP_48_BIT_RESP 1 -#define MMCI_RSPTYP_136_BIT_RESP 2 - -/* Constants for SPCMD */ -#define MMCI_SPCMD_NO_SPEC_CMD 0 -#define MMCI_SPCMD_INIT_CMD 1 -#define MMCI_SPCMD_SYNC_CMD 2 -#define MMCI_SPCMD_INT_CMD 4 -#define MMCI_SPCMD_INT_RESP 5 - -/* Constants for TRCMD */ -#define MMCI_TRCMD_NO_TRANS 0 -#define MMCI_TRCMD_START_TRANS 1 -#define MMCI_TRCMD_STOP_TRANS 2 - -/* Constants for TRTYP */ -#define MMCI_TRTYP_BLOCK 0 -#define MMCI_TRTYP_MULTI_BLOCK 1 -#define MMCI_TRTYP_STREAM 2 - -/* Bit manipulation macros */ -#define MMCI_BIT(name) \ - (1 << MMCI_##name##_OFFSET) -#define MMCI_BF(name,value) \ - (((value) & ((1 << MMCI_##name##_SIZE) - 1)) \ - << MMCI_##name##_OFFSET) -#define MMCI_BFEXT(name,value) \ - (((value) >> MMCI_##name##_OFFSET)\ - & ((1 << MMCI_##name##_SIZE) - 1)) -#define MMCI_BFINS(name,value,old) \ - (((old) & ~(((1 << MMCI_##name##_SIZE) - 1) \ - << MMCI_##name##_OFFSET)) \ - | MMCI_BF(name,value)) - -/* Register access macros */ -#define mmci_readl(reg) \ - readl((void *)MMCI_BASE + MMCI_##reg) -#define mmci_writel(reg,value) \ - writel((value), (void *)MMCI_BASE + MMCI_##reg) - -#endif /* __CPU_AT32AP_ATMEL_MCI_H__ */ diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c index 311466b..0ba8361 100644 --- a/cpu/at32ap/cpu.c +++ b/cpu/at32ap/cpu.c @@ -30,7 +30,6 @@ #include <asm/arch/memory-map.h> #include "hsmc3.h" -#include "sm.h" /* Sanity checks */ #if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \ @@ -44,47 +43,9 @@ DECLARE_GLOBAL_DATA_PTR; -static void pm_init(void) -{ - uint32_t cksel; - -#ifdef CONFIG_PLL - /* Initialize the PLL */ - sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES) - | SM_BF(PLLMUL, CFG_PLL0_MUL - 1) - | SM_BF(PLLDIV, CFG_PLL0_DIV - 1) - | SM_BF(PLLOPT, CFG_PLL0_OPT) - | SM_BF(PLLOSC, 0) - | SM_BIT(PLLEN))); - - /* Wait for lock */ - while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ; -#endif - - /* Set up clocks for the CPU and all peripheral buses */ - cksel = 0; - if (CFG_CLKDIV_CPU) - cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1); - if (CFG_CLKDIV_HSB) - cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1); - if (CFG_CLKDIV_PBA) - cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1); - if (CFG_CLKDIV_PBB) - cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1); - sm_writel(PM_CKSEL, cksel); - - gd->cpu_hz = get_cpu_clk_rate(); - -#ifdef CONFIG_PLL - /* Use PLL0 as main clock */ - sm_writel(PM_MCCTRL, SM_BIT(PLLSEL)); -#endif -} - int cpu_init(void) { extern void _evba(void); - char *p; gd->cpu_hz = CFG_OSC0_HZ; @@ -95,16 +56,15 @@ int cpu_init(void) hsmc3_writel(PULSE0, 0x0b0a0906); hsmc3_writel(SETUP0, 0x00010002); - pm_init(); + clk_init(); + /* Update the CPU speed according to the PLL configuration */ + gd->cpu_hz = get_cpu_clk_rate(); + + /* Set up the exception handler table and enable exceptions */ sysreg_write(EVBA, (unsigned long)&_evba); asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET)); - /* Lock everything that mess with the flash in the icache */ - for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ); - p += CFG_ICACHE_LINESZ) - asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory"); - return 0; } diff --git a/cpu/at32ap/entry.S b/cpu/at32ap/entry.S deleted file mode 100644 index a6fc688..0000000 --- a/cpu/at32ap/entry.S +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <asm/sysreg.h> -#include <asm/ptrace.h> - - .section .text.exception,"ax" - .global _evba - .type _evba,@function - .align 10 -_evba: - .irp x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 - .align 2 - rjmp unknown_exception - .endr - - .global timer_interrupt_handler - .type timer_interrupt_handler,@function - .align 2 -timer_interrupt_handler: - /* - * Increment timer_overflow and re-write COMPARE with 0xffffffff. - * - * We're running at interrupt level 3, so we don't need to save - * r8-r12 or lr to the stack. - */ - lda.w r8, timer_overflow - ld.w r9, r8[0] - mov r10, -1 - mtsr SYSREG_COMPARE, r10 - sub r9, -1 - st.w r8[0], r9 - rete - - .type unknown_exception, @function -unknown_exception: - pushm r0-r12 - sub r8, sp, REG_R12 - REG_R0 - 4 - mov r9, lr - mfsr r10, SYSREG_RAR_EX - mfsr r11, SYSREG_RSR_EX - pushm r8-r11 - mfsr r12, SYSREG_ECR - mov r11, sp - rcall do_unknown_exception -1: rjmp 1b diff --git a/cpu/at32ap/exception.c b/cpu/at32ap/exception.c index 0672685..dc9c300 100644 --- a/cpu/at32ap/exception.c +++ b/cpu/at32ap/exception.c @@ -111,7 +111,8 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs) printf("CPU Mode: %s\n", cpu_modes[mode]); /* Avoid exception loops */ - if (regs->sp < CFG_SDRAM_BASE || regs->sp >= gd->stack_end) + if (regs->sp < (gd->stack_end - CONFIG_STACKSIZE) + || regs->sp >= gd->stack_end) printf("\nStack pointer seems bogus, won't do stack dump\n"); else dump_mem("\nStack: ", regs->sp, gd->stack_end); diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c index 1fcfe75..992612b 100644 --- a/cpu/at32ap/hsdramc.c +++ b/cpu/at32ap/hsdramc.c @@ -30,39 +30,32 @@ #include "hsdramc1.h" -unsigned long sdram_init(const struct sdram_info *info) +unsigned long sdram_init(void *sdram_base, const struct sdram_config *config) { - unsigned long *sdram = (unsigned long *)uncached(info->phys_addr); unsigned long sdram_size; - unsigned long tmp; - unsigned long bus_hz; + uint32_t cfgreg; unsigned int i; - if (!info->refresh_period) - panic("ERROR: SDRAM refresh period == 0. " - "Please update the board code\n"); - - tmp = (HSDRAMC1_BF(NC, info->col_bits - 8) - | HSDRAMC1_BF(NR, info->row_bits - 11) - | HSDRAMC1_BF(NB, info->bank_bits - 1) - | HSDRAMC1_BF(CAS, info->cas) - | HSDRAMC1_BF(TWR, info->twr) - | HSDRAMC1_BF(TRC, info->trc) - | HSDRAMC1_BF(TRP, info->trp) - | HSDRAMC1_BF(TRCD, info->trcd) - | HSDRAMC1_BF(TRAS, info->tras) - | HSDRAMC1_BF(TXSR, info->txsr)); - -#ifdef CFG_SDRAM_16BIT - tmp |= HSDRAMC1_BIT(DBW); - sdram_size = 1 << (info->row_bits + info->col_bits - + info->bank_bits + 1); -#else - sdram_size = 1 << (info->row_bits + info->col_bits - + info->bank_bits + 2); -#endif - - hsdramc1_writel(CR, tmp); + cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8) + | HSDRAMC1_BF(NR, config->row_bits - 11) + | HSDRAMC1_BF(NB, config->bank_bits - 1) + | HSDRAMC1_BF(CAS, config->cas) + | HSDRAMC1_BF(TWR, config->twr) + | HSDRAMC1_BF(TRC, config->trc) + | HSDRAMC1_BF(TRP, config->trp) + | HSDRAMC1_BF(TRCD, config->trcd) + | HSDRAMC1_BF(TRAS, config->tras) + | HSDRAMC1_BF(TXSR, config->txsr)); + + if (config->data_bits == SDRAM_DATA_16BIT) + cfgreg |= HSDRAMC1_BIT(DBW); + + hsdramc1_writel(CR, cfgreg); + + /* Send a NOP to turn on the clock (necessary on some chips) */ + hsdramc1_writel(MR, HSDRAMC1_MODE_NOP); + hsdramc1_readl(MR); + writel(0, sdram_base); /* * Initialization sequence for SDRAM, from the data sheet: @@ -77,7 +70,7 @@ unsigned long sdram_init(const struct sdram_info *info) */ hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE); hsdramc1_readl(MR); - writel(0, sdram); + writel(0, sdram_base); /* * 3. Eight auto-refresh (CBR) cycles are provided @@ -85,58 +78,41 @@ unsigned long sdram_init(const struct sdram_info *info) hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH); hsdramc1_readl(MR); for (i = 0; i < 8; i++) - writel(0, sdram); + writel(0, sdram_base); /* * 4. A mode register set (MRS) cycle is issued to program * SDRAM parameters, in particular CAS latency and burst * length. * - * CAS from info struct, burst length 1, serial burst type + * The address will be chosen by the SDRAMC automatically; we + * just have to make sure BA[1:0] are set to 0. */ hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE); hsdramc1_readl(MR); - writel(0, sdram + (info->cas << 4)); + writel(0, sdram_base); /* - * 5. A Normal Mode command is provided, 3 clocks after tMRD - * is met. - * - * From the timing diagram, it looks like tMRD is 3 - * cycles...try a dummy read from the peripheral bus. + * 5. The application must go into Normal Mode, setting Mode + * to 0 in the Mode Register and performing a write access + * at any location in the SDRAM. */ - hsdramc1_readl(MR); hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL); hsdramc1_readl(MR); - writel(0, sdram); + writel(0, sdram_base); /* * 6. Write refresh rate into SDRAMC refresh timer count * register (refresh rate = timing between refresh cycles). - * - * 15.6 us is a typical value for a burst of length one */ - bus_hz = get_sdram_clk_rate(); - hsdramc1_writel(TR, info->refresh_period); - - printf("SDRAM: %u MB at address 0x%08lx\n", - sdram_size >> 20, info->phys_addr); - - printf("Testing SDRAM..."); - for (i = 0; i < sdram_size / 4; i++) - sdram[i] = i; - - for (i = 0; i < sdram_size / 4; i++) { - tmp = sdram[i]; - if (tmp != i) { - printf("FAILED at address 0x%08lx\n", - info->phys_addr + i * 4); - printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i); - return 0; - } - } - - puts("OK\n"); + hsdramc1_writel(TR, config->refresh_period); + + if (config->data_bits == SDRAM_DATA_16BIT) + sdram_size = 1 << (config->row_bits + config->col_bits + + config->bank_bits + 1); + else + sdram_size = 1 << (config->row_bits + config->col_bits + + config->bank_bits + 2); return sdram_size; } diff --git a/cpu/at32ap/interrupts.c b/cpu/at32ap/interrupts.c index bef1f30..160838e 100644 --- a/cpu/at32ap/interrupts.c +++ b/cpu/at32ap/interrupts.c @@ -98,18 +98,16 @@ void set_timer(unsigned long t) */ void udelay(unsigned long usec) { - unsigned long now, end; + unsigned long cycles; + unsigned long base; + unsigned long now; - now = sysreg_read(COUNT); + base = sysreg_read(COUNT); + cycles = ((usec * (get_tbclk() / 10000)) + 50) / 100; - end = ((usec * (get_tbclk() / 10000)) + 50) / 100; - end += now; - - while (now > end) - now = sysreg_read(COUNT); - - while (now < end) + do { now = sysreg_read(COUNT); + } while ((now - base) < cycles); } static int set_interrupt_handler(unsigned int nr, void (*handler)(void), diff --git a/cpu/at32ap/pio.c b/cpu/at32ap/pio.c index 9ba0b8e..f64004b 100644 --- a/cpu/at32ap/pio.c +++ b/cpu/at32ap/pio.c @@ -58,3 +58,59 @@ void gpio_select_periph_B(unsigned int pin, int use_pullup) else pio2_writel(base, PUDR, mask); } + +void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags) +{ + void *base = gpio_pin_to_addr(pin); + uint32_t mask = 1 << (pin & 0x1f); + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + if (gpiof_flags & GPIOF_OUTPUT) { + if (gpiof_flags & GPIOF_MULTIDRV) + pio2_writel(base, MDER, mask); + else + pio2_writel(base, MDDR, mask); + pio2_writel(base, PUDR, mask); + pio2_writel(base, OER, mask); + } else { + if (gpiof_flags & GPIOF_PULLUP) + pio2_writel(base, PUER, mask); + else + pio2_writel(base, PUDR, mask); + if (gpiof_flags & GPIOF_DEGLITCH) + pio2_writel(base, IFER, mask); + else + pio2_writel(base, IFDR, mask); + pio2_writel(base, ODR, mask); + } + + pio2_writel(base, PER, mask); +} + +void gpio_set_value(unsigned int pin, int value) +{ + void *base = gpio_pin_to_addr(pin); + uint32_t mask = 1 << (pin & 0x1f); + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + if (value) + pio2_writel(base, SODR, mask); + else + pio2_writel(base, CODR, mask); +} + +int gpio_get_value(unsigned int pin) +{ + void *base = gpio_pin_to_addr(pin); + int value; + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + value = pio2_readl(base, PDSR); + return (value >> (pin & 0x1f)) & 1; +} diff --git a/cpu/at32ap/start.S b/cpu/at32ap/start.S index ab8c2b7..907e9b1 100644 --- a/cpu/at32ap/start.S +++ b/cpu/at32ap/start.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2005-2006 Atmel Corporation + * Copyright (C) 2005-2008 Atmel Corporation * * See file CREDITS for list of people who contributed to this * project. @@ -20,12 +20,9 @@ * MA 02111-1307 USA */ #include <config.h> +#include <asm/ptrace.h> #include <asm/sysreg.h> -#ifndef PART_SPECIFIC_BOOTSTRAP -# define PART_SPECIFIC_BOOTSTRAP -#endif - #define SYSREG_MMUCR_I_OFFSET 2 #define SYSREG_MMUCR_S_OFFSET 4 @@ -34,11 +31,115 @@ | SYSREG_BIT(FE) | SYSREG_BIT(RE) \ | SYSREG_BIT(IBE) | SYSREG_BIT(IEE)) - .text + /* + * To save some space, we use the same entry point for + * exceptions and reset. This avoids lots of alignment padding + * since the reset vector is always suitably aligned. + */ + .section .exception.text, "ax", @progbits .global _start + .global _evba + .type _start, @function + .type _evba, @function _start: - PART_SPECIFIC_BOOTSTRAP + .size _start, 0 +_evba: + .org 0x00 + rjmp unknown_exception /* Unrecoverable exception */ + .org 0x04 + rjmp unknown_exception /* TLB multiple hit */ + .org 0x08 + rjmp unknown_exception /* Bus error data fetch */ + .org 0x0c + rjmp unknown_exception /* Bus error instruction fetch */ + .org 0x10 + rjmp unknown_exception /* NMI */ + .org 0x14 + rjmp unknown_exception /* Instruction address */ + .org 0x18 + rjmp unknown_exception /* ITLB protection */ + .org 0x1c + rjmp unknown_exception /* Breakpoint */ + .org 0x20 + rjmp unknown_exception /* Illegal opcode */ + .org 0x24 + rjmp unknown_exception /* Unimplemented instruction */ + .org 0x28 + rjmp unknown_exception /* Privilege violation */ + .org 0x2c + rjmp unknown_exception /* Floating-point */ + .org 0x30 + rjmp unknown_exception /* Coprocessor absent */ + .org 0x34 + rjmp unknown_exception /* Data Address (read) */ + .org 0x38 + rjmp unknown_exception /* Data Address (write) */ + .org 0x3c + rjmp unknown_exception /* DTLB Protection (read) */ + .org 0x40 + rjmp unknown_exception /* DTLB Protection (write) */ + .org 0x44 + rjmp unknown_exception /* DTLB Modified */ + + .org 0x50 + rjmp unknown_exception /* ITLB Miss */ + .org 0x60 + rjmp unknown_exception /* DTLB Miss (read) */ + .org 0x70 + rjmp unknown_exception /* DTLB Miss (write) */ + + .size _evba, . - _evba + + .align 2 + .type unknown_exception, @function +unknown_exception: + /* Figure out whether we're handling an exception (Exception + * mode) or just booting (Supervisor mode). */ + csrfcz SYSREG_M1_OFFSET + brcc at32ap_cpu_bootstrap + + /* This is an exception. Complain. */ + pushm r0-r12 + sub r8, sp, REG_R12 - REG_R0 - 4 + mov r9, lr + mfsr r10, SYSREG_RAR_EX + mfsr r11, SYSREG_RSR_EX + pushm r8-r11 + mfsr r12, SYSREG_ECR + mov r11, sp + rcall do_unknown_exception +1: rjmp 1b + + /* The COUNT/COMPARE timer interrupt handler */ + .global timer_interrupt_handler + .type timer_interrupt_handler,@function + .align 2 +timer_interrupt_handler: + /* + * Increment timer_overflow and re-write COMPARE with 0xffffffff. + * + * We're running at interrupt level 3, so we don't need to save + * r8-r12 or lr to the stack. + */ + lda.w r8, timer_overflow + ld.w r9, r8[0] + mov r10, -1 + mtsr SYSREG_COMPARE, r10 + sub r9, -1 + st.w r8[0], r9 + rete + /* + * CPU bootstrap after reset is handled here. SoC code may + * override this in case they need to initialize oscillators, + * etc. + */ + .section .text.at32ap_cpu_bootstrap, "ax", @progbits + .global at32ap_cpu_bootstrap + .weak at32ap_cpu_bootstrap + .type at32ap_cpu_bootstrap, @function + .align 2 +at32ap_cpu_bootstrap: /* Reset the Status Register */ mov r0, lo(SR_INIT) orh r0, hi(SR_INIT) @@ -66,9 +167,16 @@ _start: lddpc pc, 1f .align 2 -1: .long 2f +1: .long at32ap_low_level_init + .size _start, . - _start -2: lddpc sp, sp_init + /* Common CPU bootstrap code after oscillator/cache/etc. init */ + .section .text.avr32ap_low_level_init, "ax", @progbits + .global at32ap_low_level_init + .type at32ap_low_level_init, @function + .align 2 +at32ap_low_level_init: + lddpc sp, sp_init /* Initialize the GOT pointer */ lddpc r6, got_init @@ -90,6 +198,7 @@ got_init: * Relocate the u-boot image into RAM and continue from there. * Does not return. */ + .section .text.relocate_code,"ax",@progbits .global relocate_code .type relocate_code,@function relocate_code: @@ -162,3 +271,5 @@ in_ram: .align 2 got_init_reloc: .long 3b - _GLOBAL_OFFSET_TABLE_ + + .size relocate_code, . - relocate_code diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile index 92dcc16..5091781 100644 --- a/cpu/mips/Makefile +++ b/cpu/mips/Makefile @@ -25,13 +25,16 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o -COBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \ - cpu.o interrupts.o incaip_clock.o -SOBJS = incaip_wdt.o cache.o +SOBJS-y = cache.o +COBJS-y = cpu.o interrupts.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o +COBJS-$(CONFIG_INCA_IP) += asc_serial.o incaip_clock.o +COBJS-$(CONFIG_PURPLE) += asc_serial.o +COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) START := $(addprefix $(obj),$(START)) all: $(obj).depend $(START) $(LIB) diff --git a/cpu/mips/asc_serial.c b/cpu/mips/asc_serial.c index 3498b61..be686c2 100644 --- a/cpu/mips/asc_serial.c +++ b/cpu/mips/asc_serial.c @@ -4,8 +4,6 @@ #include <config.h> -#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP) - #ifdef CONFIG_PURPLE #define serial_init asc_serial_init #define serial_putc asc_serial_putc @@ -368,4 +366,3 @@ int serial_tstc (void) return res; } -#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */ diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index d70c5fe..d0cf8e0 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -23,8 +23,6 @@ */ #include <config.h> -#ifdef CONFIG_AU1X00 - #if defined(CFG_DISCOVER_PHY) #error "PHY not supported yet" /* We just assume that we are running 100FD for now */ @@ -33,20 +31,20 @@ /* I assume ethernet behaves like au1000 */ -#ifdef CONFIG_AU1000 +#ifdef CONFIG_SOC_AU1000 /* Base address differ between cpu:s */ #define ETH0_BASE AU1000_ETH0_BASE #define MAC0_ENABLE AU1000_MAC0_ENABLE #else -#ifdef CONFIG_AU1100 +#ifdef CONFIG_SOC_AU1100 #define ETH0_BASE AU1100_ETH0_BASE #define MAC0_ENABLE AU1100_MAC0_ENABLE #else -#ifdef CONFIG_AU1500 +#ifdef CONFIG_SOC_AU1500 #define ETH0_BASE AU1500_ETH0_BASE #define MAC0_ENABLE AU1500_MAC0_ENABLE #else -#ifdef CONFIG_AU1550 +#ifdef CONFIG_SOC_AU1550 #define ETH0_BASE AU1550_ETH0_BASE #define MAC0_ENABLE AU1550_MAC0_ENABLE #else @@ -307,5 +305,3 @@ int au1x00_enet_initialize(bd_t *bis){ return 1; } - -#endif /* CONFIG_AU1X00 */ diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c index 42c668e..6309794 100644 --- a/cpu/mips/au1x00_serial.c +++ b/cpu/mips/au1x00_serial.c @@ -26,9 +26,6 @@ */ #include <config.h> - -#ifdef CONFIG_AU1X00 - #include <common.h> #include <asm/au1x00.h> @@ -132,4 +129,3 @@ int serial_tstc (void) } return 0; } -#endif /* CONFIG_SERIAL_AU1X00 */ diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c index dbf72dc..1ca8aaf 100644 --- a/cpu/mips/au1x00_usb_ohci.c +++ b/cpu/mips/au1x00_usb_ohci.c @@ -35,7 +35,7 @@ #include <config.h> -#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI) +#ifdef CONFIG_USB_OHCI /* #include <pci.h> no PCI on the AU1x00 */ diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 1b0efc3..ee5d411 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -23,7 +23,6 @@ */ #include <config.h> -#include <version.h> #include <asm/asm.h> #include <asm/regdef.h> #include <asm/mipsregs.h> @@ -41,7 +40,7 @@ */ #define MIPS_MAX_CACHE_SIZE 0x10000 -#define INDEX_BASE KSEG0 +#define INDEX_BASE CKSEG0 .macro cache_op op addr .set push @@ -219,7 +218,7 @@ NESTED(mips_cache_reset, 0, ra) /* * Now clear that much memory starting from zero. */ - PTR_LI a0, KSEG1 + PTR_LI a0, CKSEG1 PTR_ADDU a1, a0, v0 2: PTR_ADDIU a0, 64 f_fill64 a0, -64, zero @@ -319,7 +318,7 @@ LEAF(dcache_enable) .globl mips_cache_lock .ent mips_cache_lock mips_cache_lock: - li a1, K0BASE - CACHE_LOCK_SIZE + li a1, CKSEG0 - CACHE_LOCK_SIZE addu a0, a1 li a2, CACHE_LOCK_SIZE li a3, CFG_CACHELINE_SIZE diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index e267bba..0f58d25 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -66,10 +66,10 @@ void flush_cache(ulong start_addr, ulong size) void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) { - write_32bit_cp0_register(CP0_ENTRYLO0, low0); - write_32bit_cp0_register(CP0_PAGEMASK, pagemask); - write_32bit_cp0_register(CP0_ENTRYLO1, low1); - write_32bit_cp0_register(CP0_ENTRYHI, hi); - write_32bit_cp0_register(CP0_INDEX, index); + write_c0_entrylo0(low0); + write_c0_pagemask(pagemask); + write_c0_entrylo1(low1); + write_c0_entryhi(hi); + write_c0_index(index); tlb_write_indexed(); } diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S index 329386b..3ade3cd 100644 --- a/cpu/mips/incaip_wdt.S +++ b/cpu/mips/incaip_wdt.S @@ -24,7 +24,6 @@ #include <config.h> -#include <version.h> #include <asm/regdef.h> diff --git a/cpu/mips/start.S b/cpu/mips/start.S index d881879..09e4aab 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -23,7 +23,6 @@ */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #include <asm/mipsregs.h> diff --git a/cpu/mpc512x/traps.c b/cpu/mpc512x/traps.c index 8455c92..8000fab 100644 --- a/cpu/mpc512x/traps.c +++ b/cpu/mpc512x/traps.c @@ -34,7 +34,13 @@ DECLARE_GLOBAL_DATA_PTR; extern unsigned long search_exception_table(unsigned long); -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) +/* + * End of addressable memory. This may be less than the actual + * amount of memory on the system if we're unable to keep all + * the memory mapped in. + */ +extern ulong get_effective_memsize(void); +#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) /* * Trap & Exception support diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index 414759e..4d5d141 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -305,6 +305,11 @@ void ft_cpu_setup (void *blob, bd_t *bd) { char * cpu_path = "/cpus/" OF_CPU; +#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ + defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) + fdt_fixup_ethernet(blob, bd); +#endif + do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c index 75c6ab2..940f5c0 100644 --- a/cpu/mpc8260/pci.c +++ b/cpu/mpc8260/pci.c @@ -33,6 +33,10 @@ #include <mpc8260.h> #include <asm/m8260_pci.h> #include <asm/io.h> +#ifdef CONFIG_OF_LIBFDT +#include <libfdt.h> +#include <fdt_support.h> +#endif #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 DECLARE_GLOBAL_DATA_PTR; @@ -449,4 +453,12 @@ void pci_mpc8250_init (struct pci_controller *hose) immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); } +#if defined(CONFIG_OF_LIBFDT) +void ft_pci_setup(void *blob, bd_t *bd) +{ + do_fixup_by_prop_u32(blob, "device_type", "pci", 4, + "clock-frequency", bd->pci_clk, 1); +} +#endif + #endif /* CONFIG_PCI */ diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 36de78d..52e4476 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -44,7 +44,6 @@ int checkcpu(void) char buf[32]; int i; -#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} const struct cpu_type { char name[15]; u32 partid; @@ -358,3 +357,23 @@ int dma_xfer(void *dest, u32 count, void *src) return ((int)dma_check()); } #endif /*CONFIG_DDR_ECC*/ + +#ifdef CONFIG_TSEC_ENET +/* Default initializations for TSEC controllers. To override, + * create a board-specific function called: + * int board_eth_init(bd_t *bis) + */ + +extern int tsec_initialize(bd_t * bis, int index, char *devname); + +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_TSEC1) + tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); +#endif +#if defined(CONFIG_TSEC2) + tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); +#endif + return 0; +} +#endif diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index fb184d8..67c9e57 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -181,8 +181,13 @@ void cpu_init_f (volatile immap_t * im) /* System General Purpose Register */ #ifdef CFG_SICRH +#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313) + /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ + im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CFG_SICRH; +#else im->sysconf.sicrh = CFG_SICRH; #endif +#endif #ifdef CFG_SICRL im->sysconf.sicrl = CFG_SICRL; #endif diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 309eb30..c182174 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -557,7 +557,7 @@ invalidate_bats: mtspr IBAT1U, r0 mtspr IBAT2U, r0 mtspr IBAT3U, r0 -#if (CFG_HID2 & HID2_HBE) +#ifdef CONFIG_HIGH_BATS mtspr IBAT4U, r0 mtspr IBAT5U, r0 mtspr IBAT6U, r0 @@ -568,7 +568,7 @@ invalidate_bats: mtspr DBAT1U, r0 mtspr DBAT2U, r0 mtspr DBAT3U, r0 -#if (CFG_HID2 & HID2_HBE) +#ifdef CONFIG_HIGH_BATS mtspr DBAT4U, r0 mtspr DBAT5U, r0 mtspr DBAT6U, r0 @@ -655,7 +655,7 @@ setup_bats: mtspr DBAT3U, r3 isync -#if (CFG_HID2 & HID2_HBE) +#ifdef CONFIG_HIGH_BATS /* IBAT 4 */ addis r4, r0, CFG_IBAT4L@h ori r4, r4, CFG_IBAT4L@l diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 9873383..0d50549 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -29,41 +29,45 @@ #include <watchdog.h> #include <command.h> #include <asm/cache.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; -struct cpu_type { - char name[15]; - u32 soc_ver; +struct cpu_type cpu_type_list [] = { + CPU_TYPE_ENTRY(8533, 8533), + CPU_TYPE_ENTRY(8533, 8533_E), + CPU_TYPE_ENTRY(8540, 8540), + CPU_TYPE_ENTRY(8541, 8541), + CPU_TYPE_ENTRY(8541, 8541_E), + CPU_TYPE_ENTRY(8543, 8543), + CPU_TYPE_ENTRY(8543, 8543_E), + CPU_TYPE_ENTRY(8544, 8544), + CPU_TYPE_ENTRY(8544, 8544_E), + CPU_TYPE_ENTRY(8545, 8545), + CPU_TYPE_ENTRY(8545, 8545_E), + CPU_TYPE_ENTRY(8547, 8547_E), + CPU_TYPE_ENTRY(8548, 8548), + CPU_TYPE_ENTRY(8548, 8548_E), + CPU_TYPE_ENTRY(8555, 8555), + CPU_TYPE_ENTRY(8555, 8555_E), + CPU_TYPE_ENTRY(8560, 8560), + CPU_TYPE_ENTRY(8567, 8567), + CPU_TYPE_ENTRY(8567, 8567_E), + CPU_TYPE_ENTRY(8568, 8568), + CPU_TYPE_ENTRY(8568, 8568_E), + CPU_TYPE_ENTRY(8572, 8572), + CPU_TYPE_ENTRY(8572, 8572_E), }; -#define CPU_TYPE_ENTRY(x) {#x, SVR_##x} +struct cpu_type *identify_cpu(u32 ver) +{ + int i; + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) + if (cpu_type_list[i].soc_ver == ver) + return &cpu_type_list[i]; -struct cpu_type cpu_type_list [] = { - CPU_TYPE_ENTRY(8533), - CPU_TYPE_ENTRY(8533_E), - CPU_TYPE_ENTRY(8540), - CPU_TYPE_ENTRY(8541), - CPU_TYPE_ENTRY(8541_E), - CPU_TYPE_ENTRY(8543), - CPU_TYPE_ENTRY(8543_E), - CPU_TYPE_ENTRY(8544), - CPU_TYPE_ENTRY(8544_E), - CPU_TYPE_ENTRY(8545), - CPU_TYPE_ENTRY(8545_E), - CPU_TYPE_ENTRY(8547_E), - CPU_TYPE_ENTRY(8548), - CPU_TYPE_ENTRY(8548_E), - CPU_TYPE_ENTRY(8555), - CPU_TYPE_ENTRY(8555_E), - CPU_TYPE_ENTRY(8560), - CPU_TYPE_ENTRY(8567), - CPU_TYPE_ENTRY(8567_E), - CPU_TYPE_ENTRY(8568), - CPU_TYPE_ENTRY(8568_E), - CPU_TYPE_ENTRY(8572), - CPU_TYPE_ENTRY(8572_E), -}; + return NULL; +} int checkcpu (void) { @@ -74,9 +78,13 @@ int checkcpu (void) uint fam; uint ver; uint major, minor; - int i; - u32 ddr_ratio; + struct cpu_type *cpu; +#ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; +#else + u32 ddr_ratio = 0; +#endif svr = get_svr(); ver = SVR_SOC_VER(svr); @@ -85,14 +93,15 @@ int checkcpu (void) puts("CPU: "); - for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) - if (cpu_type_list[i].soc_ver == ver) { - puts(cpu_type_list[i].name); - break; - } + cpu = identify_cpu(ver); + if (cpu) { + puts(cpu->name); - if (i == ARRAY_SIZE(cpu_type_list)) + if (svr & 0x80000) + puts("E"); + } else { puts("Unknown"); + } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); @@ -118,7 +127,7 @@ int checkcpu (void) puts("Clock Configuration:\n"); printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); - ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + switch (ddr_ratio) { case 0x0: printf(" DDR:%4lu MHz (%lu MT/s data rate), ", @@ -159,7 +168,7 @@ int checkcpu (void) } #ifdef CONFIG_CPM2 - printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); + printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); @@ -279,3 +288,98 @@ int dma_xfer(void *dest, uint count, void *src) { return dma_check(); } #endif +/* + * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF) + * are hardcoded as "1"."size" is the number or entries, not a sizeof. + */ +void upmconfig (uint upm, uint * table, uint size) +{ + int i, mdr, mad, old_mad = 0; + volatile u32 *mxmr; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + int loopval = 0x00004440; + volatile u32 *brp,*orp; + volatile u8* dummy = NULL; + int upmmask; + + switch (upm) { + case UPMA: + mxmr = &lbc->mamr; + upmmask = BR_MS_UPMA; + break; + case UPMB: + mxmr = &lbc->mbmr; + upmmask = BR_MS_UPMB; + break; + case UPMC: + mxmr = &lbc->mcmr; + upmmask = BR_MS_UPMC; + break; + default: + printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); + hang(); + } + + /* Find the address for the dummy write transaction */ + for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; + i++, brp += 2, orp += 2) { + + /* Look for a valid BR with selected UPM */ + if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) { + dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT); + break; + } + } + + if (i == 8) { + printf("Error: %s() could not find matching BR\n", __FUNCTION__); + hang(); + } + + for (i = 0; i < size; i++) { + /* 1 */ + out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */ + /* 2 */ + out_be32(&lbc->mdr, table[i]); + /* 3 */ + mdr = in_be32(&lbc->mdr); + /* 4 */ + *(volatile u8 *)dummy = 0; + /* 5 */ + do { + mad = in_be32(mxmr) & 0x3f; + } while (mad <= old_mad && !(!mad && i == (size-1))); + old_mad = mad; + } + out_be32(mxmr, loopval); /* OP_NORMAL */ +} + +#if defined(CONFIG_TSEC_ENET) || defined(CONFIGMPC85XX_FEC) +/* Default initializations for TSEC controllers. To override, + * create a board-specific function called: + * int board_eth_init(bd_t *bis) + */ + +extern int tsec_initialize(bd_t * bis, int index, char *devname); + +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_TSEC1) + tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); +#endif +#if defined(CONFIG_TSEC2) + tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); +#endif +#if defined(CONFIG_MPC85XX_FEC) + tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME); +#else +#if defined(CONFIG_TSEC3) + tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); +#endif +#if defined(CONFIG_TSEC4) + tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); +#endif +#endif + return 0; +} +#endif diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index e3240b5..736aef1 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -148,6 +148,12 @@ void cpu_init_early_f(void) } #endif + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + init_laws(); invalidate_tlb(0); init_tlbs(); @@ -168,12 +174,6 @@ void cpu_init_f (void) disable_tlb(14); disable_tlb(15); - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - #ifdef CONFIG_CPM2 config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR); #endif @@ -254,16 +254,7 @@ void cpu_init_f (void) int cpu_init_r(void) { -#ifdef CONFIG_CLEAR_LAW0 -#ifdef CONFIG_FSL_LAW - disable_law(0); -#else - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); - - /* clear alternate boot location LAW (used for sdram, or ddr bank) */ - ecm->lawar0 = 0; -#endif -#endif + puts ("L2: "); #if defined(CONFIG_L2_CACHE) volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; @@ -281,17 +272,17 @@ int cpu_init_r(void) case 0x20000000: if (ver == SVR_8548 || ver == SVR_8548_E || ver == SVR_8544 || ver == SVR_8568_E) { - printf ("L2 cache 512KB:"); + puts ("512 KB "); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; } else { - printf ("L2 cache 256KB:"); + puts("256 KB "); /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ cache_ctl = 0xc8000000; } break; case 0x10000000: - printf ("L2 cache 256KB:"); + puts("256 KB "); if (ver == SVR_8544 || ver == SVR_8544_E) { cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ } @@ -299,18 +290,18 @@ int cpu_init_r(void) case 0x30000000: case 0x00000000: default: - printf ("L2 cache unknown size (0x%08x)\n", cache_ctl); + printf(" unknown size (0x%08x)\n", cache_ctl); return -1; } if (l2cache->l2ctl & 0x80000000) { - printf(" already enabled."); + puts("already enabled"); l2srbar = l2cache->l2srbar0; #ifdef CFG_INIT_L2_ADDR if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) { l2srbar = CFG_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR); + printf("moving to 0x%08x", CFG_INIT_L2_ADDR); } #endif /* CFG_INIT_L2_ADDR */ puts("\n"); @@ -318,10 +309,10 @@ int cpu_init_r(void) asm("msync;isync"); l2cache->l2ctl = cache_ctl; /* invalidate & enable */ asm("msync;isync"); - printf(" enabled\n"); + puts("enabled\n"); } #else - printf("L2 cache: disabled\n"); + puts("disabled\n"); #endif #ifdef CONFIG_QE uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */ diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index bb87740..92952e6 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -26,6 +26,7 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> +#include <asm/processor.h> extern void ft_qe_setup(void *blob); #ifdef CONFIG_MP @@ -77,6 +78,131 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #endif +#ifdef CONFIG_L2_CACHE +/* return size in kilobytes */ +static inline u32 l2cache_size(void) +{ + volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; + volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; + u32 ver = SVR_SOC_VER(get_svr()); + + switch (l2siz_field) { + case 0x0: + break; + case 0x1: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8541_E || + ver == SVR_8555 || ver == SVR_8555_E) + return 128; + else + return 256; + break; + case 0x2: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8541_E || + ver == SVR_8555 || ver == SVR_8555_E) + return 256; + else + return 512; + break; + case 0x3: + return 1024; + break; + } + + return 0; +} + +static inline void ft_fixup_l2cache(void *blob) +{ + int len, off; + u32 *ph; + struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); + char compat_buf[38]; + + const u32 line_size = 32; + const u32 num_ways = 8; + const u32 size = l2cache_size() * 1024; + const u32 num_sets = size / (line_size * num_ways); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + if (off < 0) { + debug("no cpu node fount\n"); + return; + } + + ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); + + if (ph == NULL) { + debug("no next-level-cache property\n"); + return ; + } + + off = fdt_node_offset_by_phandle(blob, *ph); + if (off < 0) { + printf("%s: %s\n", __func__, fdt_strerror(off)); + return ; + } + + if (cpu) { + len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller", + cpu->name); + sprintf(&compat_buf[len + 1], "cache"); + } + fdt_setprop(blob, off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, off, "cache-block-size", line_size); + fdt_setprop_cell(blob, off, "cache-line-size", line_size); + fdt_setprop_cell(blob, off, "cache-size", size); + fdt_setprop_cell(blob, off, "cache-sets", num_sets); + fdt_setprop_cell(blob, off, "cache-level", 2); + fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf)); +} +#else +#define ft_fixup_l2cache(x) +#endif + +static inline void ft_fixup_cache(void *blob) +{ + int off; + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + + while (off != -FDT_ERR_NOTFOUND) { + u32 l1cfg0 = mfspr(SPRN_L1CFG0); + u32 l1cfg1 = mfspr(SPRN_L1CFG1); + u32 isize, iline_size, inum_sets, inum_ways; + u32 dsize, dline_size, dnum_sets, dnum_ways; + + /* d-side config */ + dsize = (l1cfg0 & 0x7ff) * 1024; + dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; + dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; + dnum_sets = dsize / (dline_size * dnum_ways); + + fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); + fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size); + fdt_setprop_cell(blob, off, "d-cache-size", dsize); + fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); + + /* i-side config */ + isize = (l1cfg1 & 0x7ff) * 1024; + inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; + iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; + inum_sets = isize / (iline_size * inum_ways); + + fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); + fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size); + fdt_setprop_cell(blob, off, "i-cache-size", isize); + fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); + + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + + ft_fixup_l2cache(blob); +} + + void ft_cpu_setup(void *blob, bd_t *bd) { #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ @@ -114,4 +240,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_MP ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); #endif + + ft_fixup_cache(blob); } diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index e3a8249..8e321eb 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1090,7 +1090,7 @@ setup_laws_and_tlbs(unsigned int memsize) */ #ifdef CONFIG_FSL_LAW - set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR); + set_next_law(CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR); #endif /* diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 2381fb0..0eab694 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -50,10 +50,12 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0; extern unsigned long search_exception_table(unsigned long); /* - * End of memory as shown by board info and determined by DDR setup. + * End of addressable memory. This may be less than the actual + * amount of memory on the system if we're unable to keep all + * the memory mapped in. */ -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) - +extern ulong get_effective_memsize(void); +#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) static __inline__ void set_tsr(unsigned long val) { @@ -214,10 +216,10 @@ MachineCheckException(struct pt_regs *regs) if (machinecheck_count > 1) { regs->nip += 4; /* skip offending instruction */ - printf("Skipping current instr, Returning to 0x%08x\n", + printf("Skipping current instr, Returning to 0x%08lx\n", regs->nip); } else { - printf("Returning back to 0x%08x\n",regs->nip); + printf("Returning back to 0x%08lx\n",regs->nip); } } @@ -300,7 +302,7 @@ ExtIntException(struct pt_regs *regs) printf("External Interrupt Exception at PC: %lx, SR: %lx, vector=%lx", regs->nip, regs->msr, regs->trap); vect = pic->iack0; - printf(" irq IACK0@%05x=%d\n",&pic->iack0,vect); + printf(" irq IACK0@%05x=%d\n",(int)&pic->iack0,vect); show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); machinecheck_count++; @@ -308,7 +310,7 @@ ExtIntException(struct pt_regs *regs) printf("Returning back to 0x%08x\n",regs->nip); #else regs->nip += 4; /* skip offending instruction */ - printf("Skipping current instr, Returning to 0x%08x\n",regs->nip); + printf("Skipping current instr, Returning to 0x%08lx\n",regs->nip); #endif } diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 3c74764..7d2b591 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -26,6 +26,7 @@ #include <watchdog.h> #include <command.h> #include <asm/cache.h> +#include <asm/mmu.h> #include <mpc86xx.h> #include <asm/fsl_law.h> @@ -268,13 +269,14 @@ dma_xfer(void *dest, uint count, void *src) /* * Print out the state of various machine registers. - * Currently prints out LAWs and BR0/OR0 + * Currently prints out LAWs, BR0/OR0, and BATs */ void mpc86xx_reginfo(void) { immap_t *immap = (immap_t *)CFG_IMMR; ccsr_lbc_t *lbc = &immap->im_lbc; + print_bats(); print_laws(); printf ("Local Bus Controller Registers\n" @@ -288,3 +290,29 @@ void mpc86xx_reginfo(void) printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7)); } + +#ifdef CONFIG_TSEC_ENET +/* Default initializations for TSEC controllers. To override, + * create a board-specific function called: + * int board_eth_init(bd_t *bis) + */ + +extern int tsec_initialize(bd_t * bis, int index, char *devname); + +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_TSEC1) + tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); +#endif +#if defined(CONFIG_TSEC2) + tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); +#endif +#if defined(CONFIG_TSEC3) + tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); +#endif +#if defined(CONFIG_TSEC4) + tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); +#endif + return 0; +} +#endif /* CONFIG_TSEC_ENET */ diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 0efd855..78ba1ea 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -119,8 +119,5 @@ void cpu_init_f(void) */ int cpu_init_r(void) { -#ifdef CONFIG_FSL_LAW - disable_law(0); -#endif return 0; } diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 5cc0c26..e26db7c 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -1183,7 +1183,7 @@ spd_sdram(void) * Set up LAWBAR for DDR 1 space. */ #ifdef CONFIG_FSL_LAW - set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV); + set_next_law(CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV); #endif debug("Interleaved memory size is 0x%08lx\n", memsize_total); @@ -1238,7 +1238,7 @@ spd_sdram(void) * Set up LAWBAR for DDR 1 space. */ #ifdef CONFIG_FSL_LAW - set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1); + set_next_law(CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1); #endif } @@ -1265,7 +1265,7 @@ spd_sdram(void) * Set up LAWBAR for DDR 2 space. */ #ifdef CONFIG_FSL_LAW - set_law(8, + set_next_law( (ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE), law_size_ddr2, LAW_TRGT_IF_DDR_2); #endif diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index 04c2e13..5695c3e 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -43,7 +43,13 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0; /* Returns 0 if exception not found and fixup otherwise. */ extern unsigned long search_exception_table(unsigned long); -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) +/* + * End of addressable memory. This may be less than the actual + * amount of memory on the system if we're unable to keep all + * the memory mapped in. + */ +extern ulong get_effective_memsize(void); +#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) /* * Trap & Exception support diff --git a/cpu/nios/spi.c b/cpu/nios/spi.c index f37146b..6408180 100644 --- a/cpu/nios/spi.c +++ b/cpu/nios/spi.c @@ -63,10 +63,10 @@ static char quickhex (int i) return hex_digit[i]; } -static void memdump (void *pv, int num) +static void memdump (const void *pv, int num) { int i; - unsigned char *pc = (unsigned char *) pv; + const unsigned char *pc = (const unsigned char *) pv; for (i = 0; i < num; i++) printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); @@ -83,26 +83,64 @@ static void memdump (void *pv, int num) #endif /* DEBUG */ +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct spi_slave *slave; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + slave->bus = bus; + slave->cs = cs; + + /* TODO: Add support for different modes and speeds */ + + return slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + +} + /* * SPI transfer: * * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf * for more informations. */ -int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) +int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout, + void *din, unsigned long flags) { + const u8 *txd = dout; + u8 *rxd = din; int j; - DPRINT(("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n", - (int)chipsel, *(uint *)dout, *(uint *)din, bitlen)); + DPRINT(("spi_xfer: slave %u:%u dout %08X din %08X bitlen %d\n", + slave->bus, slave->cs, *(uint *)dout, *(uint *)din, bitlen)); - memdump((void*)dout, (bitlen + 7) / 8); + memdump(dout, (bitlen + 7) / 8); - if(chipsel != NULL) { - chipsel(1); /* select the target chip */ - } + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); - if (bitlen > CFG_NIOS_SPIBITS) { /* leave chip select active */ + if (!(flags & SPI_XFER_END) || bitlen > CFG_NIOS_SPIBITS) { + /* leave chip select active */ spi->control |= NIOS_SPI_SSO; } @@ -114,11 +152,11 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) while ((spi->status & NIOS_SPI_TRDY) == 0) ; - spi->txdata = (unsigned)(dout[j]); + spi->txdata = (unsigned)(txd[j]); while ((spi->status & NIOS_SPI_RRDY) == 0) ; - din[j] = (unsigned char)(spi->rxdata & 0xff); + rxd[j] = (unsigned char)(spi->rxdata & 0xff); #elif (CFG_NIOS_SPIBITS == 16) j++, j++) { @@ -126,15 +164,15 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) while ((spi->status & NIOS_SPI_TRDY) == 0) ; if ((j+1) < ((bitlen + 7) / 8)) - spi->txdata = (unsigned)((dout[j] << 8) | dout[j+1]); + spi->txdata = (unsigned)((txd[j] << 8) | txd[j+1]); else - spi->txdata = (unsigned)(dout[j] << 8); + spi->txdata = (unsigned)(txd[j] << 8); while ((spi->status & NIOS_SPI_RRDY) == 0) ; - din[j] = (unsigned char)((spi->rxdata >> 8) & 0xff); + rxd[j] = (unsigned char)((spi->rxdata >> 8) & 0xff); if ((j+1) < ((bitlen + 7) / 8)) - din[j+1] = (unsigned char)(spi->rxdata & 0xff); + rxd[j+1] = (unsigned char)(spi->rxdata & 0xff); #else #error "*** unsupported value of CFG_NIOS_SPIBITS ***" @@ -142,15 +180,14 @@ int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) } - if (bitlen > CFG_NIOS_SPIBITS) { + if (bitlen > CFG_NIOS_SPIBITS && (flags & SPI_XFER_END)) { spi->control &= ~NIOS_SPI_SSO; } - if(chipsel != NULL) { - chipsel(0); /* deselect the target chip */ - } + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); - memdump((void*)din, (bitlen + 7) / 8); + memdump(din, (bitlen + 7) / 8); return 0; } diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index b9cf5cb..9efcede 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -53,6 +53,8 @@ #include <ppc4xx.h> #include <asm/mmu.h> +#include "ecc.h" + #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR)) @@ -79,157 +81,6 @@ void __spd_ddr_init_hang (void) } void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))); -/*----------------------------------------------------------------------------- - | Memory Controller Options 0 - +-----------------------------------------------------------------------------*/ -#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */ -#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */ -#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */ -#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */ -#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */ -#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */ -#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */ -#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */ -#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */ -#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */ -#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */ -#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */ - -/*----------------------------------------------------------------------------- - | Memory Controller Options 1 - +-----------------------------------------------------------------------------*/ -#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */ -#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */ - -/*-----------------------------------------------------------------------------+ - | SDRAM DEVPOT Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_DEVOPT_DLL 0x80000000 -#define SDRAM_DEVOPT_DS 0x40000000 - -/*-----------------------------------------------------------------------------+ - | SDRAM MCSTS Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_MCSTS_MRSC 0x80000000 -#define SDRAM_MCSTS_SRMS 0x40000000 -#define SDRAM_MCSTS_CIS 0x20000000 - -/*----------------------------------------------------------------------------- - | SDRAM Refresh Timer Register - +-----------------------------------------------------------------------------*/ -#define SDRAM_RTR_RINT_MASK 0xFFFF0000 -#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK) -#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) - -/*-----------------------------------------------------------------------------+ - | SDRAM UABus Base Address Reg - +-----------------------------------------------------------------------------*/ -#define SDRAM_UABBA_UBBA_MASK 0x0000000F - -/*-----------------------------------------------------------------------------+ - | Memory Bank 0-7 configuration - +-----------------------------------------------------------------------------*/ -#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */ -#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */ -#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */ -#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */ -#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */ -#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */ -#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */ -#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */ -#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */ -#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */ -#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */ -#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */ -#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */ -#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */ -#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */ - -/*-----------------------------------------------------------------------------+ - | SDRAM TR0 Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_TR0_SDWR_MASK 0x80000000 -#define SDRAM_TR0_SDWR_2_CLK 0x00000000 -#define SDRAM_TR0_SDWR_3_CLK 0x80000000 -#define SDRAM_TR0_SDWD_MASK 0x40000000 -#define SDRAM_TR0_SDWD_0_CLK 0x00000000 -#define SDRAM_TR0_SDWD_1_CLK 0x40000000 -#define SDRAM_TR0_SDCL_MASK 0x01800000 -#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000 -#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000 -#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000 -#define SDRAM_TR0_SDPA_MASK 0x000C0000 -#define SDRAM_TR0_SDPA_2_CLK 0x00040000 -#define SDRAM_TR0_SDPA_3_CLK 0x00080000 -#define SDRAM_TR0_SDPA_4_CLK 0x000C0000 -#define SDRAM_TR0_SDCP_MASK 0x00030000 -#define SDRAM_TR0_SDCP_2_CLK 0x00000000 -#define SDRAM_TR0_SDCP_3_CLK 0x00010000 -#define SDRAM_TR0_SDCP_4_CLK 0x00020000 -#define SDRAM_TR0_SDCP_5_CLK 0x00030000 -#define SDRAM_TR0_SDLD_MASK 0x0000C000 -#define SDRAM_TR0_SDLD_1_CLK 0x00000000 -#define SDRAM_TR0_SDLD_2_CLK 0x00004000 -#define SDRAM_TR0_SDRA_MASK 0x0000001C -#define SDRAM_TR0_SDRA_6_CLK 0x00000000 -#define SDRAM_TR0_SDRA_7_CLK 0x00000004 -#define SDRAM_TR0_SDRA_8_CLK 0x00000008 -#define SDRAM_TR0_SDRA_9_CLK 0x0000000C -#define SDRAM_TR0_SDRA_10_CLK 0x00000010 -#define SDRAM_TR0_SDRA_11_CLK 0x00000014 -#define SDRAM_TR0_SDRA_12_CLK 0x00000018 -#define SDRAM_TR0_SDRA_13_CLK 0x0000001C -#define SDRAM_TR0_SDRD_MASK 0x00000003 -#define SDRAM_TR0_SDRD_2_CLK 0x00000001 -#define SDRAM_TR0_SDRD_3_CLK 0x00000002 -#define SDRAM_TR0_SDRD_4_CLK 0x00000003 - -/*-----------------------------------------------------------------------------+ - | SDRAM TR1 Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_TR1_RDSS_MASK 0xC0000000 -#define SDRAM_TR1_RDSS_TR0 0x00000000 -#define SDRAM_TR1_RDSS_TR1 0x40000000 -#define SDRAM_TR1_RDSS_TR2 0x80000000 -#define SDRAM_TR1_RDSS_TR3 0xC0000000 -#define SDRAM_TR1_RDSL_MASK 0x00C00000 -#define SDRAM_TR1_RDSL_STAGE1 0x00000000 -#define SDRAM_TR1_RDSL_STAGE2 0x00400000 -#define SDRAM_TR1_RDSL_STAGE3 0x00800000 -#define SDRAM_TR1_RDCD_MASK 0x00000800 -#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000 -#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800 -#define SDRAM_TR1_RDCT_MASK 0x000001FF -#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK) -#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0) -#define SDRAM_TR1_RDCT_MIN 0x00000000 -#define SDRAM_TR1_RDCT_MAX 0x000001FF - -/*-----------------------------------------------------------------------------+ - | SDRAM WDDCTR Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000 -#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000 -#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000 -#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000 -#define SDRAM_WDDCTR_DCD_MASK 0x000001FF - -/*-----------------------------------------------------------------------------+ - | SDRAM CLKTR Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 -#define SDRAM_CLKTR_CLKP_0DEG 0x00000000 -#define SDRAM_CLKTR_CLKP_90DEG 0x40000000 -#define SDRAM_CLKTR_CLKP_180DEG 0x80000000 -#define SDRAM_CLKTR_DCDT_MASK 0x000001FF - -/*-----------------------------------------------------------------------------+ - | SDRAM DLYCAL Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC -#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) -#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) - /*-----------------------------------------------------------------------------+ | General Definition +-----------------------------------------------------------------------------*/ @@ -296,10 +147,6 @@ static void program_tr0(unsigned long *dimm_populated, unsigned long num_dimm_banks); static void program_tr1(void); -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long num_bytes); -#endif - static unsigned long program_bxcr(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -418,7 +265,7 @@ long int spd_sdram(void) { /* * If ecc is enabled, initialize the parity bits. */ - program_ecc(total_size); + ecc_init(CFG_SDRAM_BASE, total_size); #endif return total_size; @@ -1402,45 +1249,4 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, return(bank_base_addr); } - -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long num_bytes) -{ - unsigned long bank_base_addr; - unsigned long current_address; - unsigned long end_address; - unsigned long address_increment; - unsigned long cfg0; - - /* - * get Memory Controller Options 0 data - */ - mfsdram(mem_cfg0, cfg0); - - /* - * reset the bank_base address - */ - bank_base_addr = CFG_SDRAM_BASE; - - if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) { - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN); - - if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) - address_increment = 4; - else - address_increment = 8; - - current_address = (unsigned long)(bank_base_addr); - end_address = (unsigned long)(bank_base_addr) + num_bytes; - - while (current_address < end_address) { - *((unsigned long*)current_address) = 0x00000000; - current_address += address_increment; - } - - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | - SDRAM_CFG0_MCHK_CHK); - } -} -#endif /* CONFIG_DDR_ECC */ #endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index ec76b71..c28fc46 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -3,9 +3,12 @@ * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a * DDR2 controller (non Denali Core). Those currently are: * - * 405: 405EX + * 405: 405EX(r) * 440/460: 440SP/440SPe/460EX/460GT * + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson@nuovations.com> + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -45,6 +48,8 @@ #include <asm/mmu.h> #include <asm/cache.h> +#include "ecc.h" + #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT)) @@ -384,7 +389,7 @@ static unsigned long sdram_memsize(void) * banks appropriately. If Auto Memory Configuration is * not used, it is assumed that no DIMM is plugged *-----------------------------------------------------------------------------*/ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; unsigned char spd0[MAX_SPD_BYTES]; @@ -3064,9 +3069,127 @@ static void ppc440sp_sdram_register_dump(void) dcr_data = mfdcr(SDRAM_R3BAS); printf(" MQ3_B0BAS = 0x%08X\n", dcr_data); } -#else +#else /* !defined(DEBUG) */ static void ppc440sp_sdram_register_dump(void) { } -#endif -#endif /* CONFIG_SPD_EEPROM */ +#endif /* defined(DEBUG) */ +#elif defined(CONFIG_405EX) +/*----------------------------------------------------------------------------- + * Function: initdram + * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory + * banks. The configuration is performed using static, compile- + * time parameters. + *---------------------------------------------------------------------------*/ +phys_size_t initdram(int board_type) +{ + /* + * Only run this SDRAM init code once. For NAND booting + * targets like Kilauea, we call initdram() early from the + * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot(). + * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT) + * which calls initdram() again. This time the controller + * mustn't be reconfigured again since we're already running + * from SDRAM. + */ +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + unsigned long val; + + /* Set Memory Bank Configuration Registers */ + + mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF); + mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF); + mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF); + mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF); + + /* Set Memory Clock Timing Register */ + + mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR); + + /* Set Refresh Time Register */ + + mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR); + + /* Set SDRAM Timing Registers */ + + mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1); + mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2); + mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3); + + /* Set Mode and Extended Mode Registers */ + + mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE); + mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE); + + /* Set Memory Controller Options 1 Register */ + + mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1); + + /* Set Manual Initialization Control Registers */ + + mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0); + mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1); + mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2); + mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3); + mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4); + mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5); + mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6); + mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7); + mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8); + mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9); + mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10); + mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11); + mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12); + mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13); + mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14); + mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15); + + /* Set On-Die Termination Registers */ + + mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT); + mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0); + mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1); + + /* Set Write Timing Register */ + + mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR); + + /* + * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and + * SDRAM0_MCOPT2[IPTR] = 1 + */ + + mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT | + SDRAM_MCOPT2_IPTR_EXECUTE)); + + /* + * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the + * completion of initialization. + */ + + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP); + + /* Set Delay Control Registers */ + + mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR); + mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC); + mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC); + mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC); + + /* + * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1: + */ + + mfsdram(SDRAM_MCOPT2, val); + mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE); + +#if defined(CONFIG_DDR_ECC) + ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); +#endif /* defined(CONFIG_DDR_ECC) */ +#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ + + return (CFG_MBYTES_SDRAM << 20); +} +#endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */ diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c index ffbc222..a7587d4 100644 --- a/cpu/ppc4xx/4xx_uart.c +++ b/cpu/ppc4xx/4xx_uart.c @@ -98,14 +98,14 @@ DECLARE_GLOBAL_DATA_PTR; #define UDIV_SUBTRACT 0 #define UART0_SDR sdr_uart0 #define UART1_SDR sdr_uart1 -#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPe) || \ +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) #define UART2_SDR sdr_uart2 #endif -#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) #define UART3_SDR sdr_uart3 #endif diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 178c5c6..800bb41 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -45,6 +45,7 @@ COBJS += cpu.o COBJS += cpu_init.o COBJS += denali_data_eye.o COBJS += denali_spd_ddr2.o +COBJS += ecc.o COBJS += fdt.o COBJS += gpio.o COBJS += i2c.o diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c index 22156dd..8b2954c 100644 --- a/cpu/ppc4xx/commproc.c +++ b/cpu/ppc4xx/commproc.c @@ -30,29 +30,25 @@ #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) -#if defined(CFG_POST_ALT_WORD_ADDR) -void post_word_store (ulong a) -{ - out_be32((void *)CFG_POST_ALT_WORD_ADDR, a); -} +#if defined(CFG_POST_WORD_ADDR) +# define _POST_ADDR ((CFG_OCM_DATA_ADDR) + (CFG_POST_WORD_ADDR)) +#elif defined(CFG_POST_ALT_WORD_ADDR) +# define _POST_ADDR (CFG_POST_ALT_WORD_ADDR) +#endif -ulong post_word_load (void) -{ - return in_be32((void *)CFG_POST_ALT_WORD_ADDR); -} -#else /* CFG_POST_ALT_WORD_ADDR */ void post_word_store (ulong a) { - volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); - *(volatile ulong *) save_addr = a; + volatile void *save_addr = (volatile void *)(_POST_ADDR); + + out_be32(save_addr, a); } ulong post_word_load (void) { - volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); - return *(volatile ulong *) save_addr; + volatile void *save_addr = (volatile void *)(_POST_ADDR); + + return in_be32(save_addr); } -#endif /* CFG_POST_ALT_WORD_ADDR */ #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 42eabfe..ac64279 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -32,73 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; #endif -#ifdef CFG_INIT_DCACHE_CS -# if (CFG_INIT_DCACHE_CS == 0) -# define PBxAP pb0ap -# define PBxCR pb0cr -# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) -# define PBxAP_VAL CFG_EBC_PB0AP -# define PBxCR_VAL CFG_EBC_PB0CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 1) -# define PBxAP pb1ap -# define PBxCR pb1cr -# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) -# define PBxAP_VAL CFG_EBC_PB1AP -# define PBxCR_VAL CFG_EBC_PB1CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 2) -# define PBxAP pb2ap -# define PBxCR pb2cr -# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) -# define PBxAP_VAL CFG_EBC_PB2AP -# define PBxCR_VAL CFG_EBC_PB2CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 3) -# define PBxAP pb3ap -# define PBxCR pb3cr -# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) -# define PBxAP_VAL CFG_EBC_PB3AP -# define PBxCR_VAL CFG_EBC_PB3CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 4) -# define PBxAP pb4ap -# define PBxCR pb4cr -# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) -# define PBxAP_VAL CFG_EBC_PB4AP -# define PBxCR_VAL CFG_EBC_PB4CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 5) -# define PBxAP pb5ap -# define PBxCR pb5cr -# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) -# define PBxAP_VAL CFG_EBC_PB5AP -# define PBxCR_VAL CFG_EBC_PB5CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 6) -# define PBxAP pb6ap -# define PBxCR pb6cr -# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) -# define PBxAP_VAL CFG_EBC_PB6AP -# define PBxCR_VAL CFG_EBC_PB6CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 7) -# define PBxAP pb7ap -# define PBxCR pb7cr -# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) -# define PBxAP_VAL CFG_EBC_PB7AP -# define PBxCR_VAL CFG_EBC_PB7CR -# endif -# endif -#endif /* CFG_INIT_DCACHE_CS */ - #ifndef CFG_PLL_RECONFIG #define CFG_PLL_RECONFIG 0 #endif @@ -205,8 +138,8 @@ void reconfigure_pll(u32 new_cpu_freq) void cpu_init_f (void) { -#if defined(CONFIG_WATCHDOG) - unsigned long val; +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_460EX) + u32 val; #endif reconfigure_pll(CFG_PLL_RECONFIG); @@ -339,6 +272,22 @@ cpu_init_f (void) reset_4xx_watchdog(); #endif /* CONFIG_WATCHDOG */ + +#if defined(CONFIG_460EX) + /* + * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and + * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata + * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA + */ + mfsdr(SDR0_AHB_CFG, val); + val |= 0x80; + val &= ~0x40; + mtsdr(SDR0_AHB_CFG, val); + mfsdr(SDR0_USB2HOST_CFG, val); + val &= ~0xf00; + val |= 0x400; + mtsdr(SDR0_USB2HOST_CFG, val); +#endif /* CONFIG_460EX */ } /* @@ -353,24 +302,6 @@ int cpu_init_r (void) uint pvr = get_pvr(); #endif -#ifdef CFG_INIT_DCACHE_CS - /* - * Flush and invalidate dcache, then disable CS for temporary stack. - * Afterwards, this CS can be used for other purposes - */ - dcache_disable(); /* flush and invalidate dcache */ - mtebc(PBxAP, 0); - mtebc(PBxCR, 0); /* disable CS for temporary stack */ - -#if (defined(PBxAP_VAL) && defined(PBxCR_VAL)) - /* - * Write new value into CS register - */ - mtebc(PBxAP, PBxAP_VAL); - mtebc(PBxCR, PBxCR_VAL); -#endif -#endif /* CFG_INIT_DCACHE_CS */ - /* * Write Ethernetaddress into on-chip register */ diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index ad805b9..3bd6375 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -1022,7 +1022,7 @@ static void program_ddr0_44(unsigned long dimm_ranks[], * banks appropriately. If Auto Memory Configuration is * not used, it is assumed that no DIMM is plugged *-----------------------------------------------------------------------------*/ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; unsigned long dimm_ranks[MAXDIMMS]; diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c new file mode 100644 index 0000000..a2eb07b --- /dev/null +++ b/cpu/ppc4xx/ecc.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson@nuovations.com> + * + * (C) Copyright 2005-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2002 + * Jun Gu, Artesyn Technology, jung@artesyncp.com + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will abe useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * This file implements generic DRAM ECC initialization for + * PowerPC processors using a SDRAM DDR/DDR2 controller, + * including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and + * 460EX/GT. + */ + +#include <common.h> +#include <ppc4xx.h> +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/processor.h> +#include <asm/io.h> + +#include "ecc.h" + +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \ + defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) +#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) +/* + * void ecc_init() + * + * Description: + * This routine initializes a range of DRAM ECC memory with known + * data and enables ECC checking. + * + * TO DO: + * - Improve performance by utilizing cache. + * - Further generalize to make usable by other 4xx variants (e.g. + * 440EPx, et al). + * + * Input(s): + * start - A pointer to the start of memory covered by ECC requiring + * initialization. + * size - The size, in bytes, of the memory covered by ECC requiring + * initialization. + * + * Output(s): + * start - A pointer to the start of memory covered by ECC with + * CFG_ECC_PATTERN written to all locations and ECC data + * primed. + * + * Returns: + * N/A + */ +void ecc_init(unsigned long * const start, unsigned long size) +{ + const unsigned long pattern = CFG_ECC_PATTERN; + unsigned long * const end = (unsigned long * const)((long)start + size); + unsigned long * current = start; + unsigned long mcopt1; + long increment; + + if (start >= end) + return; + + mfsdram(SDRAM_ECC_CFG, mcopt1); + + /* Enable ECC generation without checking or reporting */ + + mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) | + SDRAM_ECC_CFG_MCHK_GEN)); + + increment = sizeof(u32); + +#if defined(CONFIG_440) + /* + * Look at the geometry of SDRAM (data width) to determine whether we + * can skip words when writing. + */ + + if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32) + increment = sizeof(u64); +#endif /* defined(CONFIG_440) */ + + while (current < end) { + *current = pattern; + current = (unsigned long *)((long)current + increment); + } + + /* Wait until the writes are finished. */ + + sync(); + + /* Enable ECC generation with checking and no reporting */ + + mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) | + SDRAM_ECC_CFG_MCHK_CHK)); +} +#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ +#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */ diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h new file mode 100644 index 0000000..aecf291 --- /dev/null +++ b/cpu/ppc4xx/ecc.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson@nuovations.com> + * + * Copyright (c) 2007 DENX Software Engineering, GmbH + * Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will abe useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * This file implements ECC initialization for PowerPC processors + * using the SDRAM DDR2 controller, including the 405EX(r), + * 440SP(E), 460EX and 460GT. + * + */ + +#ifndef _ECC_H_ +#define _ECC_H_ + +#if !defined(CFG_ECC_PATTERN) +#define CFG_ECC_PATTERN 0x00000000 +#endif /* !defined(CFG_ECC_PATTERN) */ + +/* + * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register + * compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT + * we need to make some processor dependant defines used later on by the + * driver. + */ + +/* For 440GP/GX/EP/GR */ +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) +#define SDRAM_ECC_CFG SDRAM_CFG0 +#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_CFG0_MCHK_MASK +#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_CFG0_MCHK_GEN +#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_CFG0_MCHK_CHK +#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_CFG0_DMWD_MASK +#define SDRAM_ECC_CFG_DMWD_32 SDRAM_CFG0_DMWD_32 +#endif + +/* For 405EX/440SP/SPe/460EX/GT */ +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) +#define SDRAM_ECC_CFG SDRAM_MCOPT1 +#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_MCOPT1_MCHK_MASK +#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_MCOPT1_MCHK_GEN +#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_MCOPT1_MCHK_CHK +#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_MCOPT1_DMWD_MASK +#define SDRAM_ECC_CFG_DMWD_32 SDRAM_MCOPT1_DMWD_32 +#endif + +extern void ecc_init(unsigned long * const start, unsigned long size); + +#endif /* _ECC_H_ */ diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c index 37d3fa8..df99f53 100644 --- a/cpu/ppc4xx/gpio.c +++ b/cpu/ppc4xx/gpio.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -52,7 +52,7 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val) } mask = 0x80000000 >> pin; - mask2 = 0xc0000000 >> (pin2 << 1); + mask2 = 0xc0000000 >> pin2; /* first set TCR to 0 */ out_be32((void *)GPIO0_TCR + offs, in_be32((void *)GPIO0_TCR + offs) & ~mask); diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 2724d91..7d60ad6 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -31,6 +31,7 @@ #include <ppc4xx.h> #include <asm/processor.h> #include "sdram.h" +#include "ecc.h" #ifdef CONFIG_SDRAM_BANK0 @@ -163,7 +164,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh) /* * Autodetect onboard SDRAM on 405 platforms */ -void sdram_init(void) +phys_size_t initdram(int board_type) { ulong speed; ulong sdtr1; @@ -231,9 +232,15 @@ void sdram_init(void) mtsdram(mem_mcopt1, 0); } #endif - return; + + /* + * OK, size detected -> all done + */ + return mb0cf[i].size; } } + + return 0; } #else /* CONFIG_440 */ @@ -332,49 +339,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value) *tr1_value = (first_good + last_bad) / 2; } -#ifdef CONFIG_SDRAM_ECC -static void ecc_init(ulong start, ulong size) -{ - ulong current_addr; /* current byte address */ - ulong end_addr; /* end of memory region */ - ulong addr_inc; /* address skip between writes */ - ulong cfg0_reg; /* for restoring ECC state */ - - /* - * TODO: Enable dcache before running this test (speedup) - */ - - mfsdram(mem_cfg0, cfg0_reg); - mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN); - - /* - * look at geometry of SDRAM (data width) to determine whether we - * can skip words when writing - */ - if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32) - addr_inc = 4; - else - addr_inc = 8; - - current_addr = start; - end_addr = start + size; - - while (current_addr < end_addr) { - *((ulong *)current_addr) = 0x00000000; - current_addr += addr_inc; - } - - /* - * TODO: Flush dcache and disable it again - */ - - /* - * Enable ecc checking and parity errors - */ - mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK); -} -#endif - /* * Autodetect onboard DDR SDRAM on 440 platforms * @@ -382,7 +346,7 @@ static void ecc_init(ulong start, ulong size) * so this should be extended for other future boards * using this routine! */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { int i; int tr1_bank1; diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index ef47ffc..34bd721 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -754,7 +754,7 @@ ulong get_OPB_freq (void) return sys_info.freqOPB; } -#elif defined(CONFIG_XILINX_ML300) +#elif defined(CONFIG_XILINX_405) extern void get_sys_info (sys_info_t * sysInfo); extern ulong get_PCI_freq (void); diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 0008170..426bf3c 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -3,6 +3,8 @@ * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson@nuovations.com> * * See file CREDITS for list of people who contributed to this * project. @@ -79,34 +81,100 @@ # if (CFG_INIT_DCACHE_CS == 0) # define PBxAP pb0ap # define PBxCR pb0cr +# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) +# define PBxAP_VAL CFG_EBC_PB0AP +# define PBxCR_VAL CFG_EBC_PB0CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 1) # define PBxAP pb1ap # define PBxCR pb1cr +# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) +# define PBxAP_VAL CFG_EBC_PB1AP +# define PBxCR_VAL CFG_EBC_PB1CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 2) # define PBxAP pb2ap # define PBxCR pb2cr +# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) +# define PBxAP_VAL CFG_EBC_PB2AP +# define PBxCR_VAL CFG_EBC_PB2CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 3) # define PBxAP pb3ap # define PBxCR pb3cr +# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) +# define PBxAP_VAL CFG_EBC_PB3AP +# define PBxCR_VAL CFG_EBC_PB3CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 4) # define PBxAP pb4ap # define PBxCR pb4cr +# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) +# define PBxAP_VAL CFG_EBC_PB4AP +# define PBxCR_VAL CFG_EBC_PB4CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 5) # define PBxAP pb5ap # define PBxCR pb5cr +# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) +# define PBxAP_VAL CFG_EBC_PB5AP +# define PBxCR_VAL CFG_EBC_PB5CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 6) # define PBxAP pb6ap # define PBxCR pb6cr +# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) +# define PBxAP_VAL CFG_EBC_PB6AP +# define PBxCR_VAL CFG_EBC_PB6CR +# endif # endif # if (CFG_INIT_DCACHE_CS == 7) # define PBxAP pb7ap # define PBxCR pb7cr +# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) +# define PBxAP_VAL CFG_EBC_PB7AP +# define PBxCR_VAL CFG_EBC_PB7CR +# endif +# endif +# ifndef PBxAP_VAL +# define PBxAP_VAL 0 +# endif +# ifndef PBxCR_VAL +# define PBxCR_VAL 0 +# endif +/* + * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB + * used as temporary stack pointer for the primordial stack + */ +# ifndef CFG_INIT_DCACHE_PBxAR +# define CFG_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(2) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +# endif /* CFG_INIT_DCACHE_PBxAR */ +# ifndef CFG_INIT_DCACHE_PBxCR +# define CFG_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR) | \ + EBC_BXCR_BS_64MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) +# endif /* CFG_INIT_DCACHE_PBxCR */ +# ifndef CFG_INIT_RAM_PATTERN +# define CFG_INIT_RAM_PATTERN 0xDEADDEAD # endif #endif /* CFG_INIT_DCACHE_CS */ @@ -114,6 +182,27 @@ #error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END! #endif +/* + * Unless otherwise overriden, enable two 128MB cachable instruction regions + * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering + * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions. + */ +#if !defined(CFG_FLASH_BASE) +/* If not already defined, set it to the "last" 128MByte region */ +# define CFG_FLASH_BASE 0xf8000000 +#endif +#if !defined(CFG_ICACHE_SACR_VALUE) +# define CFG_ICACHE_SACR_VALUE \ + (PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + ( 0 << 20)) | \ + PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \ + PPC_128MB_SACR_VALUE(CFG_FLASH_BASE)) +#endif /* !defined(CFG_ICACHE_SACR_VALUE) */ + +#if !defined(CFG_DCACHE_SACR_VALUE) +# define CFG_DCACHE_SACR_VALUE \ + (0x00000000) +#endif /* !defined(CFG_DCACHE_SACR_VALUE) */ + #define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ @@ -128,7 +217,6 @@ .extern ext_bus_cntlr_init - .extern sdram_init #ifdef CONFIG_NAND_U_BOOT .extern reconfig_tlb0 #endif @@ -401,97 +489,6 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ /* Continue from 'normal' start */ /*----------------------------------------------------------------*/ 2: - -#if defined(CONFIG_NAND_SPL) -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) - /* - * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM) - */ - lis r2,0x7fff - ori r2,r2,0xffff - mfdcr r1,isram0_dpc - and r1,r1,r2 /* Disable parity check */ - mtdcr isram0_dpc,r1 - mfdcr r1,isram0_pmeg - and r1,r1,r2 /* Disable pwr mgmt */ - mtdcr isram0_pmeg,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) - lis r1,0x4000 /* BAS = 8000_0000 */ - ori r1,r1,0x4580 /* 16k */ - mtdcr isram0_sb0cr,r1 -#endif -#endif -#if defined(CONFIG_440EP) - /* - * On 440EP with no internal SRAM, we setup SDRAM very early - * and copy the NAND_SPL to SDRAM and jump to it - */ - /* Clear Dcache to use as RAM */ - addis r3,r0,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l - addis r4,r0,CFG_INIT_RAM_END@h - ori r4,r4,CFG_INIT_RAM_END@l - rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ran3 - addi r5,r5,0x0001 -..d_ran3: - mtctr r5 -..d_ag3: - dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag3 - /*----------------------------------------------------------------*/ - /* Setup the stack in internal SRAM */ - /*----------------------------------------------------------------*/ - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l - li r0,0 - stwu r0,-4(r1) - stwu r0,-4(r1) /* Terminate call chain */ - - stwu r1,-8(r1) /* Save back chain and move SP */ - lis r0,RESET_VECTOR@h /* Address of reset vector */ - ori r0,r0, RESET_VECTOR@l - stwu r1,-8(r1) /* Save back chain and move SP */ - stw r0,+12(r1) /* Save return addr (underflow vect) */ - sync - bl early_sdram_init - sync -#endif /* CONFIG_440EP */ - - /* - * Copy SPL from cache into internal SRAM - */ - li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 - mtctr r4 - lis r2,CFG_NAND_BOOT_SPL_SRC@h - ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l - lis r3,CFG_NAND_BOOT_SPL_DST@h - ori r3,r3,CFG_NAND_BOOT_SPL_DST@l -spl_loop: - lwzu r4,4(r2) - stwu r4,4(r3) - bdnz spl_loop - - /* - * Jump to code in RAM - */ - bl 00f -00: mflr r10 - lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h - ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l - sub r10,r10,r3 - addi r10,r10,28 - mtlr r10 - blr - -start_ram: - sync - isync -#endif /* CONFIG_NAND_SPL */ - bl 3f b _start @@ -746,7 +743,7 @@ _start: stw r0,+12(r1) /* Save return addr (underflow vect) */ #ifdef CONFIG_NAND_SPL - bl nand_boot /* will not return */ + bl nand_boot_common /* will not return */ #else GET_GOT @@ -840,16 +837,16 @@ _start: /* make sure above stores all comlete before going on */ sync - /*----------------------------------------------------------------------- */ - /* Enable two 128MB cachable regions. */ - /*----------------------------------------------------------------------- */ - addis r1,r0,0xc000 - addi r1,r1,0x0001 - mticcr r1 /* instruction cache */ + /* Set-up icache cacheability. */ + lis r1, CFG_ICACHE_SACR_VALUE@h + ori r1, r1, CFG_ICACHE_SACR_VALUE@l + mticcr r1 + isync - addis r1,r0,0x0000 - addi r1,r1,0x0000 - mtdccr r1 /* data cache */ + /* Set-up dcache cacheability. */ + lis r1, CFG_DCACHE_SACR_VALUE@h + ori r1, r1, CFG_DCACHE_SACR_VALUE@l + mtdccr r1 addis r1,r0,CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ @@ -892,39 +889,33 @@ _start: /* dbsr is cleared by setting bits to 1) */ mtdbsr r4 /* clear/reset the dbsr */ - /*----------------------------------------------------------------------- */ - /* Invalidate I and D caches. Enable I cache for defined memory regions */ - /* to speed things up. Leave the D cache disabled for now. It will be */ - /* enabled/left disabled later based on user selected menu options. */ - /* Be aware that the I cache may be disabled later based on the menu */ - /* options as well. See miscLib/main.c. */ - /*----------------------------------------------------------------------- */ + /* Invalidate the i- and d-caches. */ bl invalidate_icache bl invalidate_dcache - /*----------------------------------------------------------------------- */ - /* Enable two 128MB cachable regions. */ - /*----------------------------------------------------------------------- */ - lis r4,0xc000 - ori r4,r4,0x0001 - mticcr r4 /* instruction cache */ + /* Set-up icache cacheability. */ + lis r4, CFG_ICACHE_SACR_VALUE@h + ori r4, r4, CFG_ICACHE_SACR_VALUE@l + mticcr r4 isync - lis r4,0x0000 - ori r4,r4,0x0000 - mtdccr r4 /* data cache */ + /* Set-up dcache cacheability. */ + lis r4, CFG_DCACHE_SACR_VALUE@h + ori r4, r4, CFG_DCACHE_SACR_VALUE@l + mtdccr r4 -#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX) +#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) /*----------------------------------------------------------------------- */ /* Tune the speed and size for flash CS0 */ /*----------------------------------------------------------------------- */ bl ext_bus_cntlr_init #endif + #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) /* - * Boards like the Kilauea (405EX) don't have OCM and can't use - * DCache for init-ram. So setup stack here directly after the - * SDRAM is initialized. + * For boards that don't have OCM and can't use the data cache + * for their primordial stack, setup stack here directly after the + * SDRAM is initialized in ext_bus_cntlr_init. */ lis r1, CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ @@ -1007,83 +998,90 @@ _start: #endif /* CONFIG_405EZ */ #endif -#ifdef CONFIG_NAND_SPL + /*----------------------------------------------------------------------- */ + /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ + /*----------------------------------------------------------------------- */ +#ifdef CFG_INIT_DCACHE_CS + li r4, PBxAP + mtdcr ebccfga, r4 + lis r4, CFG_INIT_DCACHE_PBxAR@h + ori r4, r4, CFG_INIT_DCACHE_PBxAR@l + mtdcr ebccfgd, r4 + + addi r4, 0, PBxCR + mtdcr ebccfga, r4 + lis r4, CFG_INIT_DCACHE_PBxCR@h + ori r4, r4, CFG_INIT_DCACHE_PBxCR@l + mtdcr ebccfgd, r4 + /* - * Copy SPL from cache into internal SRAM + * Enable the data cache for the 128MB storage access control region + * at CFG_INIT_RAM_ADDR. */ - li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 - mtctr r4 - lis r2,CFG_NAND_BOOT_SPL_SRC@h - ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l - lis r3,CFG_NAND_BOOT_SPL_DST@h - ori r3,r3,CFG_NAND_BOOT_SPL_DST@l -spl_loop: - lwzu r4,4(r2) - stwu r4,4(r3) - bdnz spl_loop + mfdccr r4 + oris r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h + ori r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l + mtdccr r4 /* - * Jump to code in RAM + * Preallocate data cache lines to be used to avoid a subsequent + * cache miss and an ensuing machine check exception when exceptions + * are enabled. */ - bl 00f -00: mflr r10 - lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h - ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l - sub r10,r10,r3 - addi r10,r10,28 - mtlr r10 - blr + li r0, 0 -start_ram: - sync - isync -#endif /* CONFIG_NAND_SPL */ + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l - /*----------------------------------------------------------------------- */ - /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ - /*----------------------------------------------------------------------- */ -#ifdef CFG_INIT_DCACHE_CS - /*----------------------------------------------------------------------- */ - /* Memory Bank x (nothingness) initialization 1GB+64MEG */ - /* used as temporary stack pointer for stage0 */ - /*----------------------------------------------------------------------- */ - li r4,PBxAP - mtdcr ebccfga,r4 - lis r4,0x0380 - ori r4,r4,0x0480 - mtdcr ebccfgd,r4 - - addi r4,0,PBxCR - mtdcr ebccfga,r4 - lis r4,0x400D - ori r4,r4,0xa000 - mtdcr ebccfgd,r4 - - /* turn on data cache for this region */ - lis r4,0x0080 - mtdccr r4 + lis r4, CFG_INIT_RAM_END@h + ori r4, r4, CFG_INIT_RAM_END@l + + /* + * Convert the size, in bytes, to the number of cache lines/blocks + * to preallocate. + */ + clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) + srwi r5, r4, L1_CACHE_SHIFT + beq ..load_counter + addi r5, r5, 0x0001 +..load_counter: + mtctr r5 - /* set stack pointer and clear stack to known value */ + /* Preallocate the computed number of cache blocks. */ +..alloc_dcache_block: + dcba r0, r3 + addi r3, r3, L1_CACHE_BYTES + bdnz ..alloc_dcache_block + sync - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l + /* + * Load the initial stack pointer and data area and convert the size, + * in bytes, to the number of words to initialize to a known value. + */ + lis r1, CFG_INIT_RAM_ADDR@h + ori r1, r1, CFG_INIT_SP_OFFSET@l - li r4,2048 /* we store 2048 words to stack */ + lis r4, (CFG_INIT_RAM_END >> 2)@h + ori r4, r4, (CFG_INIT_RAM_END >> 2)@l mtctr r4 - lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */ - ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */ + lis r2, CFG_INIT_RAM_ADDR@h + ori r2, r2, CFG_INIT_RAM_END@l - lis r4,0xdead /* we store 0xdeaddead in the stack */ - ori r4,r4,0xdead + lis r4, CFG_INIT_RAM_PATTERN@h + ori r4, r4, CFG_INIT_RAM_PATTERN@l ..stackloop: - stwu r4,-4(r2) + stwu r4, -4(r2) bdnz ..stackloop - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + /* + * Make room for stack frame header and clear final stack frame so + * that stack backtraces terminate cleanly. + */ + stwu r0, -4(r1) + stwu r0, -4(r1) + /* * Set up a dummy frame to store reset vector as return address. * this causes stack underflow to reset board. @@ -1120,13 +1118,8 @@ start_ram: stw r0, +12(r1) /* Save return addr (underflow vect) */ #endif /* CFG_INIT_DCACHE_CS */ - /*----------------------------------------------------------------------- */ - /* Initialize SDRAM Controller */ - /*----------------------------------------------------------------------- */ - bl sdram_init - #ifdef CONFIG_NAND_SPL - bl nand_boot /* will not return */ + bl nand_boot_common /* will not return */ #else GET_GOT /* initialize GOT access */ @@ -1328,33 +1321,72 @@ in32r: * This "function" does not return, instead it continues in RAM * after relocating the monitor code. * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize + * r3 = Relocated stack pointer + * r4 = Relocated global data pointer + * r5 = Relocated text pointer */ .globl relocate_code relocate_code: -#ifdef CONFIG_4xx_DCACHE +#if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) /* - * We need to flush the Init Data before the dcache will be - * invalidated + * We need to flush the initial global data (gd_t) before the dcache + * will be invalidated. */ - /* save regs */ - mr r9,r3 - mr r10,r4 - mr r11,r5 + /* Save registers */ + mr r9, r3 + mr r10, r4 + mr r11, r5 - mr r3,r4 - addi r4,r4,0x200 /* should be enough for init data */ + /* Flush initial global data range */ + mr r3, r4 + addi r4, r4, CFG_GBL_DATA_SIZE@l bl flush_dcache_range - /* restore regs */ - mr r3,r9 - mr r4,r10 - mr r5,r11 -#endif +#if defined(CFG_INIT_DCACHE_CS) + /* + * Undo the earlier data cache set-up for the primordial stack and + * data area. First, invalidate the data cache and then disable data + * cacheability for that area. Finally, restore the EBC values, if + * any. + */ + + /* Invalidate the primordial stack and data area in cache */ + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l + + lis r4, CFG_INIT_RAM_END@h + ori r4, r4, CFG_INIT_RAM_END@l + add r4, r4, r3 + + bl invalidate_dcache_range + + /* Disable cacheability for the region */ + mfdccr r3 + lis r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h + ori r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l + and r3, r3, r4 + mtdccr r3 + + /* Restore the EBC parameters */ + li r3, PBxAP + mtdcr ebccfga, r3 + lis r3, PBxAP_VAL@h + ori r3, r3, PBxAP_VAL@l + mtdcr ebccfgd, r3 + + li r3, PBxCR + mtdcr ebccfga, r3 + lis r3, PBxCR_VAL@h + ori r3, r3, PBxCR_VAL@l + mtdcr ebccfgd, r3 +#endif /* defined(CFG_INIT_DCACHE_CS) */ + + /* Restore registers */ + mr r3, r9 + mr r4, r10 + mr r5, r11 +#endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */ #ifdef CFG_INIT_RAM_DCACHE /* @@ -1396,13 +1428,13 @@ relocate_code: addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */ #else addi r1,r0,0x0000 /* Default TLB entry is #0 */ -#endif +#endif /* CFG_TLB_FOR_BOOT_FLASH */ tlbre r0,r1,0x0002 /* Read contents */ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ tlbwe r0,r1,0x0002 /* Save it out */ sync isync -#endif +#endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */ mr r1, r3 /* Set new stack pointer */ mr r9, r4 /* Save copy of Init Data pointer */ mr r10, r5 /* Save copy of Destination Address */ @@ -1425,7 +1457,7 @@ relocate_code: /* First our own GOT */ add r14, r14, r15 - /* the the one used by the C code */ + /* then the one used by the C code */ add r30, r30, r15 /* @@ -2024,3 +2056,75 @@ pll_wait: blr function_epilog(mftlb1) #endif /* CONFIG_440 */ + +#if defined(CONFIG_NAND_SPL) +/* + * void nand_boot_relocate(dst, src, bytes) + * + * r3 = Destination address to copy code to (in SDRAM) + * r4 = Source address to copy code from + * r5 = size to copy in bytes + */ +nand_boot_relocate: + mr r6,r3 + mr r7,r4 + mflr r8 + + /* + * Copy SPL from icache into SDRAM + */ + subi r3,r3,4 + subi r4,r4,4 + srwi r5,r5,2 + mtctr r5 +..spl_loop: + lwzu r0,4(r4) + stwu r0,4(r3) + bdnz ..spl_loop + + /* + * Calculate "corrected" link register, so that we "continue" + * in execution in destination range + */ + sub r3,r7,r6 /* r3 = src - dst */ + sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ + mtlr r8 + blr + +nand_boot_common: + /* + * First initialize SDRAM. It has to be available *before* calling + * nand_boot(). + */ + lis r3,CFG_SDRAM_BASE@h + ori r3,r3,CFG_SDRAM_BASE@l + bl initdram + + /* + * Now copy the 4k SPL code into SDRAM and continue execution + * from there. + */ + lis r3,CFG_NAND_BOOT_SPL_DST@h + ori r3,r3,CFG_NAND_BOOT_SPL_DST@l + lis r4,CFG_NAND_BOOT_SPL_SRC@h + ori r4,r4,CFG_NAND_BOOT_SPL_SRC@l + lis r5,CFG_NAND_BOOT_SPL_SIZE@h + ori r5,r5,CFG_NAND_BOOT_SPL_SIZE@l + bl nand_boot_relocate + + /* + * We're running from SDRAM now!!! + * + * It is necessary for 4xx systems to relocate from running at + * the original location (0xfffffxxx) to somewhere else (SDRAM + * preferably). This is because CS0 needs to be reconfigured for + * NAND access. And we can't reconfigure this CS when currently + * "running" from it. + */ + + /* + * Finally call nand_boot() to load main NAND U-Boot image from + * NAND and jump to it. + */ + bl nand_boot /* will not return */ +#endif /* CONFIG_NAND_SPL */ diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index 38b6f89..8b7e32a 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -170,7 +170,7 @@ MachineCheckException(struct pt_regs *regs) val = get_esr(); -#if !defined(CONFIG_440) +#if !defined(CONFIG_440) && !defined(CONFIG_405EX) if (val& ESR_IMCP) { printf("Instruction"); mtspr(ESR, val & ~ESR_IMCP); @@ -179,7 +179,7 @@ MachineCheckException(struct pt_regs *regs) } printf(" machine check.\n"); -#elif defined(CONFIG_440) +#elif defined(CONFIG_440) || defined(CONFIG_405EX) if (val& ESR_IMCP){ printf("Instruction Synchronous Machine Check exception\n"); mtspr(SPRN_ESR, val & ~ESR_IMCP); @@ -187,10 +187,15 @@ MachineCheckException(struct pt_regs *regs) val = mfspr(MCSR); if (val & MCSR_IB) printf("Instruction Read PLB Error\n"); +#if defined(CONFIG_440) if (val & MCSR_DRB) printf("Data Read PLB Error\n"); if (val & MCSR_DWB) printf("Data Write PLB Error\n"); +#else + if (val & MCSR_DB) + printf("Data PLB Error\n"); +#endif if (val & MCSR_TLBP) printf("TLB Parity Error\n"); if (val & MCSR_ICP){ diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c index 039ce0f..4495a80 100644 --- a/cpu/pxa/mmc.c +++ b/cpu/pxa/mmc.c @@ -119,7 +119,7 @@ mmc_block_read(uchar * dst, ulong src, ulong len) MMC_RDTO = 0xffff; MMC_NOB = 1; MMC_BLKLEN = len; - mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl, + mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl, MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK | MMC_CMDAT_DATA_EN); @@ -568,7 +568,7 @@ mmc_init(int verbose) MMC_SPI = MMC_SPI_DISABLE; /* reset */ - mmc_cmd(MMC_CMD_RESET, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0); + mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0); udelay(200000); retries = 3; while (retries--) { @@ -578,7 +578,10 @@ mmc_init(int verbose) break; } - resp = mmc_cmd(SD_CMD_APP_OP_COND, 0x0020, 0, MMC_CMDAT_R3 | (retries < 2 ? 0 : MMC_CMDAT_INIT)); /* Select 3.2-3.3 and 3.3-3.4V */ + /* Select 3.2-3.3 and 3.3-3.4V */ + resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0020, 0, + MMC_CMDAT_R3 | (retries < 2 ? 0 + : MMC_CMDAT_INIT)); if (resp[0] & 0x80000000) { mmc_dev.if_type = IF_TYPE_SD; debug("Detected SD card\n"); @@ -616,7 +619,7 @@ mmc_init(int verbose) memcpy(cid_resp, resp, sizeof(cid_resp)); /* MMC exists, get CSD too */ - resp = mmc_cmd(MMC_CMD_SET_RCA, 0, 0, MMC_CMDAT_R1); + resp = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, 0, 0, MMC_CMDAT_R1); if (IF_TYPE_SD == mmc_dev.if_type) rca = ((resp[0] & 0xffff0000) >> 16); resp = mmc_cmd(MMC_CMD_SEND_CSD, rca, 0, MMC_CMDAT_R2); diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index 1cdb709..23005e2 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -128,7 +128,7 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ + cmp r0, r2 /* until source end address [r2] */ ble copy_loop #endif /* !CONFIG_SKIP_RELOCATE_UBOOT */ diff --git a/cpu/sh3/Makefile b/cpu/sh3/Makefile index 7679248..587413d 100644 --- a/cpu/sh3/Makefile +++ b/cpu/sh3/Makefile @@ -31,19 +31,27 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o -OBJS = cpu.o interrupts.o watchdog.o time.o cache.o +SOBJS = start.o +COBJS = cpu.o interrupts.o watchdog.o time.o cache.o -all: .depend $(START) $(LIB) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude $(obj).depend ######################################################################### diff --git a/cpu/sh4/Makefile b/cpu/sh4/Makefile index 1bb8bd7..d3c5eef 100644 --- a/cpu/sh4/Makefile +++ b/cpu/sh4/Makefile @@ -28,19 +28,27 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o -OBJS = cpu.o interrupts.o watchdog.o time.o cache.o +SOBJS = start.o +COBJS = cpu.o interrupts.o watchdog.o time.o cache.o -all: .depend $(START) $(LIB) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude $(obj).depend ######################################################################### |