diff options
Diffstat (limited to 'cpu')
76 files changed, 930 insertions, 707 deletions
diff --git a/cpu/74xx_7xx/config.mk b/cpu/74xx_7xx/config.mk index 417d99f..324f62b 100644 --- a/cpu/74xx_7xx/config.mk +++ b/cpu/74xx_7xx/config.mk @@ -23,4 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -ffixed-r29 -mstring +PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 17c7a83..8b765f1 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -35,6 +35,25 @@ #endif .globl _start _start: b reset +#ifdef CONFIG_ONENAND_IPL + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + +_hang: + .word do_hang + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 /* now 16*4=64 */ +#else ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -51,6 +70,7 @@ _not_used: .word not_used _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ +#endif /* CONFIG_ONENAND_IPL */ .global _end_vect _end_vect: @@ -139,7 +159,9 @@ relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ cmp r0, r1 /* don't reloc during debug */ +#ifndef CONFIG_ONENAND_IPL beq stack_setup +#endif /* CONFIG_ONENAND_IPL */ ldr r2, _armboot_start ldr r3, _bss_start @@ -156,26 +178,36 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ +#ifdef CONFIG_ONENAND_IPL + sub sp, r0, #128 /* leave 32 words for abort-stack */ +#else sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ +#endif /* CONFIG_ONENAND_IPL */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ mov r2, #0x00000000 /* clear */ +#ifndef CONFIG_ONENAND_IPL clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l +#endif ldr pc, _start_armboot +#ifdef CONFIG_ONENAND_IPL +_start_armboot: .word start_oneboot +#else _start_armboot: .word start_armboot +#endif /* @@ -214,6 +246,8 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ + +#ifndef CONFIG_ONENAND_IPL /* ************************************************************************* * @@ -326,10 +360,17 @@ cpu_init_crit: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm +#endif /* CONFIG_ONENAND_IPL */ /* * exception handlers */ +#ifdef CONFIG_ONENAND_IPL + .align 5 +do_hang: + ldr sp, _TEXT_BASE /* use 32 words about stack */ + bl hang /* hang and never return */ +#else /* !CONFIG_ONENAND IPL */ .align 5 undefined_instruction: get_bad_stack @@ -415,3 +456,4 @@ rstctl: .word PM_RSTCTRL_WKUP #endif +#endif /* CONFIG_ONENAND_IPL */ diff --git a/cpu/arm926ejs/at91cap9/Makefile b/cpu/arm926ejs/at91cap9/Makefile new file mode 100644 index 0000000..bf15e1e --- /dev/null +++ b/cpu/arm926ejs/at91cap9/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = ether.o timer.o spi.o usb.o +SOBJS = lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/at91cap9/config.mk b/cpu/arm926ejs/at91cap9/config.mk new file mode 100644 index 0000000..ca2cae1 --- /dev/null +++ b/cpu/arm926ejs/at91cap9/config.mk @@ -0,0 +1,2 @@ +PLATFORM_CPPFLAGS += -march=armv5te +PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) diff --git a/cpu/arm926ejs/at91cap9/ether.c b/cpu/arm926ejs/at91cap9/ether.c new file mode 100644 index 0000000..b7958d5 --- /dev/null +++ b/cpu/arm926ejs/at91cap9/ether.c @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop <at> leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/AT91CAP9.h> + +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); + +#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) +void at91cap9_eth_initialize(bd_t *bi) +{ + macb_eth_initialize(0, (void *)AT91C_BASE_MACB, 0x00); +} +#endif diff --git a/cpu/arm926ejs/at91cap9/lowlevel_init.S b/cpu/arm926ejs/at91cap9/lowlevel_init.S new file mode 100644 index 0000000..24d950c --- /dev/null +++ b/cpu/arm926ejs/at91cap9/lowlevel_init.S @@ -0,0 +1,43 @@ +/* + * AT91CAP9 setup stuff + * + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop <at> leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +.globl lowlevel_init +lowlevel_init: + + /* + * Clocks/SDRAM initialization is handled by at91bootstrap, + * no need to do it here... + */ + mov pc, lr + + .ltorg + +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/cpu/arm926ejs/at91cap9/spi.c b/cpu/arm926ejs/at91cap9/spi.c new file mode 100644 index 0000000..0953820 --- /dev/null +++ b/cpu/arm926ejs/at91cap9/spi.c @@ -0,0 +1,119 @@ +/* + * Driver for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <config.h> +#include <common.h> +#include <asm/hardware.h> + +#ifdef CONFIG_HAS_DATAFLASH +#include <dataflash.h> + +/* Max Value = 10MHz to be compliant to the Continuous Array Read function */ +#define AT91C_SPI_CLK 10000000 + +/* AC Characteristics: DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xFA << 16) +#define DATAFLASH_TCHS (0x8 << 24) + +#define AT91C_TIMEOUT_WRDY 200000 +#define AT91C_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */ +#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ + +void AT91F_SpiInit(void) +{ + /* Reset the SPI */ + AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SWRST; + + /* Configure SPI in Master Mode with No CS selected !!! */ + AT91C_BASE_SPI0->SPI_MR = + AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; + + /* Configure CS0 */ + AT91C_BASE_SPI0->SPI_CSR[0] = + AT91C_SPI_CPOL | + (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); +} + +void AT91F_SpiEnable(int cs) +{ + switch (cs) { + case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ + AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI0->SPI_MR |= + ((AT91C_SPI_PCS0_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); + break; + case 3: + AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI0->SPI_MR |= + ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); + break; + } + + /* SPI_Enable */ + AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SPIEN; +} + +unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) +{ + unsigned int timeout; + + pDesc->state = BUSY; + + AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + + /* Initialize the Transmit and Receive Pointer */ + AT91C_BASE_SPI0->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt; + AT91C_BASE_SPI0->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt; + + /* Intialize the Transmit and Receive Counters */ + AT91C_BASE_SPI0->SPI_RCR = pDesc->rx_cmd_size; + AT91C_BASE_SPI0->SPI_TCR = pDesc->tx_cmd_size; + + if (pDesc->tx_data_size != 0) { + /* Initialize the Next Transmit and Next Receive Pointer */ + AT91C_BASE_SPI0->SPI_RNPR = (unsigned int)pDesc->rx_data_pt; + AT91C_BASE_SPI0->SPI_TNPR = (unsigned int)pDesc->tx_data_pt; + + /* Intialize the Next Transmit and Next Receive Counters */ + AT91C_BASE_SPI0->SPI_RNCR = pDesc->rx_data_size; + AT91C_BASE_SPI0->SPI_TNCR = pDesc->tx_data_size; + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + timeout = 0; + + AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; + while (!(AT91C_BASE_SPI0->SPI_SR & AT91C_SPI_RXBUFF) && + ((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT)); + AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + pDesc->state = IDLE; + + if (timeout >= CFG_SPI_WRITE_TOUT) { + printf("Error Timeout\n\r"); + return DATAFLASH_ERROR; + } + + return DATAFLASH_OK; +} +#endif diff --git a/cpu/arm926ejs/at91cap9/timer.c b/cpu/arm926ejs/at91cap9/timer.c new file mode 100644 index 0000000..4110e15 --- /dev/null +++ b/cpu/arm926ejs/at91cap9/timer.c @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop <at> leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +/* + * We're using the AT91CAP9 PITC in 32 bit mode, by + * setting the 20 bit counter period to its maximum (0xfffff). + */ +#define TIMER_LOAD_VAL 0xfffff +#define READ_RESET_TIMER (AT91C_BASE_PITC->PITC_PIVR) +#define READ_TIMER (AT91C_BASE_PITC->PITC_PIIR) +#define TIMER_FREQ (AT91C_MASTER_CLOCK << 4) +#define TICKS_TO_USEC(ticks) ((ticks) / 6) + +ulong get_timer_masked(void); +ulong resettime; + +AT91PS_PITC p_pitc; + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init(void) +{ + /* + * Enable PITC Clock + * The clock is already enabled for system controller in boot + */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS; + + /* Enable PITC */ + AT91C_BASE_PITC->PITC_PIMR = AT91C_PITC_PITEN; + + /* Load PITC_PIMR with the right timer value */ + AT91C_BASE_PITC->PITC_PIMR |= TIMER_LOAD_VAL; + + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +static inline ulong get_timer_raw(void) +{ + ulong now = READ_TIMER; + if (now >= resettime) + return now - resettime; + else + return 0xFFFFFFFFUL - (resettime - now) ; +} + +void reset_timer_masked(void) +{ + resettime = READ_TIMER; +} + +ulong get_timer_masked(void) +{ + return TICKS_TO_USEC(get_timer_raw()); + +} + +void udelay_masked(unsigned long usec) +{ + ulong tmp; + + tmp = get_timer(0); + while (get_timer(tmp) < usec) /* our timer works in usecs */ + ; /* NOP */ +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + ulong now = get_timer_masked(); + + if (now >= base) + return now - base; + else + return TICKS_TO_USEC(0xFFFFFFFFUL) - (base - now) ; +} + +void udelay(unsigned long usec) +{ + udelay_masked(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + tbclk = CFG_HZ; + return tbclk; +} + +/* + * Reset the cpu by setting up the watchdog timer and let him time out + * on the AT91CAP9ADK board + */ +void reset_cpu(ulong ignored) +{ + /* this is the way Linux does it */ + AT91C_BASE_RSTC->RSTC_RCR = (0xA5 << 24) | + AT91C_RSTC_PROCRST | + AT91C_RSTC_PERRST; + + while (1); + /* Never reached */ +} diff --git a/cpu/arm926ejs/at91cap9/usb.c b/cpu/arm926ejs/at91cap9/usb.c new file mode 100644 index 0000000..69da5f3 --- /dev/null +++ b/cpu/arm926ejs/at91cap9/usb.c @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2006 + * DENX Software Engineering <mk <at> denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) +#ifdef CONFIG_AT91CAP9 + +#include <asm/arch/hardware.h> + +int usb_cpu_init(void) +{ + /* Enable USB host clock. */ + AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UHP; + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_UHP; + + return 0; +} + +int usb_cpu_stop(void) +{ + /* Disable USB host clock. */ + AT91C_BASE_PMC->PMC_PCDR = 1 << AT91C_ID_UHP; + AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_UHP; + return 0; +} + +int usb_cpu_init_fail(void) +{ + return usb_cpu_stop(); +} + +#endif /* CONFIG_AT91CAP9 */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c index c6b1dda..4a1a54d 100644 --- a/cpu/arm926ejs/davinci/timer.c +++ b/cpu/arm926ejs/davinci/timer.c @@ -61,6 +61,11 @@ davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE; #define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ) #define READ_TIMER timer->tim34 +/* Timer runs with CFG_HZ_CLOCK, currently 27MHz. To avoid wrap + around of timestamp already after min ~159s, divide it, e.g. by 16. + timestamp will then wrap around all min ~42min */ +#define DIV(x) ((x) >> 4) + static ulong timestamp; static ulong lastinc; @@ -101,20 +106,20 @@ void udelay(unsigned long usec) void reset_timer_masked(void) { - lastinc = READ_TIMER; + lastinc = DIV(READ_TIMER); timestamp = 0; } ulong get_timer_raw(void) { - ulong now = READ_TIMER; + ulong now = DIV(READ_TIMER); if (now >= lastinc) { /* normal mode */ timestamp += now - lastinc; } else { /* overflow ... */ - timestamp += now + TIMER_LOAD_VAL - lastinc; + timestamp += now + DIV(TIMER_LOAD_VAL) - lastinc; } lastinc = now; return timestamp; @@ -122,7 +127,7 @@ ulong get_timer_raw(void) ulong get_timer_masked(void) { - return(get_timer_raw() / TIMER_LOAD_VAL); + return(get_timer_raw() / DIV(TIMER_LOAD_VAL)); } void udelay_masked(unsigned long usec) diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c index 9cac969..33da56a 100644 --- a/cpu/arm926ejs/interrupts.c +++ b/cpu/arm926ejs/interrupts.c @@ -172,7 +172,7 @@ void do_irq (struct pt_regs *pt_regs) bad_mode (); } -#ifdef CONFIG_INTEGRATOR +#if defined(CONFIG_INTEGRATOR) || defined(CONFIG_AT91CAP9ADK) /* Timer functionality supplied by Integrator board (AP or CP) */ diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S index 725c663..297efe0 100644 --- a/cpu/arm926ejs/start.S +++ b/cpu/arm926ejs/start.S @@ -182,6 +182,9 @@ clbss_l:str r2, [r0] /* clear loop... */ cmp r0, r1 ble clbss_l + bl coloured_LED_init + bl red_LED_on + ldr pc, _start_armboot _start_armboot: @@ -198,8 +201,7 @@ _start_armboot: * ************************************************************************* */ - - +#ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* * flush v4 I/D caches @@ -225,6 +227,8 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + /* ************************************************************************* * diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c index a936e03..1fcfe75 100644 --- a/cpu/at32ap/hsdramc.c +++ b/cpu/at32ap/hsdramc.c @@ -38,6 +38,10 @@ unsigned long sdram_init(const struct sdram_info *info) unsigned long bus_hz; unsigned int i; + if (!info->refresh_period) + panic("ERROR: SDRAM refresh period == 0. " + "Please update the board code\n"); + tmp = (HSDRAMC1_BF(NC, info->col_bits - 8) | HSDRAMC1_BF(NR, info->row_bits - 11) | HSDRAMC1_BF(NB, info->bank_bits - 1) @@ -113,7 +117,7 @@ unsigned long sdram_init(const struct sdram_info *info) * 15.6 us is a typical value for a burst of length one */ bus_hz = get_sdram_clk_rate(); - hsdramc1_writel(TR, (156 * (bus_hz / 1000)) / 10000); + hsdramc1_writel(TR, info->refresh_period); printf("SDRAM: %u MB at address 0x%08lx\n", sdram_size >> 20, info->phys_addr); diff --git a/cpu/bf533/Makefile b/cpu/bf533/Makefile index dd4f299..ad48f1c 100644 --- a/cpu/bf533/Makefile +++ b/cpu/bf533/Makefile @@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o +SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o EXTRA = init_sdram_bootrom_initblock.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h index 25b96a9..9970b72 100644 --- a/cpu/bf533/bf533_serial.h +++ b/cpu/bf533/bf533_serial.h @@ -49,8 +49,8 @@ #include <asm/blackfin.h> #define SYNC_ALL __asm__ __volatile__ ("ssync;\n") -#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB; -#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB); +#define ACCESS_LATCH *pUART_LCR |= DLAB; +#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB); void serial_setbrg(void); static void local_put_char(char ch); diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S index 03aebe4..d9015c6 100644 --- a/cpu/bf533/cache.S +++ b/cpu/bf533/cache.S @@ -2,6 +2,7 @@ #include <asm/linkage.h> #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/mpu.h> .text .align 2 @@ -11,7 +12,7 @@ ENTRY(_blackfin_icache_flush_range) P0 = R2; P1 = R1; CSYNC; -1: + 1: IFLUSH[P0++]; CC = P0 < P1(iu); IF CC JUMP 1b(bp); diff --git a/cpu/bf533/config.mk b/cpu/bf533/config.mk index 6a713c3..2caa3cc 100644 --- a/cpu/bf533/config.mk +++ b/cpu/bf533/config.mk @@ -24,4 +24,4 @@ # MA 02110-1301 USA # -PLATFORM_RELFLAGS += -mcpu=bf533 -ffixed-P5 +PLATFORM_RELFLAGS += -mcpu=bf533 diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c index 8118861..edb771e 100644 --- a/cpu/bf533/cpu.c +++ b/cpu/bf533/cpu.c @@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2]; int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM) + __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) ); return 0; @@ -100,22 +100,18 @@ void icache_enable(void) } - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); - sti(); + SSYNC(); } void icache_disable(void) { - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); - sti(); + SSYNC(); } int icache_status(void) @@ -175,14 +171,12 @@ void dcache_enable(void) } } - cli(); temp = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - sync(); - sti(); + SSYNC(); } void dcache_disable(void) @@ -190,13 +184,11 @@ void dcache_disable(void) unsigned int *I0, *I1; int i; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); - sti(); + SSYNC(); /* after disable dcache, * clear it so we don't confuse the next application diff --git a/cpu/bf533/init_sdram.S b/cpu/bf533/init_sdram.S index e1a8e2f..67a99e4 100644 --- a/cpu/bf533/init_sdram.S +++ b/cpu/bf533/init_sdram.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (CONFIG_CCLK_DIV == 1) diff --git a/cpu/bf533/init_sdram_bootrom_initblock.S b/cpu/bf533/init_sdram_bootrom_initblock.S index 99ed920..8694ca2 100644 --- a/cpu/bf533/init_sdram_bootrom_initblock.S +++ b/cpu/bf533/init_sdram_bootrom_initblock.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (CONFIG_CCLK_DIV == 1) diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S index c356d53..7556ec9 100644 --- a/cpu/bf533/interrupt.S +++ b/cpu/bf533/interrupt.S @@ -42,9 +42,7 @@ #define ASSEMBLY #include <config.h> #include <asm/blackfin.h> -#include <asm/hw_irq.h> #include <asm/entry.h> -#include <asm/blackfin_defs.h> .global _blackfin_irq_panic; @@ -55,7 +53,7 @@ .global _evt_emulation _evt_emulation: SAVE_CONTEXT - r0 = IRQ_EMU; + r0 = 0; r1 = seqstat; sp += -12; call _blackfin_irq_panic; @@ -66,7 +64,7 @@ _evt_emulation: .global _evt_nmi _evt_nmi: SAVE_CONTEXT - r0 = IRQ_NMI; + r0 = 2; r1 = RETN; sp += -12; call _blackfin_irq_panic; @@ -88,7 +86,7 @@ _trap: .global _evt_rst _evt_rst: SAVE_CONTEXT - r0 = IRQ_RST; + r0 = 1; r1 = RETN; sp += -12; call _do_reset; @@ -98,7 +96,7 @@ _evt_rst_exit: rtn; irq_panic: - r0 = IRQ_EVX; + r0 = 3; r1 = sp; sp += -12; call _blackfin_irq_panic; @@ -115,7 +113,7 @@ _evt_ivhw_exit: .global _evt_timer _evt_timer: SAVE_CONTEXT - r0 = IRQ_CORETMR; + r0 = 6; sp += -12; /* Polling method used now. */ /* call timer_int; */ diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c index 14d06cf..3d1c3bc 100644 --- a/cpu/bf533/interrupts.c +++ b/cpu/bf533/interrupts.c @@ -35,8 +35,6 @@ */ #include <common.h> -#include <asm/machdep.h> -#include <asm/irq.h> #include <config.h> #include <asm/blackfin.h> #include "cpu.h" @@ -72,12 +70,10 @@ ulong get_tbclk(void) void enable_interrupts(void) { - restore_flags(int_flag); } int disable_interrupts(void) { - save_and_cli(int_flag); return 1; } diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c index 5586689..05d9a1b 100644 --- a/cpu/bf533/ints.c +++ b/cpu/bf533/ints.c @@ -39,12 +39,9 @@ #include <common.h> #include <linux/stddef.h> #include <asm/system.h> -#include <asm/irq.h> #include <asm/traps.h> #include <asm/io.h> #include <asm/errno.h> -#include <asm/machdep.h> -#include <asm/setup.h> #include <asm/blackfin.h> #include "cpu.h" @@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs) void blackfin_init_IRQ(void) { - *(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL; - cli(); + *(unsigned volatile long *)(SIC_IMASK) = 0; #ifndef CONFIG_KGDB - *(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0; + *(unsigned volatile long *)(EVT1) = 0x0; #endif - *(unsigned volatile long *)(EVT_NMI_ADDR) = + *(unsigned volatile long *)(EVT2) = (unsigned volatile long)evt_nmi; - *(unsigned volatile long *)(EVT_EXCEPTION_ADDR) = + *(unsigned volatile long *)(EVT3) = (unsigned volatile long)trap; - *(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) = + *(unsigned volatile long *)(EVT5) = (unsigned volatile long)evt_ivhw; - *(unsigned volatile long *)(EVT_RESET_ADDR) = + *(unsigned volatile long *)(EVT0) = (unsigned volatile long)evt_rst; - *(unsigned volatile long *)(EVT_TIMER_ADDR) = + *(unsigned volatile long *)(EVT6) = (unsigned volatile long)evt_timer; - *(unsigned volatile long *)(EVT_IVG7_ADDR) = + *(unsigned volatile long *)(EVT7) = (unsigned volatile long)evt_evt7; - *(unsigned volatile long *)(EVT_IVG8_ADDR) = + *(unsigned volatile long *)(EVT8) = (unsigned volatile long)evt_evt8; - *(unsigned volatile long *)(EVT_IVG9_ADDR) = + *(unsigned volatile long *)(EVT9) = (unsigned volatile long)evt_evt9; - *(unsigned volatile long *)(EVT_IVG10_ADDR) = + *(unsigned volatile long *)(EVT10) = (unsigned volatile long)evt_evt10; - *(unsigned volatile long *)(EVT_IVG11_ADDR) = + *(unsigned volatile long *)(EVT11) = (unsigned volatile long)evt_evt11; - *(unsigned volatile long *)(EVT_IVG12_ADDR) = + *(unsigned volatile long *)(EVT12) = (unsigned volatile long)evt_evt12; - *(unsigned volatile long *)(EVT_IVG13_ADDR) = + *(unsigned volatile long *)(EVT13) = (unsigned volatile long)evt_evt13; - *(unsigned volatile long *)(EVT_IVG14_ADDR) = + *(unsigned volatile long *)(EVT14) = (unsigned volatile long)evt_system_call; - *(unsigned volatile long *)(EVT_IVG15_ADDR) = + *(unsigned volatile long *)(EVT15) = (unsigned volatile long)evt_soft_int1; *(volatile unsigned long *)ILAT = 0; asm("csync;"); - sti(); *(volatile unsigned long *)IMASK = 0xffbf; asm("csync;"); } diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c index 8ac6e3f..05fcfcc 100644 --- a/cpu/bf533/serial.c +++ b/cpu/bf533/serial.c @@ -43,14 +43,12 @@ */ #include <common.h> -#include <asm/irq.h> #include <asm/system.h> -#include <asm/segment.h> #include <asm/bitops.h> #include <asm/delay.h> -#include <asm/uaccess.h> #include <asm/io.h> #include "bf533_serial.h" +#include <asm/mach-common/bits/uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -85,30 +83,30 @@ void serial_setbrg(void) } /* Enable UART */ - *pUART_GCTL |= UART_GCTL_UCEN; - sync(); + *pUART_GCTL |= UCEN; + SSYNC(); /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH; - sync(); + SSYNC(); *pUART_DLL = hw_baud_table[i].dl_low; - sync(); + SSYNC(); *pUART_DLH = hw_baud_table[i].dl_high; - sync(); + SSYNC(); /* Clear DLAB in LCR to Access THR RBR IER */ ACCESS_PORT_IER; - sync(); + SSYNC(); /* Enable ERBFI and ELSI interrupts * to poll SIC_ISR register*/ - *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI; - sync(); + *pUART_IER = ELSI | ERBFI | ETBEI; + SSYNC(); /* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = UART_LCR_WLS8; - sync(); + *pUART_LCR = WLS_8; + SSYNC(); return; } @@ -121,14 +119,14 @@ int serial_init(void) void serial_putc(const char c) { - if ((*pUART_LSR) & UART_LSR_TEMT) { + if ((*pUART_LSR) & TEMT) { if (c == '\n') serial_putc('\r'); local_put_char(c); } - while (!((*pUART_LSR) & UART_LSR_TEMT)) + while (!((*pUART_LSR) & TEMT)) SYNC_ALL; return; @@ -136,7 +134,7 @@ void serial_putc(const char c) int serial_tstc(void) { - if (*pUART_LSR & UART_LSR_DR) + if (*pUART_LSR & DR) return 1; else return 0; @@ -149,14 +147,14 @@ int serial_getc(void) int ret; /* Poll for RX Interrupt */ - while (!((isr_val = - *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ; + while (!serial_tstc()) + continue; asm("csync;"); uart_lsr_val = *pUART_LSR; /* Clear status bit */ uart_rbr_val = *pUART_RBR; /* getc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { + if (uart_lsr_val & (OE|PE|FE|BI)) { ret = -1; } else { ret = uart_rbr_val & 0xff; @@ -177,19 +175,12 @@ static void local_put_char(char ch) int flags = 0; unsigned long isr_val; - save_and_cli(flags); - /* Poll for TX Interruput */ - while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ; + while (!(*pUART_LSR & THRE)) + continue; asm("csync;"); *pUART_THR = ch; /* putc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { - printf("?"); - } - - restore_flags(flags); - return; } diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S index 67a60cf..c32fef6 100644 --- a/cpu/bf533/start.S +++ b/cpu/bf533/start.S @@ -41,19 +41,16 @@ #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/dma.h> +#include <asm/mach-common/bits/pll.h> + .global _stext; .global __bss_start; .global start; .global _start; -.global _rambase; -.global _ramstart; -.global _ramend; -.global _bf533_data_dest; -.global _bf533_data_size; .global edata; -.global _initialize; .global _exit; -.global flashdataend; .global init_sdram; #if (CONFIG_CCLK_DIV == 1) @@ -143,8 +140,8 @@ no_soft_reset: nop; /* Clear EVT registers */ - p0.h = (EVT_EMULATION_ADDR >> 16); - p0.l = (EVT_EMULATION_ADDR & 0xFFFF); + p0.h = (EVT0 >> 16); + p0.l = (EVT0 & 0xFFFF); p0 += 8; p1 = 14; r1 = 0; @@ -200,8 +197,8 @@ loop1: */ /* To keep ourselves in the supervisor mode */ - p0.l = (EVT_IVG15_ADDR & 0xFFFF); - p0.h = (EVT_IVG15_ADDR >> 16); + p0.l = (EVT15 & 0xFFFF); + p0.h = (EVT15 >> 16); p1.l = _real_start; p1.h = _real_start; @@ -209,8 +206,8 @@ loop1: p0.l = (IMASK & 0xFFFF); p0.h = (IMASK >> 16); - r0.l = LO(IVG15_POS); - r0.h = HI(IVG15_POS); + r0.l = LO(EVT_IVG15); + r0.h = HI(EVT_IVG15); [p0] = r0; raise 15; p0.l = WAIT_HERE; @@ -236,8 +233,8 @@ copy: R1.H = reset_end; R1.L = reset_end; R2 = R1 - R0; /* Count */ - R1.H = hi(L1_ISRAM); /* Destination Address (high) */ - R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ + R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ /* Destination DMAConfig Value (8-bit words) */ R4.L = (DI_EN | WNR | DMAEN); diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c index 19b1fde..7e156d5 100644 --- a/cpu/bf533/traps.c +++ b/cpu/bf533/traps.c @@ -36,14 +36,13 @@ #include <common.h> #include <linux/types.h> #include <asm/errno.h> -#include <asm/irq.h> #include <asm/system.h> #include <asm/traps.h> -#include <asm/machdep.h> #include "cpu.h" -#include <asm/arch/anomaly.h> #include <asm/cplb.h> #include <asm/io.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/mpu.h> void init_IRQ(void) { @@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] = void trap_c(struct pt_regs *regs) { unsigned int addr; - unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE; + unsigned long trapnr = (regs->seqstat) & EXCAUSE; unsigned int i, j, size, *I0, *I1; unsigned short data = 0; @@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs) /* 0x26 - Data CPLB Miss */ case VEC_CPLB_M: -#ifdef ANOMALY_05000261 +#if ANOMALY_05000261 /* * Work around an anomaly: if we see a new DCPLB fault, * return without doing anything. Then, @@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache off */ if (data) { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); + SSYNC(); } if (data) { @@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache back on */ if (data) { j = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); + SSYNC(); } break; diff --git a/cpu/bf537/Makefile b/cpu/bf537/Makefile index 8b0f9c0..06d1aae 100644 --- a/cpu/bf537/Makefile +++ b/cpu/bf537/Makefile @@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o +SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o i2c.o EXTRA = init_sdram_bootrom_initblock.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/bf537/cache.S b/cpu/bf537/cache.S index 5bda5bf..d9015c6 100644 --- a/cpu/bf537/cache.S +++ b/cpu/bf537/cache.S @@ -2,6 +2,7 @@ #include <asm/linkage.h> #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/mpu.h> .text .align 2 diff --git a/cpu/bf537/config.mk b/cpu/bf537/config.mk index 8a35789..fbbe75d 100644 --- a/cpu/bf537/config.mk +++ b/cpu/bf537/config.mk @@ -24,4 +24,4 @@ # MA 02110-1301 USA # -PLATFORM_RELFLAGS += -mcpu=bf537 -ffixed-P5 +PLATFORM_RELFLAGS += -mcpu=bf537 diff --git a/cpu/bf537/cpu.c b/cpu/bf537/cpu.c index 62f603b..7233908 100644 --- a/cpu/bf537/cpu.c +++ b/cpu/bf537/cpu.c @@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2]; int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM) + __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) ); return 0; @@ -103,24 +103,20 @@ void icache_enable(void) } - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); - sti(); + SSYNC(); } void icache_disable(void) { if ((*pCHIPID >> 28) < 2) return; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); - sti(); + SSYNC(); } int icache_status(void) @@ -180,14 +176,12 @@ void dcache_enable(void) } } - cli(); temp = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - sync(); - sti(); + SSYNC(); } void dcache_disable(void) @@ -195,13 +189,11 @@ void dcache_disable(void) unsigned int *I0, *I1; int i; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); - sti(); + SSYNC(); /* after disable dcache, * clear it so we don't confuse the next application diff --git a/cpu/bf537/i2c.c b/cpu/bf537/i2c.c index 0daba63..ab7dd38 100644 --- a/cpu/bf537/i2c.c +++ b/cpu/bf537/i2c.c @@ -21,53 +21,10 @@ #include <asm/blackfin.h> #include <i2c.h> #include <asm/io.h> +#include <asm/mach-common/bits/twi.h> DECLARE_GLOBAL_DATA_PTR; -#define bfin_read16(addr) ({ unsigned __v; \ - __asm__ __volatile__ (\ - "%0 = w[%1] (z);\n\t"\ - : "=d"(__v) : "a"(addr)); (unsigned short)__v; }) - -#define bfin_write16(addr,val) ({\ - __asm__ __volatile__ (\ - "w[%0] = %1;\n\t"\ - : : "a"(addr) , "d"(val) : "memory");}) - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val) -#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val) - #ifdef DEBUG_I2C #define PRINTD(fmt,args...) do { \ if (gd->have_console) \ diff --git a/cpu/bf537/init_sdram.S b/cpu/bf537/init_sdram.S index 897a589..e997500 100644 --- a/cpu/bf537/init_sdram.S +++ b/cpu/bf537/init_sdram.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (BFIN_BOOT_MODE != BF537_UART_BOOT) diff --git a/cpu/bf537/init_sdram_bootrom_initblock.S b/cpu/bf537/init_sdram_bootrom_initblock.S index f9adbb9..197b836 100644 --- a/cpu/bf537/init_sdram_bootrom_initblock.S +++ b/cpu/bf537/init_sdram_bootrom_initblock.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (BFIN_BOOT_MODE != BF537_UART_BOOT) diff --git a/cpu/bf537/interrupt.S b/cpu/bf537/interrupt.S index a71df55..fe850bf 100644 --- a/cpu/bf537/interrupt.S +++ b/cpu/bf537/interrupt.S @@ -42,9 +42,7 @@ #define ASSEMBLY #include <config.h> #include <asm/blackfin.h> -#include <asm/hw_irq.h> #include <asm/entry.h> -#include <asm/blackfin_defs.h> .global _blackfin_irq_panic; @@ -55,7 +53,7 @@ .global _evt_emulation _evt_emulation: SAVE_CONTEXT - r0 = IRQ_EMU; + r0 = 0; r1 = seqstat; sp += -12; call _blackfin_irq_panic; @@ -66,7 +64,7 @@ _evt_emulation: .global _evt_nmi _evt_nmi: SAVE_CONTEXT - r0 = IRQ_NMI; + r0 = 2; r1 = RETN; sp += -12; call _blackfin_irq_panic; @@ -88,7 +86,7 @@ _trap: .global _evt_rst _evt_rst: SAVE_CONTEXT - r0 = IRQ_RST; + r0 = 1; r1 = RETN; sp += -12; call _do_reset; @@ -98,7 +96,7 @@ _evt_rst_exit: rtn; irq_panic: - r0 = IRQ_EVX; + r0 = 3; r1 = sp; sp += -12; call _blackfin_irq_panic; @@ -115,7 +113,7 @@ _evt_ivhw_exit: .global _evt_timer _evt_timer: SAVE_CONTEXT - r0 = IRQ_CORETMR; + r0 = 6; sp += -12; /* Polling method used now. */ /* call timer_int; */ diff --git a/cpu/bf537/interrupts.c b/cpu/bf537/interrupts.c index d2213b1..853fa49 100644 --- a/cpu/bf537/interrupts.c +++ b/cpu/bf537/interrupts.c @@ -35,8 +35,6 @@ */ #include <common.h> -#include <asm/machdep.h> -#include <asm/irq.h> #include <config.h> #include <asm/blackfin.h> #include "cpu.h" @@ -72,12 +70,10 @@ ulong get_tbclk (void) void enable_interrupts(void) { - restore_flags(int_flag); } int disable_interrupts(void) { - save_and_cli(int_flag); return 1; } diff --git a/cpu/bf537/ints.c b/cpu/bf537/ints.c index 5586689..05d9a1b 100644 --- a/cpu/bf537/ints.c +++ b/cpu/bf537/ints.c @@ -39,12 +39,9 @@ #include <common.h> #include <linux/stddef.h> #include <asm/system.h> -#include <asm/irq.h> #include <asm/traps.h> #include <asm/io.h> #include <asm/errno.h> -#include <asm/machdep.h> -#include <asm/setup.h> #include <asm/blackfin.h> #include "cpu.h" @@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs) void blackfin_init_IRQ(void) { - *(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL; - cli(); + *(unsigned volatile long *)(SIC_IMASK) = 0; #ifndef CONFIG_KGDB - *(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0; + *(unsigned volatile long *)(EVT1) = 0x0; #endif - *(unsigned volatile long *)(EVT_NMI_ADDR) = + *(unsigned volatile long *)(EVT2) = (unsigned volatile long)evt_nmi; - *(unsigned volatile long *)(EVT_EXCEPTION_ADDR) = + *(unsigned volatile long *)(EVT3) = (unsigned volatile long)trap; - *(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) = + *(unsigned volatile long *)(EVT5) = (unsigned volatile long)evt_ivhw; - *(unsigned volatile long *)(EVT_RESET_ADDR) = + *(unsigned volatile long *)(EVT0) = (unsigned volatile long)evt_rst; - *(unsigned volatile long *)(EVT_TIMER_ADDR) = + *(unsigned volatile long *)(EVT6) = (unsigned volatile long)evt_timer; - *(unsigned volatile long *)(EVT_IVG7_ADDR) = + *(unsigned volatile long *)(EVT7) = (unsigned volatile long)evt_evt7; - *(unsigned volatile long *)(EVT_IVG8_ADDR) = + *(unsigned volatile long *)(EVT8) = (unsigned volatile long)evt_evt8; - *(unsigned volatile long *)(EVT_IVG9_ADDR) = + *(unsigned volatile long *)(EVT9) = (unsigned volatile long)evt_evt9; - *(unsigned volatile long *)(EVT_IVG10_ADDR) = + *(unsigned volatile long *)(EVT10) = (unsigned volatile long)evt_evt10; - *(unsigned volatile long *)(EVT_IVG11_ADDR) = + *(unsigned volatile long *)(EVT11) = (unsigned volatile long)evt_evt11; - *(unsigned volatile long *)(EVT_IVG12_ADDR) = + *(unsigned volatile long *)(EVT12) = (unsigned volatile long)evt_evt12; - *(unsigned volatile long *)(EVT_IVG13_ADDR) = + *(unsigned volatile long *)(EVT13) = (unsigned volatile long)evt_evt13; - *(unsigned volatile long *)(EVT_IVG14_ADDR) = + *(unsigned volatile long *)(EVT14) = (unsigned volatile long)evt_system_call; - *(unsigned volatile long *)(EVT_IVG15_ADDR) = + *(unsigned volatile long *)(EVT15) = (unsigned volatile long)evt_soft_int1; *(volatile unsigned long *)ILAT = 0; asm("csync;"); - sti(); *(volatile unsigned long *)IMASK = 0xffbf; asm("csync;"); } diff --git a/cpu/bf537/serial.c b/cpu/bf537/serial.c index f7a2483..3c6a370 100644 --- a/cpu/bf537/serial.c +++ b/cpu/bf537/serial.c @@ -43,14 +43,12 @@ */ #include <common.h> -#include <asm/irq.h> #include <asm/system.h> -#include <asm/segment.h> #include <asm/bitops.h> #include <asm/delay.h> -#include <asm/uaccess.h> #include <asm/io.h> #include "serial.h" +#include <asm/mach-common/bits/uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -85,30 +83,30 @@ void serial_setbrg(void) } /* Enable UART */ - *pUART_GCTL |= UART_GCTL_UCEN; - sync(); + *pUART0_GCTL |= UCEN; + SSYNC(); /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH; - sync(); + SSYNC(); - *pUART_DLL = hw_baud_table[i].dl_low; - sync(); - *pUART_DLH = hw_baud_table[i].dl_high; - sync(); + *pUART0_DLL = hw_baud_table[i].dl_low; + SSYNC(); + *pUART0_DLH = hw_baud_table[i].dl_high; + SSYNC(); /* Clear DLAB in LCR to Access THR RBR IER */ ACCESS_PORT_IER; - sync(); + SSYNC(); /* Enable ERBFI and ELSI interrupts * to poll SIC_ISR register*/ - *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI; - sync(); + *pUART0_IER = ELSI | ERBFI | ETBEI; + SSYNC(); /* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = UART_LCR_WLS8; - sync(); + *pUART0_LCR = WLS_8; + SSYNC(); return; } @@ -121,14 +119,14 @@ int serial_init(void) void serial_putc(const char c) { - if ((*pUART_LSR) & UART_LSR_TEMT) { + if ((*pUART0_LSR) & TEMT) { if (c == '\n') serial_putc('\r'); local_put_char(c); } - while (!((*pUART_LSR) & UART_LSR_TEMT)) + while (!((*pUART0_LSR) & TEMT)) SYNC_ALL; return; @@ -136,7 +134,7 @@ void serial_putc(const char c) int serial_tstc(void) { - if (*pUART_LSR & UART_LSR_DR) + if (*pUART0_LSR & DR) return 1; else return 0; @@ -149,14 +147,14 @@ int serial_getc(void) int ret; /* Poll for RX Interrupt */ - while (!((isr_val = - *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ; + while (!serial_tstc()) + continue; asm("csync;"); - uart_lsr_val = *pUART_LSR; /* Clear status bit */ - uart_rbr_val = *pUART_RBR; /* getc() */ + uart_lsr_val = *pUART0_LSR; /* Clear status bit */ + uart_rbr_val = *pUART0_RBR; /* getc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { + if (uart_lsr_val & (OE|PE|FE|BI)) { ret = -1; } else { ret = uart_rbr_val & 0xff; @@ -177,19 +175,12 @@ static void local_put_char(char ch) int flags = 0; unsigned long isr_val; - save_and_cli(flags); - /* Poll for TX Interruput */ - while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ; + while (!(*pUART0_LSR & THRE)) + continue; asm("csync;"); - *pUART_THR = ch; /* putc() */ - - if (isr_val & IRQ_UART_ERROR_BIT) { - printf("?"); - } - - restore_flags(flags); + *pUART0_THR = ch; /* putc() */ return; } diff --git a/cpu/bf537/serial.h b/cpu/bf537/serial.h index 76555c2..e4e0b9a 100644 --- a/cpu/bf537/serial.h +++ b/cpu/bf537/serial.h @@ -49,8 +49,8 @@ #include <asm/blackfin.h> #define SYNC_ALL __asm__ __volatile__ ("ssync;\n") -#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB; -#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB); +#define ACCESS_LATCH *pUART0_LCR |= DLAB; +#define ACCESS_PORT_IER *pUART0_LCR &= (~DLAB); void serial_setbrg(void); static void local_put_char(char ch); diff --git a/cpu/bf537/start.S b/cpu/bf537/start.S index 4e02bcb..a48f3c6 100644 --- a/cpu/bf537/start.S +++ b/cpu/bf537/start.S @@ -41,19 +41,16 @@ #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/dma.h> +#include <asm/mach-common/bits/pll.h> + .global _stext; .global __bss_start; .global start; .global _start; -.global _rambase; -.global _ramstart; -.global _ramend; -.global _bf533_data_dest; -.global _bf533_data_size; .global edata; -.global _initialize; .global _exit; -.global flashdataend; .global init_sdram; .global _icache_enable; .global _dcache_enable; @@ -151,8 +148,8 @@ no_soft_reset: nop; /* Clear EVT registers */ - p0.h = (EVT_EMULATION_ADDR >> 16); - p0.l = (EVT_EMULATION_ADDR & 0xFFFF); + p0.h = (EVT0 >> 16); + p0.l = (EVT0 & 0xFFFF); p0 += 8; p1 = 14; r1 = 0; @@ -291,8 +288,8 @@ postcopy: R1.H = (CFG_FLASH_BASE >> 16); R1.L = (CFG_FLASH_BASE & 0xFFFF); R0 = R0 + R1; /* Source Address */ - R1.H = hi(L1_ISRAM); /* Destination Address (high) */ - R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ + R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ /* Destination DMAConfig Value (8-bit words) */ R4.L = (DI_EN | WNR | DMAEN); @@ -415,8 +412,8 @@ loop1: */ /* To keep ourselves in the supervisor mode */ - p0.l = (EVT_IVG15_ADDR & 0xFFFF); - p0.h = (EVT_IVG15_ADDR >> 16); + p0.l = (EVT15 & 0xFFFF); + p0.h = (EVT15 >> 16); p1.l = _real_start; p1.h = _real_start; @@ -424,8 +421,8 @@ loop1: p0.l = (IMASK & 0xFFFF); p0.h = (IMASK >> 16); - r0.l = LO(IVG15_POS); - r0.h = HI(IVG15_POS); + r0.l = LO(EVT_IVG15); + r0.h = HI(EVT_IVG15); [p0] = r0; raise 15; p0.l = WAIT_HERE; @@ -495,8 +492,8 @@ copy: R1.H = reset_end; R1.L = reset_end; R2 = R1 - R0; /* Count */ - R1.H = hi(L1_ISRAM); /* Destination Address (high) */ - R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ + R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ diff --git a/cpu/bf537/traps.c b/cpu/bf537/traps.c index 4e18e27..51de322 100644 --- a/cpu/bf537/traps.c +++ b/cpu/bf537/traps.c @@ -36,14 +36,13 @@ #include <common.h> #include <linux/types.h> #include <asm/errno.h> -#include <asm/irq.h> #include <asm/system.h> #include <asm/traps.h> -#include <asm/machdep.h> #include "cpu.h" -#include <asm/arch/anomaly.h> #include <asm/cplb.h> #include <asm/io.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/mpu.h> void init_IRQ(void) { @@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] = void trap_c(struct pt_regs *regs) { unsigned int addr; - unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE; + unsigned long trapnr = (regs->seqstat) & EXCAUSE; unsigned int i, j, size, *I0, *I1; unsigned short data = 0; @@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs) /* 0x26 - Data CPLB Miss */ case VEC_CPLB_M: -#ifdef ANOMALY_05000261 +#if ANOMALY_05000261 /* * Work around an anomaly: if we see a new DCPLB fault, * return without doing anything. Then, @@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache off */ if (data) { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); + SSYNC(); } if (data) { @@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache back on */ if (data) { j = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); + SSYNC(); } break; diff --git a/cpu/bf561/Makefile b/cpu/bf561/Makefile index 2947169..418a437 100644 --- a/cpu/bf561/Makefile +++ b/cpu/bf561/Makefile @@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o +SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o EXTRA = init_sdram_bootrom_initblock.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/bf561/cache.S b/cpu/bf561/cache.S index 5bda5bf..d9015c6 100644 --- a/cpu/bf561/cache.S +++ b/cpu/bf561/cache.S @@ -2,6 +2,7 @@ #include <asm/linkage.h> #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/mpu.h> .text .align 2 diff --git a/cpu/bf561/config.mk b/cpu/bf561/config.mk index f4dc04b..3628a02 100644 --- a/cpu/bf561/config.mk +++ b/cpu/bf561/config.mk @@ -24,4 +24,4 @@ # MA 02110-1301 USA # -PLATFORM_RELFLAGS += -mcpu=bf561 -ffixed-P5 +PLATFORM_RELFLAGS += -mcpu=bf561 diff --git a/cpu/bf561/cpu.c b/cpu/bf561/cpu.c index 5b907cd..e0dd2f5 100644 --- a/cpu/bf561/cpu.c +++ b/cpu/bf561/cpu.c @@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2]; int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM) + __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) ); return 0; @@ -100,22 +100,18 @@ void icache_enable(void) } - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); - sti(); + SSYNC(); } void icache_disable(void) { - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); - sti(); + SSYNC(); } int icache_status(void) @@ -175,14 +171,12 @@ void dcache_enable(void) } } - cli(); temp = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - sync(); - sti(); + SSYNC(); } void dcache_disable(void) @@ -191,13 +185,11 @@ void dcache_disable(void) unsigned int *I0, *I1; int i; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); - sti(); + SSYNC(); /* after disable dcache, clear it so we don't confuse the next application */ I0 = (unsigned int *)DCPLB_ADDR0; diff --git a/cpu/bf561/init_sdram.S b/cpu/bf561/init_sdram.S index d763f27..f5ccf30 100644 --- a/cpu/bf561/init_sdram.S +++ b/cpu/bf561/init_sdram.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (CONFIG_CCLK_DIV == 1) diff --git a/cpu/bf561/init_sdram_bootrom_initblock.S b/cpu/bf561/init_sdram_bootrom_initblock.S index 5e3c88a..9cc5e78 100644 --- a/cpu/bf561/init_sdram_bootrom_initblock.S +++ b/cpu/bf561/init_sdram_bootrom_initblock.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (CONFIG_CCLK_DIV == 1) diff --git a/cpu/bf561/interrupt.S b/cpu/bf561/interrupt.S index 21839ce..a10eaab 100644 --- a/cpu/bf561/interrupt.S +++ b/cpu/bf561/interrupt.S @@ -42,9 +42,7 @@ #define ASSEMBLY #include <config.h> #include <asm/blackfin.h> -#include <asm/hw_irq.h> #include <asm/entry.h> -#include <asm/blackfin_defs.h> .global _blackfin_irq_panic; @@ -55,7 +53,7 @@ .global _evt_emulation _evt_emulation: SAVE_CONTEXT - r0 = IRQ_EMU; + r0 = 0; r1 = seqstat; sp += -12; call _blackfin_irq_panic; @@ -66,7 +64,7 @@ _evt_emulation: .global _evt_nmi _evt_nmi: SAVE_CONTEXT - r0 = IRQ_NMI; + r0 = 2; r1 = RETN; sp += -12; call _blackfin_irq_panic; @@ -88,7 +86,7 @@ _trap: .global _evt_rst _evt_rst: SAVE_CONTEXT - r0 = IRQ_RST; + r0 = 1; r1 = RETN; sp += -12; call _do_reset; @@ -98,7 +96,7 @@ _evt_rst_exit: rtn; irq_panic: - r0 = IRQ_EVX; + r0 = 3; r1 = sp; sp += -12; call _blackfin_irq_panic; @@ -115,7 +113,7 @@ _evt_ivhw_exit: .global _evt_timer _evt_timer: SAVE_CONTEXT - r0 = IRQ_CORETMR; + r0 = 6; sp += -12; /* Polling method used now. */ /* call timer_int; */ diff --git a/cpu/bf561/interrupts.c b/cpu/bf561/interrupts.c index ecbc6ad..7880061 100644 --- a/cpu/bf561/interrupts.c +++ b/cpu/bf561/interrupts.c @@ -35,8 +35,6 @@ */ #include <common.h> -#include <asm/machdep.h> -#include <asm/irq.h> #include <config.h> #include <asm/blackfin.h> #include "cpu.h" @@ -72,12 +70,10 @@ ulong get_tbclk(void) void enable_interrupts(void) { - restore_flags(int_flag); } int disable_interrupts(void) { - save_and_cli(int_flag); return 1; } diff --git a/cpu/bf561/ints.c b/cpu/bf561/ints.c index 27a38a3..d6aa393 100644 --- a/cpu/bf561/ints.c +++ b/cpu/bf561/ints.c @@ -39,12 +39,9 @@ #include <common.h> #include <linux/stddef.h> #include <asm/system.h> -#include <asm/irq.h> #include <asm/traps.h> #include <asm/io.h> #include <asm/errno.h> -#include <asm/machdep.h> -#include <asm/setup.h> #include <asm/blackfin.h> #include "cpu.h" @@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs) void blackfin_init_IRQ(void) { - *(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL; - cli(); + *(unsigned volatile long *)(SICA_IMASK0) = 0; #ifndef CONFIG_KGDB - *(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0; + *(unsigned volatile long *)(EVT1) = 0x0; #endif - *(unsigned volatile long *)(EVT_NMI_ADDR) = + *(unsigned volatile long *)(EVT2) = (unsigned volatile long)evt_nmi; - *(unsigned volatile long *)(EVT_EXCEPTION_ADDR) = + *(unsigned volatile long *)(EVT3) = (unsigned volatile long)trap; - *(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) = + *(unsigned volatile long *)(EVT5) = (unsigned volatile long)evt_ivhw; - *(unsigned volatile long *)(EVT_RESET_ADDR) = + *(unsigned volatile long *)(EVT0) = (unsigned volatile long)evt_rst; - *(unsigned volatile long *)(EVT_TIMER_ADDR) = + *(unsigned volatile long *)(EVT6) = (unsigned volatile long)evt_timer; - *(unsigned volatile long *)(EVT_IVG7_ADDR) = + *(unsigned volatile long *)(EVT7) = (unsigned volatile long)evt_evt7; - *(unsigned volatile long *)(EVT_IVG8_ADDR) = + *(unsigned volatile long *)(EVT8) = (unsigned volatile long)evt_evt8; - *(unsigned volatile long *)(EVT_IVG9_ADDR) = + *(unsigned volatile long *)(EVT9) = (unsigned volatile long)evt_evt9; - *(unsigned volatile long *)(EVT_IVG10_ADDR) = + *(unsigned volatile long *)(EVT10) = (unsigned volatile long)evt_evt10; - *(unsigned volatile long *)(EVT_IVG11_ADDR) = + *(unsigned volatile long *)(EVT11) = (unsigned volatile long)evt_evt11; - *(unsigned volatile long *)(EVT_IVG12_ADDR) = + *(unsigned volatile long *)(EVT12) = (unsigned volatile long)evt_evt12; - *(unsigned volatile long *)(EVT_IVG13_ADDR) = + *(unsigned volatile long *)(EVT13) = (unsigned volatile long)evt_evt13; - *(unsigned volatile long *)(EVT_IVG14_ADDR) = + *(unsigned volatile long *)(EVT14) = (unsigned volatile long)evt_system_call; - *(unsigned volatile long *)(EVT_IVG15_ADDR) = + *(unsigned volatile long *)(EVT15) = (unsigned volatile long)evt_soft_int1; *(volatile unsigned long *)ILAT = 0; asm("csync;"); - sti(); *(volatile unsigned long *)IMASK = 0xffbf; asm("csync;"); } diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c index bc5a4f5..a398fd5 100644 --- a/cpu/bf561/serial.c +++ b/cpu/bf561/serial.c @@ -43,14 +43,12 @@ */ #include <common.h> -#include <asm/irq.h> #include <asm/system.h> -#include <asm/segment.h> #include <asm/bitops.h> #include <asm/delay.h> -#include <asm/uaccess.h> #include "serial.h" #include <asm/io.h> +#include <asm/mach-common/bits/uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -85,32 +83,32 @@ void serial_setbrg(void) } /* Enable UART */ - *pUART_GCTL |= UART_GCTL_UCEN; - sync(); + *pUART_GCTL |= UCEN; + SSYNC(); /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH; - sync(); + SSYNC(); *pUART_DLL = hw_baud_table[i].dl_low; - sync(); + SSYNC(); *pUART_DLH = hw_baud_table[i].dl_high; - sync(); + SSYNC(); /* Clear DLAB in LCR to Access THR RBR IER */ ACCESS_PORT_IER; - sync(); + SSYNC(); /* * Enable ERBFI and ELSI interrupts * to poll SIC_ISR register */ - *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI; - sync(); + *pUART_IER = ELSI | ERBFI | ETBEI; + SSYNC(); /* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = UART_LCR_WLS8; - sync(); + *pUART_LCR = WLS_8; + SSYNC(); return; } @@ -123,14 +121,14 @@ int serial_init(void) void serial_putc(const char c) { - if ((*pUART_LSR) & UART_LSR_TEMT) { + if ((*pUART_LSR) & TEMT) { if (c == '\n') serial_putc('\r'); local_put_char(c); } - while (!((*pUART_LSR) & UART_LSR_TEMT)) + while (!((*pUART_LSR) & TEMT)) SYNC_ALL; return; @@ -138,7 +136,7 @@ void serial_putc(const char c) int serial_tstc(void) { - if (*pUART_LSR & UART_LSR_DR) + if (*pUART_LSR & DR) return 1; else return 0; @@ -151,14 +149,14 @@ int serial_getc(void) int ret; /* Poll for RX Interrupt */ - while (!((isr_val = - *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ; + while (!serial_tstc()) + continue; asm("csync;"); uart_lsr_val = *pUART_LSR; /* Clear status bit */ uart_rbr_val = *pUART_RBR; /* getc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { + if (uart_lsr_val & (OE|PE|FE|BI)) { ret = -1; } else { ret = uart_rbr_val & 0xff; @@ -179,19 +177,12 @@ static void local_put_char(char ch) int flags = 0; unsigned long isr_val; - save_and_cli(flags); - /* Poll for TX Interruput */ - while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ; + while (!(*pUART_LSR & THRE)) + continue; asm("csync;"); *pUART_THR = ch; /* putc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { - printf("?"); - } - - restore_flags(flags); - return; } diff --git a/cpu/bf561/serial.h b/cpu/bf561/serial.h index c1cbf36..647560c 100644 --- a/cpu/bf561/serial.h +++ b/cpu/bf561/serial.h @@ -49,8 +49,8 @@ #include <asm/blackfin.h> #define SYNC_ALL __asm__ __volatile__ ("ssync;\n") -#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB; -#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB); +#define ACCESS_LATCH *pUART_LCR |= DLAB; +#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB); void serial_setbrg(void); static void local_put_char(char ch); diff --git a/cpu/bf561/start.S b/cpu/bf561/start.S index bd26cf3..6565de8 100644 --- a/cpu/bf561/start.S +++ b/cpu/bf561/start.S @@ -41,17 +41,16 @@ #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/dma.h> +#include <asm/mach-common/bits/pll.h> + .global _stext; .global __bss_start; .global start; .global _start; -.global _rambase; -.global _ramstart; -.global _ramend; .global edata; -.global _initialize; .global _exit; -.global flashdataend; .global init_sdram; .text @@ -127,16 +126,16 @@ no_soft_reset: nop; /* Clear EVT registers */ - p0.h = (EVT_EMULATION_ADDR >> 16); - p0.l = (EVT_EMULATION_ADDR & 0xFFFF); + p0.h = (EVT0 >> 16); + p0.l = (EVT0 & 0xFFFF); p0 += 8; p1 = 14; r1 = 0; LSETUP(4,4) lc0 = p1; [ p0 ++ ] = r1; - p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); + p0.h = hi(SICA_IWR0); + p0.l = lo(SICA_IWR0); r0.l = 0x1; w[p0] = r0.l; SSYNC; @@ -193,8 +192,8 @@ loop1: */ /* To keep ourselves in the supervisor mode */ - p0.l = (EVT_IVG15_ADDR & 0xFFFF); - p0.h = (EVT_IVG15_ADDR >> 16); + p0.l = (EVT15 & 0xFFFF); + p0.h = (EVT15 >> 16); p1.l = _real_start; p1.h = _real_start; @@ -202,8 +201,8 @@ loop1: p0.l = (IMASK & 0xFFFF); p0.h = (IMASK >> 16); - r0.l = LO(IVG15_POS); - r0.h = HI(IVG15_POS); + r0.l = LO(EVT_IVG15); + r0.h = HI(EVT_IVG15); [p0] = r0; raise 15; p0.l = WAIT_HERE; @@ -218,13 +217,6 @@ WAIT_HERE: _real_start: [ -- sp ] = reti; -#ifdef CONFIG_EZKIT561 - p0.l = (WDOG_CTL & 0xFFFF); - p0.h = (WDOG_CTL >> 16); - r0 = WATCHDOG_DISABLE(z); - w[p0] = r0; -#endif - /* DMA reset code to Hi of L1 SRAM */ copy: P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */ @@ -235,37 +227,37 @@ copy: R1.H = reset_end; R1.L = reset_end; R2 = R1 - R0; /* Count */ - R1.H = hi(L1_ISRAM); /* Destination Address (high) */ - R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ + R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ DMA: R6 = 0x1 (Z); - W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ - W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ + W[P1+OFFSET_(IMDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ + W[P1+OFFSET_(IMDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ - [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ - W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ + [P1+OFFSET_(IMDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ + W[P1+OFFSET_(IMDMA_S0_X_COUNT)] = R2; /* Set Source Count */ /* Set Source DMAConfig = DMA Enable, Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ - W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; + W[P1+OFFSET_(IMDMA_S0_CONFIG)] = R3; - [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ - W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ + [P1+OFFSET_(IMDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ + W[P1+OFFSET_(IMDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ /* Set Destination DMAConfig = DMA Enable, Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ - W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; + W[P1+OFFSET_(IMDMA_D0_CONFIG)] = R4; WAIT_DMA_DONE: - p0.h = hi(MDMA_D0_IRQ_STATUS); - p0.l = lo(MDMA_D0_IRQ_STATUS); + p0.h = hi(IMDMA_D0_IRQ_STATUS); + p0.l = lo(IMDMA_D0_IRQ_STATUS); R0 = W[P0](Z); CC = BITTST(R0, 0); if ! CC jump WAIT_DMA_DONE R0 = 0x1; - W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ + W[P1+OFFSET_(IMDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ /* Initialize BSS Section with 0 s */ p1.l = __bss_start; diff --git a/cpu/bf561/traps.c b/cpu/bf561/traps.c index 7e2dcd1..e35620c 100644 --- a/cpu/bf561/traps.c +++ b/cpu/bf561/traps.c @@ -36,14 +36,13 @@ #include <common.h> #include <linux/types.h> #include <asm/errno.h> -#include <asm/irq.h> #include <asm/system.h> #include <asm/traps.h> -#include <asm/machdep.h> #include "cpu.h" -#include <asm/arch/anomaly.h> #include <asm/cplb.h> #include <asm/io.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/mpu.h> void init_IRQ(void) { @@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] = void trap_c(struct pt_regs *regs) { unsigned int addr; - unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE; + unsigned long trapnr = (regs->seqstat) & EXCAUSE; unsigned int i, j, size, *I0, *I1; unsigned short data = 0; @@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs) /* 0x26 - Data CPLB Miss */ case VEC_CPLB_M: -#ifdef ANOMALY_05000261 +#if ANOMALY_05000261 /* * Work around an anomaly: if we see a new DCPLB fault, return * without doing anything. Then, if we get the same fault again, @@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache off */ if (data) { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); + SSYNC(); } if (data) { @@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache back on */ if (data) { j = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); + SSYNC(); } break; diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk index 8a07c5a..5b7e1f2 100644 --- a/cpu/mpc512x/config.mk +++ b/cpu/mpc512x/config.mk @@ -22,4 +22,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ - -ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e + -ffixed-r2 -msoft-float -mcpu=603e diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 244c69b..5a9d868 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -479,52 +479,6 @@ get_pvr: mfspr r3, PVR blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*-------------------------------------------------------------------------- - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - *-------------------------------------------------------------------------- */ - - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - - .globl ppcDWstore -ppcDWstore: - lfd 1, 0(r4) - stfd 1, 0(r3) - blr - - .globl ppcDWload -ppcDWload: - lfd 1, 0(r3) - stfd 1, 0(r4) - blr - /*-------------------------------------------------------------------*/ /* diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk index 64cd600..6d66c32 100644 --- a/cpu/mpc5xx/config.mk +++ b/cpu/mpc5xx/config.mk @@ -30,7 +30,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float +PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float # Use default linker script. Board port can override in board/*/config.mk LDSCRIPT := $(SRCTREE)/cpu/mpc5xx/u-boot.lds diff --git a/cpu/mpc5xxx/config.mk b/cpu/mpc5xxx/config.mk index 0df51ba..b0ce2ee 100644 --- a/cpu/mpc5xxx/config.mk +++ b/cpu/mpc5xxx/config.mk @@ -23,7 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 -ffixed-r29 \ +PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \ -mstring -mcpu=603e -mmultiple # Use default linker script. Board port can override in board/*/config.mk diff --git a/cpu/mpc8220/config.mk b/cpu/mpc8220/config.mk index 8e3ba54..5819048 100644 --- a/cpu/mpc8220/config.mk +++ b/cpu/mpc8220/config.mk @@ -23,7 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 -ffixed-r29 \ +PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \ -mstring -mcpu=603e -mmultiple # Use default linker script. Board port can override in board/*/config.mk diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk index 66207f4..1bb0487 100644 --- a/cpu/mpc824x/config.mk +++ b/cpu/mpc824x/config.mk @@ -23,7 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float +PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float # Use default linker script. Board port can override in board/*/config.mk LDSCRIPT := $(SRCTREE)/cpu/mpc824x/u-boot.lds diff --git a/cpu/mpc8260/config.mk b/cpu/mpc8260/config.mk index 683b6fb..2cb0270 100644 --- a/cpu/mpc8260/config.mk +++ b/cpu/mpc8260/config.mk @@ -23,7 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \ +PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \ -mstring -mcpu=603e -mmultiple # Use default linker script. Board port can override in board/*/config.mk diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk index ecf8a60..2f0f1ce 100644 --- a/cpu/mpc83xx/config.mk +++ b/cpu/mpc83xx/config.mk @@ -23,7 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \ - -ffixed-r2 -ffixed-r29 -msoft-float + -ffixed-r2 -msoft-float # Use default linker script. Board port can override in board/*/config.mk LDSCRIPT := $(SRCTREE)/cpu/mpc83xx/u-boot.lds diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 1dfbf62..309eb30 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -840,40 +840,6 @@ get_pvr: mfspr r3, PVR blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*-------------------------------------------------------------------------- - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - *-------------------------------------------------------------------------- */ - - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - .globl ppcDWstore ppcDWstore: lfd 1, 0(r4) diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk index 6121074..f6df702 100644 --- a/cpu/mpc85xx/config.mk +++ b/cpu/mpc85xx/config.mk @@ -23,4 +23,5 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 -ffixed-r29 -Wa,-me500 -msoft-float -mno-string +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 \ + -Wa,-me500 -msoft-float -mno-string diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 27de37a..952f30c 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -75,6 +75,9 @@ int get_clocks (void) get_sys_info (&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; + gd->i2c1_clk = sys_info.freqSystemBus; + gd->i2c2_clk = sys_info.freqSystemBus; + #if defined(CONFIG_CPM2) gd->vco_out = 2*sys_info.freqSystemBus; gd->cpm_clk = gd->vco_out / 2; diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index e8e5eb2..eb24dbc 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -757,51 +757,6 @@ in32r: lwbrx r3,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*-------------------------------------------------------------------------- - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - *-------------------------------------------------------------------------- */ - - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcSync */ -/* Description: Processor Synchronize */ -/* Input: none. */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcSync -ppcSync: - sync - blr - /*------------------------------------------------------------------------------*/ /* diff --git a/cpu/mpc86xx/config.mk b/cpu/mpc86xx/config.mk index 3c54f4a..d767269 100644 --- a/cpu/mpc86xx/config.mk +++ b/cpu/mpc86xx/config.mk @@ -23,4 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -mstring diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 11354d3..e1b3c52 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -27,6 +27,7 @@ #include <command.h> #include <asm/cache.h> #include <mpc86xx.h> +#include <asm/fsl_law.h> #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> @@ -324,6 +325,27 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) memcpy(p, bd->bi_enet3addr, 6); #endif +#endif /* CONFIG_OF_FLAT_TREE */ + +/* + * Print out the state of various machine registers. + * Currently prints out LAWs and BR0/OR0 + */ +void mpc86xx_reginfo(void) +{ + immap_t *immap = (immap_t *)CFG_IMMR; + ccsr_lbc_t *lbc = &immap->im_lbc; + + print_laws(); + + printf ("Local Bus Controller Registers\n" + "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0)); + printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1)); + printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2)); + printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3)); + printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4)); + printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5)); + printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6)); + printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7)); } -#endif diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 4f8956e..ab5906d 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -49,6 +49,10 @@ void cpu_init_f(void) /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); +#ifdef CONFIG_FSL_LAW + init_laws(); +#endif + /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary * addresses - these have to be modified later when FLASH size * has been determined @@ -114,5 +118,8 @@ void cpu_init_f(void) */ int cpu_init_r(void) { +#ifdef CONFIG_FSL_LAW + disable_law(0); +#endif return 0; } diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 54e40f1..e501caf 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -27,7 +27,7 @@ #include <i2c.h> #include <spd.h> #include <asm/mmu.h> - +#include <asm/fsl_law.h> #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void dma_init(void); @@ -1123,7 +1123,6 @@ spd_sdram(void) int memsize_ddr1 = 0; unsigned int law_size_ddr1; volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; #ifdef CONFIG_DDR_INTERLEAVE volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; #endif @@ -1179,12 +1178,9 @@ spd_sdram(void) /* * Set up LAWBAR for DDR 1 space. */ - mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); - mcm->lawar1 = (LAWAR_EN - | LAWAR_TRGT_IF_DDR_INTERLEAVED - | (LAWAR_SIZE & law_size_interleaved)); - debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); - debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); +#ifdef CONFIG_FSL_LAW + set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV); +#endif debug("Interleaved memory size is 0x%08lx\n", memsize_total); #ifdef CONFIG_DDR_INTERLEAVE @@ -1239,12 +1235,9 @@ spd_sdram(void) /* * Set up LAWBAR for DDR 1 space. */ - mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); - mcm->lawar1 = (LAWAR_EN - | LAWAR_TRGT_IF_DDR1 - | (LAWAR_SIZE & law_size_ddr1)); - debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); - debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); +#ifdef CONFIG_FSL_LAW + set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1); +#endif } #if (CONFIG_NUM_DDR_CONTROLLERS > 1) @@ -1269,17 +1262,11 @@ spd_sdram(void) /* * Set up LAWBAR for DDR 2 space. */ - if (ddr1_enabled) - mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12) - & 0xfffff); - else - mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); - - mcm->lawar8 = (LAWAR_EN - | LAWAR_TRGT_IF_DDR2 - | (LAWAR_SIZE & law_size_ddr2)); - debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8); - debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8); +#ifdef CONFIG_FSL_LAW + set_law(8, + (ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE), + law_size_ddr2, LAW_TRGT_IF_DDR_2); +#endif } debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2); diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 4f7e8f1..7e884f8 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -105,6 +105,8 @@ int get_clocks(void) get_sys_info(&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; + gd->i2c1_clk = sys_info.freqSystemBus; + gd->i2c2_clk = sys_info.freqSystemBus; if (gd->cpu_clk != 0) return 0; diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index c83310a..c71c926 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -235,17 +235,8 @@ in_flash: bl enable_ext_addr /* setup the bats */ - bl setup_bats - sync - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* setup ccsrbar */ - bl setup_ccsrbar -#endif + bl early_bats - /* setup the law entries */ - bl law_entry - sync /* * Cache must be enabled here for stack-in-cache trick. * This means we need to enable the BATS. @@ -282,6 +273,16 @@ in_flash: GET_GOT /* initialize GOT access */ + /* setup the rest of the bats */ + bl setup_bats + bl clear_tlbs + sync + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* setup ccsrbar */ + bl setup_ccsrbar +#endif + /* run low-level CPU init code (from Flash) */ bl cpu_init_f sync @@ -359,6 +360,7 @@ invalidate_bats: /* setup_bats - set them up to some initial state */ + /* Skip any BATS setup in early_bats */ .globl setup_bats setup_bats: @@ -454,42 +456,6 @@ setup_bats: mtspr DBAT4U, r3 isync - /* IBAT 5 */ - addis r4, r0, CFG_IBAT5L@h - ori r4, r4, CFG_IBAT5L@l - addis r3, r0, CFG_IBAT5U@h - ori r3, r3, CFG_IBAT5U@l - mtspr IBAT5L, r4 - mtspr IBAT5U, r3 - isync - - /* DBAT 5 */ - addis r4, r0, CFG_DBAT5L@h - ori r4, r4, CFG_DBAT5L@l - addis r3, r0, CFG_DBAT5U@h - ori r3, r3, CFG_DBAT5U@l - mtspr DBAT5L, r4 - mtspr DBAT5U, r3 - isync - - /* IBAT 6 */ - addis r4, r0, CFG_IBAT6L@h - ori r4, r4, CFG_IBAT6L@l - addis r3, r0, CFG_IBAT6U@h - ori r3, r3, CFG_IBAT6U@l - mtspr IBAT6L, r4 - mtspr IBAT6U, r3 - isync - - /* DBAT 6 */ - addis r4, r0, CFG_DBAT6L@h - ori r4, r4, CFG_DBAT6L@l - addis r3, r0, CFG_DBAT6U@h - ori r3, r3, CFG_DBAT6U@l - mtspr DBAT6L, r4 - mtspr DBAT6U, r3 - isync - /* IBAT 7 */ addis r4, r0, CFG_IBAT7L@h ori r4, r4, CFG_IBAT7L@l @@ -508,18 +474,65 @@ setup_bats: mtspr DBAT7U, r3 isync -1: - addis r3, 0, 0x0000 - addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */ + sync + blr + +/* + * early_bats: + * + * Set up bats needed early on - this is usually the BAT for the + * stack-in-cache and the Flash + */ + .globl early_bats +early_bats: + /* IBAT 5 */ + lis r4, CFG_IBAT5L@h + ori r4, r4, CFG_IBAT5L@l + lis r3, CFG_IBAT5U@h + ori r3, r3, CFG_IBAT5U@l + mtspr IBAT5L, r4 + mtspr IBAT5U, r3 + isync + + /* DBAT 5 */ + lis r4, CFG_DBAT5L@h + ori r4, r4, CFG_DBAT5L@l + lis r3, CFG_DBAT5U@h + ori r3, r3, CFG_DBAT5U@l + mtspr DBAT5L, r4 + mtspr DBAT5U, r3 isync + /* IBAT 6 */ + lis r4, CFG_IBAT6L@h + ori r4, r4, CFG_IBAT6L@l + lis r3, CFG_IBAT6U@h + ori r3, r3, CFG_IBAT6U@l + mtspr IBAT6L, r4 + mtspr IBAT6U, r3 + isync + + /* DBAT 6 */ + lis r4, CFG_DBAT6L@h + ori r4, r4, CFG_DBAT6L@l + lis r3, CFG_DBAT6U@h + ori r3, r3, CFG_DBAT6U@l + mtspr DBAT6L, r4 + mtspr DBAT6U, r3 + isync + blr + + .globl clear_tlbs +clear_tlbs: + addis r3, 0, 0x0000 + addis r5, 0, 0x4 + isync tlblp: - tlbie r3 + tlbie r3 sync - addi r3, r3, 0x1000 - cmp 0, 0, r3, r5 + addi r3, r3, 0x1000 + cmp 0, 0, r3, r5 blt tlblp - blr .globl enable_addr_trans @@ -708,50 +721,6 @@ in32r: blr /* - * Function: ppcDcbf - * Description: Data Cache block flush - * Input: r3 = effective address - * Output: none. - */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/* - * Function: ppcDcbi - * Description: Data Cache block Invalidate - * Input: r3 = effective address - * Output: none. - */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/* - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - */ - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - -/* - * Function: ppcSync - * Description: Processor Synchronize - * Input: none. - * Output: none. - */ - .globl ppcSync -ppcSync: - sync - blr - -/* * void relocate_code (addr_sp, gd, addr_moni) * * This "function" does not return, instead it continues in RAM @@ -767,7 +736,7 @@ relocate_code: mr r1, r3 /* Set new stack pointer */ mr r9, r4 /* Save copy of Global Data pointer */ - mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */ + mr r2, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */ mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ diff --git a/cpu/mpc8xx/config.mk b/cpu/mpc8xx/config.mk index bfa6625..6031e7f 100644 --- a/cpu/mpc8xx/config.mk +++ b/cpu/mpc8xx/config.mk @@ -23,4 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -ffixed-r29 -mstring -mcpu=860 -msoft-float +PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk index 4fd5108..311c97b 100644 --- a/cpu/ppc4xx/config.mk +++ b/cpu/ppc4xx/config.mk @@ -22,7 +22,7 @@ # PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -msoft-float +PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') is440=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg)) diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 825bc21..60f89c9 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -3,7 +3,7 @@ * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core * DDR2 controller, specifically the 440EPx/GRx. * - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Larry Johnson, lrj@acm.org. * * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is... @@ -77,10 +77,10 @@ * memory. * * If at some time this restriction doesn't apply anymore, just define - * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * CONFIG_4xx_DCACHE in the board config file and this code should setup * everything correctly. */ -#if defined(CFG_ENABLE_SDRAM_CACHE) +#if defined(CONFIG_4xx_DCACHE) #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index ec1b38c..9e2229d 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -121,8 +121,8 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo, /* The NDFC uses Smart Media (SMC) bytes order */ - ecc_code[0] = p[2]; - ecc_code[1] = p[1]; + ecc_code[0] = p[1]; + ecc_code[1] = p[2]; ecc_code[2] = p[3]; return 0; diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 77c2aa4..d8df67b 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -110,6 +110,10 @@ # endif #endif /* CFG_INIT_DCACHE_CS */ +#if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10))) +#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END! +#endif + #define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ @@ -1306,39 +1310,6 @@ in32r: lwbrx r3,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcSync */ -/* Description: Processor Synchronize */ -/* Input: none. */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcSync -ppcSync: - sync - blr - /* * void relocate_code (addr_sp, gd, addr_moni) * |