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-rw-r--r--cpu/leon2/cpu.c9
-rw-r--r--cpu/leon3/cpu.c8
-rw-r--r--cpu/mcf523x/cpu.c14
-rw-r--r--cpu/mcf52x2/cpu.c15
-rw-r--r--cpu/mcf532x/cpu.c14
-rw-r--r--cpu/mcf5445x/cpu.c14
-rw-r--r--cpu/mcf547x_8x/cpu.c21
-rw-r--r--cpu/mpc85xx/Makefile22
-rw-r--r--cpu/mpc85xx/cpu.c8
-rw-r--r--cpu/mpc85xx/cpu_init.c7
-rw-r--r--cpu/mpc85xx/ddr-gen1.c120
-rw-r--r--cpu/mpc85xx/ddr-gen2.c74
-rw-r--r--cpu/mpc85xx/ddr-gen3.c105
-rw-r--r--cpu/mpc85xx/interrupts.c109
-rw-r--r--cpu/mpc85xx/mpc8536_serdes.c180
-rw-r--r--cpu/mpc85xx/pci.c2
-rw-r--r--cpu/mpc85xx/spd_sdram.c1154
-rw-r--r--cpu/mpc85xx/speed.c4
-rw-r--r--cpu/mpc85xx/tlb.c64
19 files changed, 684 insertions, 1260 deletions
diff --git a/cpu/leon2/cpu.c b/cpu/leon2/cpu.c
index 1c1e24b..5de1c52 100644
--- a/cpu/leon2/cpu.c
+++ b/cpu/leon2/cpu.c
@@ -56,3 +56,12 @@ int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
/* ------------------------------------------------------------------------- */
+
+extern int greth_initialize(bd_t *bis);
+
+#ifdef CONFIG_GRETH
+int cpu_eth_init(bd_t *bis)
+{
+ return greth_initialize(bis);
+}
+#endif
diff --git a/cpu/leon3/cpu.c b/cpu/leon3/cpu.c
index 306a210..1725fdb 100644
--- a/cpu/leon3/cpu.c
+++ b/cpu/leon3/cpu.c
@@ -65,3 +65,11 @@ u64 flash_read64(void *addr)
}
/* ------------------------------------------------------------------------- */
+extern int greth_initialize(bd_t *bis);
+
+#ifdef CONFIG_GRETH
+int cpu_eth_init(bd_t *bis)
+{
+ return greth_initialize(bis);
+}
+#endif
diff --git a/cpu/mcf523x/cpu.c b/cpu/mcf523x/cpu.c
index f0d954b..8d2152d 100644
--- a/cpu/mcf523x/cpu.c
+++ b/cpu/mcf523x/cpu.c
@@ -107,3 +107,17 @@ int watchdog_init(void)
return (0);
}
#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int mcffec_initialize(bd_t*);
+
+int cpu_eth_init(bd_t *bis)
+{
+ return mcffec_initialize(bis);
+}
+#endif
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index d5d3d33..2af31cb 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -321,3 +321,18 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
return 0;
};
#endif
+
+#if defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int mcffec_initialize(bd_t*);
+
+int cpu_eth_init(bd_t *bis)
+{
+ return mcffec_initialize(bis);
+}
+#endif
+
diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c
index 61541ab..20d0d5c 100644
--- a/cpu/mcf532x/cpu.c
+++ b/cpu/mcf532x/cpu.c
@@ -129,3 +129,17 @@ int watchdog_init(void)
return (0);
}
#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int mcffec_initialize(bd_t*);
+
+int cpu_eth_init(bd_t *bis)
+{
+ return mcffec_initialize(bis);
+}
+#endif
diff --git a/cpu/mcf5445x/cpu.c b/cpu/mcf5445x/cpu.c
index e601b89..ab342dd 100644
--- a/cpu/mcf5445x/cpu.c
+++ b/cpu/mcf5445x/cpu.c
@@ -95,3 +95,17 @@ int checkcpu(void)
return 0;
}
+
+#if defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int mcffec_initialize(bd_t*);
+
+int cpu_eth_init(bd_t *bis)
+{
+ return mcffec_initialize(bis);
+}
+#endif
diff --git a/cpu/mcf547x_8x/cpu.c b/cpu/mcf547x_8x/cpu.c
index 528bca6..1ba7aa8 100644
--- a/cpu/mcf547x_8x/cpu.c
+++ b/cpu/mcf547x_8x/cpu.c
@@ -141,3 +141,24 @@ int watchdog_init(void)
return (0);
}
#endif /* CONFIG_HW_WATCHDOG */
+
+#if defined(CONFIG_FSLDMAFEC) || defined(CONFIG_MCFFEC)
+/* Default initializations for MCFFEC controllers. To override,
+ * create a board-specific function called:
+ * int board_eth_init(bd_t *bis)
+ */
+
+extern int mcdmafec_initialize(bd_t *bis);
+extern int mcffec_initialize(bd_t*);
+
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSLDMAFEC)
+ mcdmafec_initialize(bis);
+#endif
+#if defined(CONFIG_MCFFEC)
+ mcffec_initialize(bis);
+#endif
+ return 0;
+}
+#endif
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index d51a6dd..627e61b 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -34,14 +34,22 @@ SOBJS = $(SOBJS-y)
COBJS-$(CONFIG_MP) += mp.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
-ifneq ($(CONFIG_FSL_DDR3),y)
-ifneq ($(CONFIG_FSL_DDR2),y)
-ifneq ($(CONFIG_FSL_DDR1),y)
-COBJS-y += spd_sdram.o
-endif
-endif
-endif
+# supports ddr1
+COBJS-$(CONFIG_MPC8540) += ddr-gen1.o
+COBJS-$(CONFIG_MPC8560) += ddr-gen1.o
+COBJS-$(CONFIG_MPC8541) += ddr-gen1.o
+COBJS-$(CONFIG_MPC8555) += ddr-gen1.o
+# supports ddr1/2
+COBJS-$(CONFIG_MPC8548) += ddr-gen2.o
+COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
+COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
+
+# supports ddr1/2/3
+COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
+COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
+
+COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
pci.o serial_scc.o commproc.o ether_fcc.o qe_io.o \
$(COBJS-y)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index bde8e56..2fe3cea 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -36,6 +36,8 @@ DECLARE_GLOBAL_DATA_PTR;
struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8533, 8533),
CPU_TYPE_ENTRY(8533, 8533_E),
+ CPU_TYPE_ENTRY(8536, 8536),
+ CPU_TYPE_ENTRY(8536, 8536_E),
CPU_TYPE_ENTRY(8540, 8540),
CPU_TYPE_ENTRY(8541, 8541),
CPU_TYPE_ENTRY(8541, 8541_E),
@@ -89,6 +91,9 @@ int checkcpu (void)
svr = get_svr();
ver = SVR_SOC_VER(svr);
major = SVR_MAJ(svr);
+#ifdef CONFIG_MPC8536
+ major &= 0x7; /* the msb of this nibble is a mfg code */
+#endif
minor = SVR_MIN(svr);
puts("CPU: ");
@@ -154,7 +159,8 @@ int checkcpu (void)
#endif
clkdiv = lcrr & 0x0f;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
+#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
+ defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
/*
* Yes, the entire PQ38 family use the same
* bit-representation for twice the clock divider values.
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 4feb751..783c5ba 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -37,6 +37,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_MPC8536
+extern void fsl_serdes_init(void);
+#endif
+
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -240,6 +244,9 @@ void cpu_init_f (void)
/* Config QE ioports */
config_qe_ioports();
#endif
+#if defined(CONFIG_MPC8536)
+ fsl_serdes_init();
+#endif
}
diff --git a/cpu/mpc85xx/ddr-gen1.c b/cpu/mpc85xx/ddr-gen1.c
new file mode 100644
index 0000000..2c11ee4
--- /dev/null
+++ b/cpu/mpc85xx/ddr-gen1.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR;
+
+ if (ctrl_num != 0) {
+ printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+ return;
+ }
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i == 0) {
+ out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs0_config, regs->cs[i].config);
+
+ } else if (i == 1) {
+ out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs1_config, regs->cs[i].config);
+
+ } else if (i == 2) {
+ out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs2_config, regs->cs[i].config);
+
+ } else if (i == 3) {
+ out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs3_config, regs->cs[i].config);
+ }
+ }
+
+ out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+ out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+ out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+ out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541)
+ out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+#endif
+
+ /*
+ * 200 painful micro-seconds must elapse between
+ * the DDR clock setup and the DDR config enable.
+ */
+ udelay(200);
+ asm volatile("sync;isync");
+
+ out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+
+ asm("sync;isync;msync");
+ udelay(500);
+}
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void dma_init(void);
+extern uint dma_check(void);
+extern int dma_xfer(void *dest, uint count, void *src);
+
+/*
+ * Initialize all of memory for ECC, then enable errors.
+ */
+
+void
+ddr_enable_ecc(unsigned int dram_size)
+{
+ uint *p = 0;
+ uint i = 0;
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+
+ dma_init();
+
+ for (*p = 0; p < (uint *)(8 * 1024); p++) {
+ if (((unsigned int)p & 0x1f) == 0) {
+ ppcDcbz((unsigned long) p);
+ }
+ *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
+ if (((unsigned int)p & 0x1c) == 0x1c) {
+ ppcDcbf((unsigned long) p);
+ }
+ }
+
+ dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
+ dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
+ dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
+ dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
+ dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
+ dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
+ dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
+ dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
+ dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
+ dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
+
+ for (i = 1; i < dram_size / 0x800000; i++) {
+ dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
+ }
+
+ /*
+ * Enable errors for ECC.
+ */
+ debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
+ ddr->err_disable = 0x00000000;
+ asm("sync;isync;msync");
+ debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
+}
+
+#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
diff --git a/cpu/mpc85xx/ddr-gen2.c b/cpu/mpc85xx/ddr-gen2.c
new file mode 100644
index 0000000..130090c
--- /dev/null
+++ b/cpu/mpc85xx/ddr-gen2.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR;
+
+ if (ctrl_num) {
+ printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+ return;
+ }
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i == 0) {
+ out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs0_config, regs->cs[i].config);
+
+ } else if (i == 1) {
+ out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs1_config, regs->cs[i].config);
+
+ } else if (i == 2) {
+ out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs2_config, regs->cs[i].config);
+
+ } else if (i == 3) {
+ out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs3_config, regs->cs[i].config);
+ }
+ }
+
+ out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+ out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+ out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+ out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+ out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+ out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+ out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+ out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+ out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+ out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
+ out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+ out_be32(&ddr->init_addr, regs->ddr_init_addr);
+ out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+
+ /*
+ * 200 painful micro-seconds must elapse between
+ * the DDR clock setup and the DDR config enable.
+ */
+ udelay(200);
+ asm volatile("sync;isync");
+
+ out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+
+ /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
+ while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
+ udelay(10000); /* throttle polling rate */
+ }
+}
diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c
new file mode 100644
index 0000000..d7cc9db
--- /dev/null
+++ b/cpu/mpc85xx/ddr-gen3.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
+#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
+#endif
+
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ volatile ccsr_ddr_t *ddr;
+
+ switch (ctrl_num) {
+ case 0:
+ ddr = (void *)CFG_MPC85xx_DDR_ADDR;
+ break;
+ case 1:
+ ddr = (void *)CFG_MPC85xx_DDR2_ADDR;
+ break;
+ default:
+ printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+ return;
+ }
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i == 0) {
+ out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs0_config, regs->cs[i].config);
+ out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
+
+ } else if (i == 1) {
+ out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs1_config, regs->cs[i].config);
+ out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
+
+ } else if (i == 2) {
+ out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs2_config, regs->cs[i].config);
+ out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
+
+ } else if (i == 3) {
+ out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
+ out_be32(&ddr->cs3_config, regs->cs[i].config);
+ out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
+ }
+ }
+
+ out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
+ out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
+ out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
+ out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
+ out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+ out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
+ out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
+ out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+ out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+ out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
+ out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
+ out_be32(&ddr->init_addr, regs->ddr_init_addr);
+ out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+
+ out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
+ out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
+ out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
+ out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+ out_be32(&ddr->ddr_pd_cntl, regs->ddr_pd_cntl);
+ out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
+ out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
+ out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+
+ /*
+ * 32-bit workaround for DDR2
+ * 32_BE
+ */
+ if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
+ && in_be32(&ddr->sdram_cfg_2) & 0x80000) {
+ /* set DEBUG_1[31] */
+ u32 temp = in_be32(&ddr->debug_1);
+ out_be32(&ddr->debug_1, temp | 1);
+ }
+
+ /*
+ * 200 painful micro-seconds must elapse between
+ * the DDR clock setup and the DDR config enable.
+ */
+ udelay(200);
+ asm volatile("sync;isync");
+
+ out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+
+ /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
+ while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
+ udelay(10000); /* throttle polling rate */
+ }
+}
diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c
index 4fe1fac..06d4d8b 100644
--- a/cpu/mpc85xx/interrupts.c
+++ b/cpu/mpc85xx/interrupts.c
@@ -31,64 +31,20 @@
#include <watchdog.h>
#include <command.h>
#include <asm/processor.h>
-#include <ppc_asm.tmpl>
-unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
-
-static __inline__ unsigned long get_msr(void)
-{
- unsigned long msr;
-
- asm volatile("mfmsr %0" : "=r" (msr) :);
- return msr;
-}
-
-static __inline__ void set_msr(unsigned long msr)
-{
- asm volatile("mtmsr %0" : : "r" (msr));
- asm volatile("isync");
-}
-
-static __inline__ unsigned long get_dec (void)
-{
- unsigned long val;
-
- asm volatile ("mfdec %0":"=r" (val):);
-
- return val;
-}
-
-
-static __inline__ void set_dec (unsigned long val)
-{
- if (val)
- asm volatile ("mtdec %0"::"r" (val));
-}
-
-void enable_interrupts (void)
-{
- set_msr (get_msr() | MSR_EE);
-}
-
-/* returns flag if MSR_EE was set before */
-int disable_interrupts (void)
-{
- ulong msr = get_msr();
- set_msr (msr & ~MSR_EE);
- return ((msr & MSR_EE) != 0);
-}
-
-int interrupt_init (void)
+int interrupt_init_cpu(unsigned long *decrementer_count)
{
volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
pic->gcr = MPC85xx_PICGCR_RST;
- while (pic->gcr & MPC85xx_PICGCR_RST);
+ while (pic->gcr & MPC85xx_PICGCR_RST)
+ ;
pic->gcr = MPC85xx_PICGCR_M;
- decrementer_count = get_tbclk() / CFG_HZ;
+
+ *decrementer_count = get_tbclk() / CFG_HZ;
+
+ /* PIE is same as DIE, dec interrupt enable */
mtspr(SPRN_TCR, TCR_PIE);
- set_dec (decrementer_count);
- set_msr (get_msr () | MSR_EE);
#ifdef CONFIG_INTERRUPTS
pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
@@ -123,9 +79,7 @@ int interrupt_init (void)
return (0);
}
-/*
- * Install and free a interrupt handler. Not implemented yet.
- */
+/* Install and free a interrupt handler. Not implemented yet. */
void
irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
@@ -139,55 +93,16 @@ irq_free_handler(int vec)
return;
}
-/****************************************************************************/
-
-
-volatile ulong timestamp = 0;
-
-/*
- * timer_interrupt - gets called when the decrementer overflows,
- * with interrupts disabled.
- * Trivial implementation - no need to be really accurate.
- */
-void timer_interrupt(struct pt_regs *regs)
+void timer_interrupt_cpu(struct pt_regs *regs)
{
- timestamp++;
- set_dec (decrementer_count);
+ /* PIS is same as DIS, dec interrupt status */
mtspr(SPRN_TSR, TSR_PIS);
-#if defined(CONFIG_WATCHDOG)
- if ((timestamp % 1000) == 0)
- reset_85xx_watchdog();
-#endif /* CONFIG_WATCHDOG */
-}
-
-void reset_timer (void)
-{
- timestamp = 0;
-}
-
-ulong get_timer (ulong base)
-{
- return (timestamp - base);
-}
-
-void set_timer (ulong t)
-{
- timestamp = t;
}
#if defined(CONFIG_CMD_IRQ)
-
-/*******************************************************************************
- *
- * irqinfo - print information about PCI devices,not implemented.
- *
- */
-int
-do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+/* irqinfo - print information about PCI devices,not implemented. */
+int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- printf ("\nInterrupt-unsupported:\n");
-
return 0;
}
-
#endif
diff --git a/cpu/mpc85xx/mpc8536_serdes.c b/cpu/mpc85xx/mpc8536_serdes.c
new file mode 100644
index 0000000..ae091e6
--- /dev/null
+++ b/cpu/mpc85xx/mpc8536_serdes.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (C) 2008 Freescale Semicondutor, Inc. All rights reserved.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+
+/* PORDEVSR register */
+#define GUTS_PORDEVSR_OFFS 0xc
+#define GUTS_PORDEVSR_SERDES2_IO_SEL 0x38000000
+#define GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT 27
+
+/* SerDes CR0 register */
+#define FSL_SRDSCR0_OFFS 0x0
+#define FSL_SRDSCR0_TXEQA_MASK 0x00007000
+#define FSL_SRDSCR0_TXEQA_SGMII 0x00004000
+#define FSL_SRDSCR0_TXEQA_SATA 0x00001000
+#define FSL_SRDSCR0_TXEQE_MASK 0x00000700
+#define FSL_SRDSCR0_TXEQE_SGMII 0x00000400
+#define FSL_SRDSCR0_TXEQE_SATA 0x00000100
+
+/* SerDes CR1 register */
+#define FSL_SRDSCR1_OFFS 0x4
+#define FSL_SRDSCR1_LANEA_MASK 0x80200000
+#define FSL_SRDSCR1_LANEA_OFF 0x80200000
+#define FSL_SRDSCR1_LANEE_MASK 0x08020000
+#define FSL_SRDSCR1_LANEE_OFF 0x08020000
+
+/* SerDes CR2 register */
+#define FSL_SRDSCR2_OFFS 0x8
+#define FSL_SRDSCR2_EICA_MASK 0x00001f00
+#define FSL_SRDSCR2_EICA_SGMII 0x00000400
+#define FSL_SRDSCR2_EICA_SATA 0x00001400
+#define FSL_SRDSCR2_EICE_MASK 0x0000001f
+#define FSL_SRDSCR2_EICE_SGMII 0x00000004
+#define FSL_SRDSCR2_EICE_SATA 0x00000014
+
+/* SerDes CR3 register */
+#define FSL_SRDSCR3_OFFS 0xc
+#define FSL_SRDSCR3_LANEA_MASK 0x3f000700
+#define FSL_SRDSCR3_LANEA_SGMII 0x00000000
+#define FSL_SRDSCR3_LANEA_SATA 0x15000500
+#define FSL_SRDSCR3_LANEE_MASK 0x003f0007
+#define FSL_SRDSCR3_LANEE_SGMII 0x00000000
+#define FSL_SRDSCR3_LANEE_SATA 0x00150005
+
+void fsl_serdes_init(void)
+{
+ void *guts = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ void *sd = (void *)CFG_MPC85xx_SERDES2_ADDR;
+ u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
+ u32 srds2_io_sel;
+ u32 tmp;
+
+ /* parse the SRDS2_IO_SEL of PORDEVSR */
+ srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL)
+ >> GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
+
+ switch (srds2_io_sel) {
+ case 1: /* Lane A - SATA1, Lane E - SATA2 */
+ /* CR 0 */
+ tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
+ tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
+ tmp |= FSL_SRDSCR0_TXEQA_SATA;
+ tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
+ tmp |= FSL_SRDSCR0_TXEQE_SATA;
+ out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
+ /* CR 1 */
+ tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
+ tmp &= ~FSL_SRDSCR1_LANEA_MASK;
+ tmp &= ~FSL_SRDSCR1_LANEE_MASK;
+ out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
+ /* CR 2 */
+ tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
+ tmp &= ~FSL_SRDSCR2_EICA_MASK;
+ tmp |= FSL_SRDSCR2_EICA_SATA;
+ tmp &= ~FSL_SRDSCR2_EICE_MASK;
+ tmp |= FSL_SRDSCR2_EICE_SATA;
+ out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
+ /* CR 3 */
+ tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
+ tmp &= ~FSL_SRDSCR3_LANEA_MASK;
+ tmp |= FSL_SRDSCR3_LANEA_SATA;
+ tmp &= ~FSL_SRDSCR3_LANEE_MASK;
+ tmp |= FSL_SRDSCR3_LANEE_SATA;
+ out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
+ break;
+ case 3: /* Lane A - SATA1, Lane E - disabled */
+ /* CR 0 */
+ tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
+ tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
+ tmp |= FSL_SRDSCR0_TXEQA_SATA;
+ out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
+ /* CR 1 */
+ tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
+ tmp &= ~FSL_SRDSCR1_LANEE_MASK;
+ tmp |= FSL_SRDSCR1_LANEE_OFF;
+ out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
+ /* CR 2 */
+ tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
+ tmp &= ~FSL_SRDSCR2_EICA_MASK;
+ tmp |= FSL_SRDSCR2_EICA_SATA;
+ out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
+ /* CR 3 */
+ tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
+ tmp &= ~FSL_SRDSCR3_LANEA_MASK;
+ tmp |= FSL_SRDSCR3_LANEA_SATA;
+ out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
+ break;
+ case 4: /* Lane A - eTSEC1 SGMII, Lane E - eTSEC3 SGMII */
+ /* CR 0 */
+ tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
+ tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
+ tmp |= FSL_SRDSCR0_TXEQA_SGMII;
+ tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
+ tmp |= FSL_SRDSCR0_TXEQE_SGMII;
+ out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
+ /* CR 1 */
+ tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
+ tmp &= ~FSL_SRDSCR1_LANEA_MASK;
+ tmp &= ~FSL_SRDSCR1_LANEE_MASK;
+ out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
+ /* CR 2 */
+ tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
+ tmp &= ~FSL_SRDSCR2_EICA_MASK;
+ tmp |= FSL_SRDSCR2_EICA_SGMII;
+ tmp &= ~FSL_SRDSCR2_EICE_MASK;
+ tmp |= FSL_SRDSCR2_EICE_SGMII;
+ out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
+ /* CR 3 */
+ tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
+ tmp &= ~FSL_SRDSCR3_LANEA_MASK;
+ tmp |= FSL_SRDSCR3_LANEA_SGMII;
+ tmp &= ~FSL_SRDSCR3_LANEE_MASK;
+ tmp |= FSL_SRDSCR3_LANEE_SGMII;
+ out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
+ break;
+ case 6: /* Lane A - eTSEC1 SGMII, Lane E - disabled */
+ /* CR 0 */
+ tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
+ tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
+ tmp |= FSL_SRDSCR0_TXEQA_SGMII;
+ out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
+ /* CR 1 */
+ tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
+ tmp &= ~FSL_SRDSCR1_LANEE_MASK;
+ tmp |= FSL_SRDSCR1_LANEE_OFF;
+ out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
+ /* CR 2 */
+ tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
+ tmp &= ~FSL_SRDSCR2_EICA_MASK;
+ tmp |= FSL_SRDSCR2_EICA_SGMII;
+ out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
+ /* CR 3 */
+ tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
+ tmp &= ~FSL_SRDSCR3_LANEA_MASK;
+ tmp |= FSL_SRDSCR3_LANEA_SGMII;
+ out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
+ break;
+ case 7: /* Lane A - disabled, Lane E - disabled */
+ /* CR 1 */
+ tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
+ tmp &= ~FSL_SRDSCR1_LANEA_MASK;
+ tmp |= FSL_SRDSCR1_LANEA_OFF;
+ tmp &= ~FSL_SRDSCR1_LANEE_MASK;
+ tmp |= FSL_SRDSCR1_LANEE_OFF;
+ out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
+ break;
+ default:
+ break;
+ }
+}
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index a5060cd..fdc4c83 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -29,7 +29,7 @@
#include <asm/cpm_85xx.h>
#include <pci.h>
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)
static struct pci_controller *pci_hose;
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
deleted file mode 100644
index 8e321eb..0000000
--- a/cpu/mpc85xx/spd_sdram.c
+++ /dev/null
@@ -1,1154 +0,0 @@
-/*
- * Copyright 2004, 2007 Freescale Semiconductor.
- * (C) Copyright 2003 Motorola Inc.
- * Xianghua Xiao (X.Xiao@motorola.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <spd.h>
-#include <asm/mmu.h>
-#include <asm/fsl_law.h>
-
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void dma_init(void);
-extern uint dma_check(void);
-extern int dma_xfer(void *dest, uint count, void *src);
-#endif
-
-#ifdef CONFIG_SPD_EEPROM
-
-#ifndef CFG_READ_SPD
-#define CFG_READ_SPD i2c_read
-#endif
-
-static unsigned int setup_laws_and_tlbs(unsigned int memsize);
-
-
-/*
- * Convert picoseconds into clock cycles (rounding up if needed).
- */
-
-int
-picos_to_clk(int picos)
-{
- int clks;
-
- clks = picos / (2000000000 / (get_ddr_freq(0) / 1000));
- if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) {
- clks++;
- }
-
- return clks;
-}
-
-
-/*
- * Calculate the Density of each Physical Rank.
- * Returned size is in bytes.
- *
- * Study these table from Byte 31 of JEDEC SPD Spec.
- *
- * DDR I DDR II
- * Bit Size Size
- * --- ----- ------
- * 7 high 512MB 512MB
- * 6 256MB 256MB
- * 5 128MB 128MB
- * 4 64MB 16GB
- * 3 32MB 8GB
- * 2 16MB 4GB
- * 1 2GB 2GB
- * 0 low 1GB 1GB
- *
- * Reorder Table to be linear by stripping the bottom
- * 2 or 5 bits off and shifting them up to the top.
- */
-
-unsigned int
-compute_banksize(unsigned int mem_type, unsigned char row_dens)
-{
- unsigned int bsize;
-
- if (mem_type == SPD_MEMTYPE_DDR) {
- /* Bottom 2 bits up to the top. */
- bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
- debug("DDR: DDR I rank density = 0x%08x\n", bsize);
- } else {
- /* Bottom 5 bits up to the top. */
- bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
- debug("DDR: DDR II rank density = 0x%08x\n", bsize);
- }
- return bsize;
-}
-
-
-/*
- * Convert a two-nibble BCD value into a cycle time.
- * While the spec calls for nano-seconds, picos are returned.
- *
- * This implements the tables for bytes 9, 23 and 25 for both
- * DDR I and II. No allowance for distinguishing the invalid
- * fields absent for DDR I yet present in DDR II is made.
- * (That is, cycle times of .25, .33, .66 and .75 ns are
- * allowed for both DDR II and I.)
- */
-
-unsigned int
-convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
-{
- /*
- * Table look up the lower nibble, allow DDR I & II.
- */
- unsigned int tenths_ps[16] = {
- 0,
- 100,
- 200,
- 300,
- 400,
- 500,
- 600,
- 700,
- 800,
- 900,
- 250,
- 330,
- 660,
- 750,
- 0, /* undefined */
- 0 /* undefined */
- };
-
- unsigned int whole_ns = (spd_val & 0xF0) >> 4;
- unsigned int tenth_ns = spd_val & 0x0F;
- unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
-
- return ps;
-}
-
-
-/*
- * Determine Refresh Rate. Ignore self refresh bit on DDR I.
- * Table from SPD Spec, Byte 12, converted to picoseconds and
- * filled in with "default" normal values.
- */
-unsigned int determine_refresh_rate(unsigned int spd_refresh)
-{
- unsigned int refresh_time_ns[8] = {
- 15625000, /* 0 Normal 1.00x */
- 3900000, /* 1 Reduced .25x */
- 7800000, /* 2 Extended .50x */
- 31300000, /* 3 Extended 2.00x */
- 62500000, /* 4 Extended 4.00x */
- 125000000, /* 5 Extended 8.00x */
- 15625000, /* 6 Normal 1.00x filler */
- 15625000, /* 7 Normal 1.00x filler */
- };
-
- return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]);
-}
-
-
-long int
-spd_sdram(void)
-{
- volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
- spd_eeprom_t spd;
- unsigned int n_ranks;
- unsigned int rank_density;
- unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits;
- unsigned int odt_cfg, mode_odt_enable;
- unsigned int refresh_clk;
-#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
- unsigned char clk_adjust;
-#endif
- unsigned int dqs_cfg;
- unsigned char twr_clk, twtr_clk, twr_auto_clk;
- unsigned int tCKmin_ps, tCKmax_ps;
- unsigned int max_data_rate, effective_data_rate;
- unsigned int busfreq;
- unsigned sdram_cfg;
- unsigned int memsize = 0;
- unsigned char caslat, caslat_ctrl;
- unsigned int trfc, trfc_clk, trfc_low, trfc_high;
- unsigned int trcd_clk;
- unsigned int trtp_clk;
- unsigned char cke_min_clk;
- unsigned char add_lat;
- unsigned char wr_lat;
- unsigned char wr_data_delay;
- unsigned char four_act;
- unsigned char cpo;
- unsigned char burst_len;
- unsigned int mode_caslat;
- unsigned char sdram_type;
- unsigned char d_init;
- unsigned int bnds;
-
- /*
- * Skip configuration if already configured.
- * memsize is determined from last configured chip select.
- */
- if (ddr->cs0_config & 0x80000000) {
- debug(" cs0 already configured, bnds=%x\n",ddr->cs0_bnds);
- bnds = 0xfff & ddr->cs0_bnds;
- if (bnds < 0xff) { /* do not add if at top of 4G */
- memsize = (bnds + 1) << 4;
- }
- }
- if (ddr->cs1_config & 0x80000000) {
- debug(" cs1 already configured, bnds=%x\n",ddr->cs1_bnds);
- bnds = 0xfff & ddr->cs1_bnds;
- if (bnds < 0xff) { /* do not add if at top of 4G */
- memsize = (bnds + 1) << 4; /* assume ordered bnds */
- }
- }
- if (ddr->cs2_config & 0x80000000) {
- debug(" cs2 already configured, bnds=%x\n",ddr->cs2_bnds);
- bnds = 0xfff & ddr->cs2_bnds;
- if (bnds < 0xff) { /* do not add if at top of 4G */
- memsize = (bnds + 1) << 4;
- }
- }
- if (ddr->cs3_config & 0x80000000) {
- debug(" cs3 already configured, bnds=%x\n",ddr->cs3_bnds);
- bnds = 0xfff & ddr->cs3_bnds;
- if (bnds < 0xff) { /* do not add if at top of 4G */
- memsize = (bnds + 1) << 4;
- }
- }
-
- if (memsize) {
- printf(" Reusing current %dMB configuration\n",memsize);
- memsize = setup_laws_and_tlbs(memsize);
- return memsize << 20;
- }
-
- /*
- * Read SPD information.
- */
- CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd));
-
- /*
- * Check for supported memory module types.
- */
- if (spd.mem_type != SPD_MEMTYPE_DDR &&
- spd.mem_type != SPD_MEMTYPE_DDR2) {
- printf("Unable to locate DDR I or DDR II module.\n"
- " Fundamental memory type is 0x%0x\n",
- spd.mem_type);
- return 0;
- }
-
- /*
- * These test gloss over DDR I and II differences in interpretation
- * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
- * are not supported on DDR I; and not encoded on DDR II.
- *
- * Also note that the 8548 controller can support:
- * 12 <= nrow <= 16
- * and
- * 8 <= ncol <= 11 (still, for DDR)
- * 6 <= ncol <= 9 (for FCRAM)
- */
- if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
- printf("DDR: Unsupported number of Row Addr lines: %d.\n",
- spd.nrow_addr);
- return 0;
- }
- if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
- printf("DDR: Unsupported number of Column Addr lines: %d.\n",
- spd.ncol_addr);
- return 0;
- }
-
- /*
- * Determine the number of physical banks controlled by
- * different Chip Select signals. This is not quite the
- * same as the number of DIMM modules on the board. Feh.
- */
- if (spd.mem_type == SPD_MEMTYPE_DDR) {
- n_ranks = spd.nrows;
- } else {
- n_ranks = (spd.nrows & 0x7) + 1;
- }
-
- debug("DDR: number of ranks = %d\n", n_ranks);
-
- if (n_ranks > 2) {
- printf("DDR: Only 2 chip selects are supported: %d\n",
- n_ranks);
- return 0;
- }
-
-#ifdef CONFIG_MPC8548
- /*
- * Adjust DDR II IO voltage biasing.
- * Only 8548 rev 1 needs the fix
- */
- if ((SVR_SOC_VER(get_svr()) == SVR_8548_E) &&
- (SVR_MJREV(get_svr()) == 1) &&
- (spd.mem_type == SPD_MEMTYPE_DDR2)) {
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- gur->ddrioovcr = (0x80000000 /* Enable */
- | 0x10000000);/* VSEL to 1.8V */
- }
-#endif
-
- /*
- * Determine the size of each Rank in bytes.
- */
- rank_density = compute_banksize(spd.mem_type, spd.row_dens);
-
-
- /*
- * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
- */
- ddr->cs0_bnds = (rank_density >> 24) - 1;
-
- /*
- * ODT configuration recommendation from DDR Controller Chapter.
- */
- odt_rd_cfg = 0; /* Never assert ODT */
- odt_wr_cfg = 0; /* Never assert ODT */
- if (spd.mem_type == SPD_MEMTYPE_DDR2) {
- odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
-#if 0
- /* FIXME: How to determine the number of dimm modules? */
- if (n_dimm_modules == 2) {
- odt_rd_cfg = 1; /* Assert ODT on reads to CS0 */
- }
-#endif
- }
-
- ba_bits = 0;
- if (spd.nbanks == 0x8)
- ba_bits = 1;
-
- ddr->cs0_config = ( 1 << 31
- | (odt_rd_cfg << 20)
- | (odt_wr_cfg << 16)
- | (ba_bits << 14)
- | (spd.nrow_addr - 12) << 8
- | (spd.ncol_addr - 8) );
- debug("\n");
- debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
- debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
-
- if (n_ranks == 2) {
- /*
- * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg
- */
- ddr->cs1_bnds = ( (rank_density >> 8)
- | ((rank_density >> (24 - 1)) - 1) );
- ddr->cs1_config = ( 1<<31
- | (odt_rd_cfg << 20)
- | (odt_wr_cfg << 16)
- | (spd.nrow_addr - 12) << 8
- | (spd.ncol_addr - 8) );
- debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
- debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
- }
-
-
- /*
- * Find the largest CAS by locating the highest 1 bit
- * in the spd.cas_lat field. Translate it to a DDR
- * controller field value:
- *
- * CAS Lat DDR I DDR II Ctrl
- * Clocks SPD Bit SPD Bit Value
- * ------- ------- ------- -----
- * 1.0 0 0001
- * 1.5 1 0010
- * 2.0 2 2 0011
- * 2.5 3 0100
- * 3.0 4 3 0101
- * 3.5 5 0110
- * 4.0 4 0111
- * 4.5 1000
- * 5.0 5 1001
- */
- caslat = __ilog2(spd.cas_lat);
- if ((spd.mem_type == SPD_MEMTYPE_DDR)
- && (caslat > 5)) {
- printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
- return 0;
-
- } else if (spd.mem_type == SPD_MEMTYPE_DDR2
- && (caslat < 2 || caslat > 5)) {
- printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
- spd.cas_lat);
- return 0;
- }
- debug("DDR: caslat SPD bit is %d\n", caslat);
-
- /*
- * Calculate the Maximum Data Rate based on the Minimum Cycle time.
- * The SPD clk_cycle field (tCKmin) is measured in tenths of
- * nanoseconds and represented as BCD.
- */
- tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
- debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
-
- /*
- * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
- */
- max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
- debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
-
-
- /*
- * Adjust the CAS Latency to allow for bus speeds that
- * are slower than the DDR module.
- */
- busfreq = get_ddr_freq(0) / 1000000; /* MHz */
-
- effective_data_rate = max_data_rate;
- if (busfreq < 90) {
- /* DDR rate out-of-range */
- puts("DDR: platform frequency is not fit for DDR rate\n");
- return 0;
-
- } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) {
- /*
- * busfreq 90~230 range, treated as DDR 200.
- */
- effective_data_rate = 200;
- if (spd.clk_cycle3 == 0xa0) /* 10 ns */
- caslat -= 2;
- else if (spd.clk_cycle2 == 0xa0)
- caslat--;
-
- } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) {
- /*
- * busfreq 230~280 range, treated as DDR 266.
- */
- effective_data_rate = 266;
- if (spd.clk_cycle3 == 0x75) /* 7.5 ns */
- caslat -= 2;
- else if (spd.clk_cycle2 == 0x75)
- caslat--;
-
- } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) {
- /*
- * busfreq 280~350 range, treated as DDR 333.
- */
- effective_data_rate = 333;
- if (spd.clk_cycle3 == 0x60) /* 6.0 ns */
- caslat -= 2;
- else if (spd.clk_cycle2 == 0x60)
- caslat--;
-
- } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) {
- /*
- * busfreq 350~460 range, treated as DDR 400.
- */
- effective_data_rate = 400;
- if (spd.clk_cycle3 == 0x50) /* 5.0 ns */
- caslat -= 2;
- else if (spd.clk_cycle2 == 0x50)
- caslat--;
-
- } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) {
- /*
- * busfreq 460~560 range, treated as DDR 533.
- */
- effective_data_rate = 533;
- if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */
- caslat -= 2;
- else if (spd.clk_cycle2 == 0x3D)
- caslat--;
-
- } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) {
- /*
- * busfreq 560~700 range, treated as DDR 667.
- */
- effective_data_rate = 667;
- if (spd.clk_cycle3 == 0x30) /* 3.0 ns */
- caslat -= 2;
- else if (spd.clk_cycle2 == 0x30)
- caslat--;
-
- } else if (700 <= busfreq) {
- /*
- * DDR rate out-of-range
- */
- printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
- busfreq, max_data_rate);
- return 0;
- }
-
-
- /*
- * Convert caslat clocks to DDR controller value.
- * Force caslat_ctrl to be DDR Controller field-sized.
- */
- if (spd.mem_type == SPD_MEMTYPE_DDR) {
- caslat_ctrl = (caslat + 1) & 0x07;
- } else {
- caslat_ctrl = (2 * caslat - 1) & 0x0f;
- }
-
- debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
- debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
- caslat, caslat_ctrl);
-
- /*
- * Timing Config 0.
- * Avoid writing for DDR I. The new PQ38 DDR controller
- * dreams up non-zero default values to be backwards compatible.
- */
- if (spd.mem_type == SPD_MEMTYPE_DDR2) {
- unsigned char taxpd_clk = 8; /* By the book. */
- unsigned char tmrd_clk = 2; /* By the book. */
- unsigned char act_pd_exit = 2; /* Empirical? */
- unsigned char pre_pd_exit = 6; /* Empirical? */
-
- ddr->timing_cfg_0 = (0
- | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
- | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
- | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
- | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
- );
-#if 0
- ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */
-#endif
- debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
-
- } else {
-#if 0
- /*
- * Force extra cycles with 0xaa bits.
- * Incidentally supply the dreamt-up backwards compat value!
- */
- ddr->timing_cfg_0 = 0x00110105; /* backwards compat value */
- ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */
- debug("DDR: HACK timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
-#endif
- }
-
-
- /*
- * Some Timing Config 1 values now.
- * Sneak Extended Refresh Recovery in here too.
- */
-
- /*
- * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
- * use conservative value.
- * For DDR II, they are bytes 36 and 37, in quarter nanos.
- */
-
- if (spd.mem_type == SPD_MEMTYPE_DDR) {
- twr_clk = 3; /* Clocks */
- twtr_clk = 1; /* Clocks */
- } else {
- twr_clk = picos_to_clk(spd.twr * 250);
- twtr_clk = picos_to_clk(spd.twtr * 250);
- }
-
- /*
- * Calculate Trfc, in picos.
- * DDR I: Byte 42 straight up in ns.
- * DDR II: Byte 40 and 42 swizzled some, in ns.
- */
- if (spd.mem_type == SPD_MEMTYPE_DDR) {
- trfc = spd.trfc * 1000; /* up to ps */
- } else {
- unsigned int byte40_table_ps[8] = {
- 0,
- 250,
- 330,
- 500,
- 660,
- 750,
- 0,
- 0
- };
-
- trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
- + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
- }
- trfc_clk = picos_to_clk(trfc);
-
- /*
- * Trcd, Byte 29, from quarter nanos to ps and clocks.
- */
- trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
-
- /*
- * Convert trfc_clk to DDR controller fields. DDR I should
- * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
- * 8548 controller has an extended REFREC field of three bits.
- * The controller automatically adds 8 clocks to this value,
- * so preadjust it down 8 first before splitting it up.
- */
- trfc_low = (trfc_clk - 8) & 0xf;
- trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
-
- /*
- * Sneak in some Extended Refresh Recovery.
- */
- ddr->timing_cfg_3 = (trfc_high << 16);
- debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
-
- ddr->timing_cfg_1 =
- (0
- | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
- | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
- | (trcd_clk << 20) /* ACTTORW */
- | (caslat_ctrl << 16) /* CASLAT */
- | (trfc_low << 12) /* REFEC */
- | ((twr_clk & 0x07) << 8) /* WRRREC */
- | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
- | ((twtr_clk & 0x07) << 0) /* WRTORD */
- );
-
- debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
-
-
- /*
- * Timing_Config_2
- * Was: 0x00000800;
- */
-
- /*
- * Additive Latency
- * For DDR I, 0.
- * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
- * which comes from Trcd, and also note that:
- * add_lat + caslat must be >= 4
- */
- add_lat = 0;
- if (spd.mem_type == SPD_MEMTYPE_DDR2
- && (odt_wr_cfg || odt_rd_cfg)
- && (caslat < 4)) {
- add_lat = 4 - caslat;
- if (add_lat > trcd_clk) {
- add_lat = trcd_clk - 1;
- }
- }
-
- /*
- * Write Data Delay
- * Historically 0x2 == 4/8 clock delay.
- * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
- */
- wr_data_delay = 3;
-
- /*
- * Write Latency
- * Read to Precharge
- * Minimum CKE Pulse Width.
- * Four Activate Window
- */
- if (spd.mem_type == SPD_MEMTYPE_DDR) {
- /*
- * This is a lie. It should really be 1, but if it is
- * set to 1, bits overlap into the old controller's
- * otherwise unused ACSM field. If we leave it 0, then
- * the HW will magically treat it as 1 for DDR 1. Oh Yea.
- */
- wr_lat = 0;
-
- trtp_clk = 2; /* By the book. */
- cke_min_clk = 1; /* By the book. */
- four_act = 1; /* By the book. */
-
- } else {
- wr_lat = caslat - 1;
-
- /* Convert SPD value from quarter nanos to picos. */
- trtp_clk = picos_to_clk(spd.trtp * 250);
-
- cke_min_clk = 3; /* By the book. */
- four_act = picos_to_clk(37500); /* By the book. 1k pages? */
- }
-
- /*
- * Empirically set ~MCAS-to-preamble override for DDR 2.
- * Your milage will vary.
- */
- cpo = 0;
- if (spd.mem_type == SPD_MEMTYPE_DDR2) {
- if (effective_data_rate <= 333) {
- cpo = 0x7; /* READ_LAT + 5/4 */
- } else {
- cpo = 0x9; /* READ_LAT + 7/4 */
- }
- }
-
- ddr->timing_cfg_2 = (0
- | ((add_lat & 0x7) << 28) /* ADD_LAT */
- | ((cpo & 0x1f) << 23) /* CPO */
- | ((wr_lat & 0x7) << 19) /* WR_LAT */
- | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
- | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
- | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
- | ((four_act & 0x1f) << 0) /* FOUR_ACT */
- );
-
- debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
-
-
- /*
- * Determine the Mode Register Set.
- *
- * This is nominally part specific, but it appears to be
- * consistent for all DDR I devices, and for all DDR II devices.
- *
- * caslat must be programmed
- * burst length is always 4
- * burst type is sequential
- *
- * For DDR I:
- * operating mode is "normal"
- *
- * For DDR II:
- * other stuff
- */
-
- mode_caslat = 0;
-
- /*
- * Table lookup from DDR I or II Device Operation Specs.
- */
- if (spd.mem_type == SPD_MEMTYPE_DDR) {
- if (1 <= caslat && caslat <= 4) {
- unsigned char mode_caslat_table[4] = {
- 0x5, /* 1.5 clocks */
- 0x2, /* 2.0 clocks */
- 0x6, /* 2.5 clocks */
- 0x3 /* 3.0 clocks */
- };
- mode_caslat = mode_caslat_table[caslat - 1];
- } else {
- puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
- "2.5 and 3.0 clocks are supported.\n");
- return 0;
- }
-
- } else {
- if (2 <= caslat && caslat <= 5) {
- mode_caslat = caslat;
- } else {
- puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
- "4.0 and 5.0 clocks are supported.\n");
- return 0;
- }
- }
-
- /*
- * Encoded Burst Lenght of 4.
- */
- burst_len = 2; /* Fiat. */
-
- if (spd.mem_type == SPD_MEMTYPE_DDR) {
- twr_auto_clk = 0; /* Historical */
- } else {
- /*
- * Determine tCK max in picos. Grab tWR and convert to picos.
- * Auto-precharge write recovery is:
- * WR = roundup(tWR_ns/tCKmax_ns).
- *
- * Ponder: Is twr_auto_clk different than twr_clk?
- */
- tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
- twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
- }
-
-
- /*
- * Mode Reg in bits 16 ~ 31,
- * Extended Mode Reg 1 in bits 0 ~ 15.
- */
- mode_odt_enable = 0x0; /* Default disabled */
- if (odt_wr_cfg || odt_rd_cfg) {
- /*
- * Bits 6 and 2 in Extended MRS(1)
- * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
- * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
- */
- mode_odt_enable = 0x40; /* 150 Ohm */
- }
-
- ddr->sdram_mode =
- (0
- | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
- | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
- | (twr_auto_clk << 9) /* Write Recovery Autopre */
- | (mode_caslat << 4) /* caslat */
- | (burst_len << 0) /* Burst length */
- );
-
- debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode);
-
-
- /*
- * Clear EMRS2 and EMRS3.
- */
- ddr->sdram_mode_2 = 0;
- debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
-
- /*
- * Determine Refresh Rate.
- */
- refresh_clk = determine_refresh_rate(spd.refresh & 0x7);
-
- /*
- * Set BSTOPRE to 0x100 for page mode
- * If auto-charge is used, set BSTOPRE = 0
- */
- ddr->sdram_interval =
- (0
- | (refresh_clk & 0x3fff) << 16
- | 0x100
- );
- debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
-
- /*
- * Is this an ECC DDR chip?
- * But don't mess with it if the DDR controller will init mem.
- */
-#ifdef CONFIG_DDR_ECC
- if (spd.config == 0x02) {
-#ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
- ddr->err_disable = 0x0000000d;
-#endif
- ddr->err_sbe = 0x00ff0000;
- }
-
- debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
- debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
-#endif /* CONFIG_DDR_ECC */
-
- asm("sync;isync;msync");
- udelay(500);
-
- /*
- * SDRAM Cfg 2
- */
-
- /*
- * When ODT is enabled, Chap 9 suggests asserting ODT to
- * internal IOs only during reads.
- */
- odt_cfg = 0;
- if (odt_rd_cfg | odt_wr_cfg) {
- odt_cfg = 0x2; /* ODT to IOs during reads */
- }
-
- /*
- * Try to use differential DQS with DDR II.
- */
- if (spd.mem_type == SPD_MEMTYPE_DDR) {
- dqs_cfg = 0; /* No Differential DQS for DDR I */
- } else {
- dqs_cfg = 0x1; /* Differential DQS for DDR II */
- }
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Use the DDR controller to auto initialize memory.
- */
- d_init = 1;
- ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
- debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
-#else
- /*
- * Memory will be initialized via DMA, or not at all.
- */
- d_init = 0;
-#endif
-
- ddr->sdram_cfg_2 = (0
- | (dqs_cfg << 26) /* Differential DQS */
- | (odt_cfg << 21) /* ODT */
- | (d_init << 4) /* D_INIT auto init DDR */
- );
-
- debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
-
-
-#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
- /*
- * Setup the clock control.
- * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
- * SDRAM_CLK_CNTL[5-7] = Clock Adjust
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- if (spd.mem_type == SPD_MEMTYPE_DDR)
- clk_adjust = 0x6;
- else
-#ifdef CONFIG_MPC8568
- /* Empirally setting clk_adjust */
- clk_adjust = 0x6;
-#else
- clk_adjust = 0x7;
-#endif
-
- ddr->sdram_clk_cntl = (0
- | 0x80000000
- | (clk_adjust << 23)
- );
- debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
-#endif
-
- /*
- * Figure out the settings for the sdram_cfg register.
- * Build up the entire register in 'sdram_cfg' before writing
- * since the write into the register will actually enable the
- * memory controller; all settings must be done before enabling.
- *
- * sdram_cfg[0] = 1 (ddr sdram logic enable)
- * sdram_cfg[1] = 1 (self-refresh-enable)
- * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
- * 010 DDR 1 SDRAM
- * 011 DDR 2 SDRAM
- */
- sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
- sdram_cfg = (0
- | (1 << 31) /* Enable */
- | (1 << 30) /* Self refresh */
- | (sdram_type << 24) /* SDRAM type */
- );
-
- /*
- * sdram_cfg[3] = RD_EN - registered DIMM enable
- * A value of 0x26 indicates micron registered DIMMS (micron.com)
- */
- if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) {
- sdram_cfg |= 0x10000000; /* RD_EN */
- }
-
-#if defined(CONFIG_DDR_ECC)
- /*
- * If the user wanted ECC (enabled via sdram_cfg[2])
- */
- if (spd.config == 0x02) {
- sdram_cfg |= 0x20000000; /* ECC_EN */
- }
-#endif
-
- /*
- * REV1 uses 1T timing.
- * REV2 may use 1T or 2T as configured by the user.
- */
- {
- uint pvr = get_pvr();
-
- if (pvr != PVR_85xx_REV1) {
-#if defined(CONFIG_DDR_2T_TIMING)
- /*
- * Enable 2T timing by setting sdram_cfg[16].
- */
- sdram_cfg |= 0x8000; /* 2T_EN */
-#endif
- }
- }
-
- /*
- * 200 painful micro-seconds must elapse between
- * the DDR clock setup and the DDR config enable.
- */
- udelay(200);
-
- /*
- * Go!
- */
- ddr->sdram_cfg = sdram_cfg;
-
- asm("sync;isync;msync");
- udelay(500);
-
- debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg);
-
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Poll until memory is initialized.
- * 512 Meg at 400 might hit this 200 times or so.
- */
- while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
- udelay(1000);
- }
-#endif
-
-
- /*
- * Figure out memory size in Megabytes.
- */
- memsize = n_ranks * rank_density / 0x100000;
-
- /*
- * Establish Local Access Window and TLB mappings for DDR memory.
- */
- memsize = setup_laws_and_tlbs(memsize);
- if (memsize == 0) {
- return 0;
- }
-
- return memsize * 1024 * 1024;
-}
-
-
-/*
- * Setup Local Access Window and TLB1 mappings for the requested
- * amount of memory. Returns the amount of memory actually mapped
- * (usually the original request size), or 0 on error.
- */
-
-static unsigned int
-setup_laws_and_tlbs(unsigned int memsize)
-{
- unsigned int tlb_size;
- unsigned int law_size;
- unsigned int ram_tlb_index;
- unsigned int ram_tlb_address;
-
- /*
- * Determine size of each TLB1 entry.
- */
- switch (memsize) {
- case 16:
- case 32:
- tlb_size = BOOKE_PAGESZ_16M;
- break;
- case 64:
- case 128:
- tlb_size = BOOKE_PAGESZ_64M;
- break;
- case 256:
- case 512:
- tlb_size = BOOKE_PAGESZ_256M;
- break;
- case 1024:
- case 2048:
- if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
- tlb_size = BOOKE_PAGESZ_1G;
- else
- tlb_size = BOOKE_PAGESZ_256M;
- break;
- default:
- puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
-
- /*
- * The memory was not able to be mapped.
- * Default to a small size.
- */
- tlb_size = BOOKE_PAGESZ_64M;
- memsize=64;
- break;
- }
-
- /*
- * Configure DDR TLB1 entries.
- * Starting at TLB1 8, use no more than 8 TLB1 entries.
- */
- ram_tlb_index = 8;
- ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
- while (ram_tlb_address < (memsize * 1024 * 1024)
- && ram_tlb_index < 16) {
- set_tlb(1, ram_tlb_address, ram_tlb_address,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, ram_tlb_index, tlb_size, 1);
-
- ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
- ram_tlb_index++;
- }
-
-
- /*
- * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
- */
- law_size = 19 + __ilog2(memsize);
-
- /*
- * Set up LAWBAR for all of DDR.
- */
-
-#ifdef CONFIG_FSL_LAW
- set_next_law(CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
-#endif
-
- /*
- * Confirm that the requested amount of memory was mapped.
- */
- return memsize;
-}
-
-#endif /* CONFIG_SPD_EEPROM */
-
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-
-/*
- * Initialize all of memory for ECC, then enable errors.
- */
-
-void
-ddr_enable_ecc(unsigned int dram_size)
-{
- uint *p = 0;
- uint i = 0;
- volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
-
- dma_init();
-
- for (*p = 0; p < (uint *)(8 * 1024); p++) {
- if (((unsigned int)p & 0x1f) == 0) {
- ppcDcbz((unsigned long) p);
- }
- *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
- if (((unsigned int)p & 0x1c) == 0x1c) {
- ppcDcbf((unsigned long) p);
- }
- }
-
- dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
- dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
- dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
- dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
- dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
- dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
- dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
- dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
- dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
- dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
-
- for (i = 1; i < dram_size / 0x800000; i++) {
- dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
- }
-
- /*
- * Enable errors for ECC.
- */
- debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
- ddr->err_disable = 0x00000000;
- asm("sync;isync;msync");
- debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
-}
-
-#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 699441b4..1cda1e3 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -110,6 +110,10 @@ int get_clocks (void)
#endif
gd->i2c2_clk = gd->i2c1_clk;
+#if defined(CONFIG_MPC8536)
+ gd->sdhc_clk = gd->bus_clk / 2;
+#endif
+
#if defined(CONFIG_CPM2)
gd->vco_out = 2*sys_info.freqSystemBus;
gd->cpm_clk = gd->vco_out / 2;
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 3d15d50..7ce7a14 100644
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -90,3 +90,67 @@ void init_tlbs(void)
return ;
}
+
+unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+{
+ unsigned int tlb_size;
+ unsigned int ram_tlb_index;
+ unsigned int ram_tlb_address;
+
+ /*
+ * Determine size of each TLB1 entry.
+ */
+ switch (memsize_in_meg) {
+ case 16:
+ case 32:
+ tlb_size = BOOKE_PAGESZ_16M;
+ break;
+ case 64:
+ case 128:
+ tlb_size = BOOKE_PAGESZ_64M;
+ break;
+ case 256:
+ case 512:
+ tlb_size = BOOKE_PAGESZ_256M;
+ break;
+ case 1024:
+ case 2048:
+ if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
+ tlb_size = BOOKE_PAGESZ_1G;
+ else
+ tlb_size = BOOKE_PAGESZ_256M;
+ break;
+ default:
+ puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G"
+ " and 2G are supported.\n");
+
+ /*
+ * The memory was not able to be mapped.
+ * Default to a small size.
+ */
+ tlb_size = BOOKE_PAGESZ_64M;
+ memsize_in_meg = 64;
+ break;
+ }
+
+ /*
+ * Configure DDR TLB1 entries.
+ * Starting at TLB1 8, use no more than 8 TLB1 entries.
+ */
+ ram_tlb_index = 8;
+ ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
+ while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
+ && ram_tlb_index < 16) {
+ set_tlb(1, ram_tlb_address, ram_tlb_address,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, ram_tlb_index, tlb_size, 1);
+
+ ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
+ ram_tlb_index++;
+ }
+
+ /*
+ * Confirm that the requested amount of memory was mapped.
+ */
+ return memsize_in_meg;
+}
generated by cgit v1.1 at 2024-12-02 08:48:32 +0000