diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm920t/at91rm9200/lowlevel_init.S | 6 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91cap9/spi.c | 119 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91sam9/Makefile (renamed from cpu/arm926ejs/at91cap9/Makefile) | 9 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91sam9/config.mk (renamed from cpu/arm926ejs/at91cap9/config.mk) | 0 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91sam9/ether.c (renamed from cpu/arm926ejs/at91cap9/ether.c) | 6 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91sam9/lowlevel_init.S (renamed from cpu/arm926ejs/at91cap9/lowlevel_init.S) | 2 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91sam9/spi.c | 157 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91sam9/timer.c (renamed from cpu/arm926ejs/at91cap9/timer.c) | 32 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91sam9/usb.c (renamed from cpu/arm926ejs/at91cap9/usb.c) | 12 | ||||
| -rw-r--r-- | cpu/arm926ejs/interrupts.c | 2 |
10 files changed, 193 insertions, 152 deletions
diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S index 1902bd0..98363eb 100644 --- a/cpu/arm920t/at91rm9200/lowlevel_init.S +++ b/cpu/arm920t/at91rm9200/lowlevel_init.S @@ -46,7 +46,7 @@ #define MC_ASR 0xFFFFFF04 #define MC_AASR 0xFFFFFF08 #define EBI_CFGR 0xFFFFFF64 -#define SMC2_CSR 0xFFFFFF70 +#define SMC_CSR0 0xFFFFFF70 /* clocks */ #define PLLAR 0xFFFFFC28 @@ -146,8 +146,8 @@ SMRDATA: .word MC_AASR_VAL .word EBI_CFGR .word EBI_CFGR_VAL - .word SMC2_CSR - .word SMC2_CSR_VAL + .word SMC_CSR0 + .word SMC_CSR0_VAL .word PLLAR .word PLLAR_VAL .word PLLBR diff --git a/cpu/arm926ejs/at91cap9/spi.c b/cpu/arm926ejs/at91cap9/spi.c deleted file mode 100644 index 0953820..0000000 --- a/cpu/arm926ejs/at91cap9/spi.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Driver for ATMEL DataFlash support - * Author : Hamid Ikdoumi (Atmel) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include <config.h> -#include <common.h> -#include <asm/hardware.h> - -#ifdef CONFIG_HAS_DATAFLASH -#include <dataflash.h> - -/* Max Value = 10MHz to be compliant to the Continuous Array Read function */ -#define AT91C_SPI_CLK 10000000 - -/* AC Characteristics: DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -#define DATAFLASH_TCSS (0xFA << 16) -#define DATAFLASH_TCHS (0x8 << 24) - -#define AT91C_TIMEOUT_WRDY 200000 -#define AT91C_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */ -#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ - -void AT91F_SpiInit(void) -{ - /* Reset the SPI */ - AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SWRST; - - /* Configure SPI in Master Mode with No CS selected !!! */ - AT91C_BASE_SPI0->SPI_MR = - AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; - - /* Configure CS0 */ - AT91C_BASE_SPI0->SPI_CSR[0] = - AT91C_SPI_CPOL | - (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | - (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); -} - -void AT91F_SpiEnable(int cs) -{ - switch (cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI0->SPI_MR |= - ((AT91C_SPI_PCS0_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - case 3: - AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI0->SPI_MR |= - ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - } - - /* SPI_Enable */ - AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SPIEN; -} - -unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) -{ - unsigned int timeout; - - pDesc->state = BUSY; - - AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - /* Initialize the Transmit and Receive Pointer */ - AT91C_BASE_SPI0->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt; - AT91C_BASE_SPI0->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt; - - /* Intialize the Transmit and Receive Counters */ - AT91C_BASE_SPI0->SPI_RCR = pDesc->rx_cmd_size; - AT91C_BASE_SPI0->SPI_TCR = pDesc->tx_cmd_size; - - if (pDesc->tx_data_size != 0) { - /* Initialize the Next Transmit and Next Receive Pointer */ - AT91C_BASE_SPI0->SPI_RNPR = (unsigned int)pDesc->rx_data_pt; - AT91C_BASE_SPI0->SPI_TNPR = (unsigned int)pDesc->tx_data_pt; - - /* Intialize the Next Transmit and Next Receive Counters */ - AT91C_BASE_SPI0->SPI_RNCR = pDesc->rx_data_size; - AT91C_BASE_SPI0->SPI_TNCR = pDesc->tx_data_size; - } - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - timeout = 0; - - AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; - while (!(AT91C_BASE_SPI0->SPI_SR & AT91C_SPI_RXBUFF) && - ((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT)); - AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - pDesc->state = IDLE; - - if (timeout >= CFG_SPI_WRITE_TOUT) { - printf("Error Timeout\n\r"); - return DATAFLASH_ERROR; - } - - return DATAFLASH_OK; -} -#endif diff --git a/cpu/arm926ejs/at91cap9/Makefile b/cpu/arm926ejs/at91sam9/Makefile index bf15e1e..203abc2 100644 --- a/cpu/arm926ejs/at91cap9/Makefile +++ b/cpu/arm926ejs/at91sam9/Makefile @@ -25,11 +25,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = ether.o timer.o spi.o usb.o +COBJS-y += ether.o +COBJS-y += timer.o +COBJS-$(CONFIG_HAS_DATAFLASH) +=spi.o +COBJS-y += usb.o SOBJS = lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) all: $(obj).depend $(LIB) diff --git a/cpu/arm926ejs/at91cap9/config.mk b/cpu/arm926ejs/at91sam9/config.mk index ca2cae1..ca2cae1 100644 --- a/cpu/arm926ejs/at91cap9/config.mk +++ b/cpu/arm926ejs/at91sam9/config.mk diff --git a/cpu/arm926ejs/at91cap9/ether.c b/cpu/arm926ejs/at91sam9/ether.c index b7958d5..e4f5601 100644 --- a/cpu/arm926ejs/at91cap9/ether.c +++ b/cpu/arm926ejs/at91sam9/ether.c @@ -23,13 +23,13 @@ */ #include <common.h> -#include <asm/arch/AT91CAP9.h> +#include <asm/arch/hardware.h> extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); #if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) -void at91cap9_eth_initialize(bd_t *bi) +void at91sam9_eth_initialize(bd_t *bi) { - macb_eth_initialize(0, (void *)AT91C_BASE_MACB, 0x00); + macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00); } #endif diff --git a/cpu/arm926ejs/at91cap9/lowlevel_init.S b/cpu/arm926ejs/at91sam9/lowlevel_init.S index 24d950c..40a3f6a 100644 --- a/cpu/arm926ejs/at91cap9/lowlevel_init.S +++ b/cpu/arm926ejs/at91sam9/lowlevel_init.S @@ -1,5 +1,5 @@ /* - * AT91CAP9 setup stuff + * AT91CAP9/SAM9 setup stuff * * (C) Copyright 2007-2008 * Stelian Pop <stelian.pop <at> leadtechdesign.com> diff --git a/cpu/arm926ejs/at91sam9/spi.c b/cpu/arm926ejs/at91sam9/spi.c new file mode 100644 index 0000000..c9fe6d8 --- /dev/null +++ b/cpu/arm926ejs/at91sam9/spi.c @@ -0,0 +1,157 @@ +/* + * Driver for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_spi.h> + +#include <dataflash.h> + +#define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */ +#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 0: NPCS0%1101 */ +#define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ + +void AT91F_SpiInit(void) +{ + /* Reset the SPI */ + writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR); + + /* Configure SPI in Master Mode with No CS selected !!! */ + writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS, + AT91_BASE_SPI + AT91_SPI_MR); + + /* Configure CS0 */ + writel(AT91_SPI_NCPHA | + (AT91_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), + AT91_BASE_SPI + AT91_SPI_CSR(0)); + +#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS1 + /* Configure CS1 */ + writel(AT91_SPI_NCPHA | + (AT91_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), + AT91_BASE_SPI + AT91_SPI_CSR(1)); +#endif + +#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS3 + /* Configure CS3 */ + writel(AT91_SPI_NCPHA | + (AT91_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), + AT91_BASE_SPI + AT91_SPI_CSR(3)); +#endif + + /* SPI_Enable */ + writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR); + + while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS)); + + /* + * Add tempo to get SPI in a safe state. + * Should not be needed for new silicon (Rev B) + */ + udelay(500000); + readl(AT91_BASE_SPI + AT91_SPI_SR); + readl(AT91_BASE_SPI + AT91_SPI_RDR); + +} + +void AT91F_SpiEnable(int cs) +{ + unsigned long mode; + + switch (cs) { + case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ + mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode &= 0xFFF0FFFF; + writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS), + AT91_BASE_SPI + AT91_SPI_MR); + break; + case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */ + mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode &= 0xFFF0FFFF; + writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS), + AT91_BASE_SPI + AT91_SPI_MR); + break; + case 3: + mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode &= 0xFFF0FFFF; + writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS), + AT91_BASE_SPI + AT91_SPI_MR); + break; + } + + /* SPI_Enable */ + writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR); +} + +unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc); + +unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) +{ + unsigned int timeout; + + pDesc->state = BUSY; + + writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR); + + /* Initialize the Transmit and Receive Pointer */ + writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR); + writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR); + + /* Intialize the Transmit and Receive Counters */ + writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR); + writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR); + + if (pDesc->tx_data_size != 0) { + /* Initialize the Next Transmit and Next Receive Pointer */ + writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR); + writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR); + + /* Intialize the Next Transmit and Next Receive Counters */ + writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR); + writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR); + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + timeout = 0; + + writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR); + while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) && + ((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT)); + writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR); + pDesc->state = IDLE; + + if (timeout >= CFG_SPI_WRITE_TOUT) { + printf("Error Timeout\n\r"); + return DATAFLASH_ERROR; + } + + return DATAFLASH_OK; +} diff --git a/cpu/arm926ejs/at91cap9/timer.c b/cpu/arm926ejs/at91sam9/timer.c index 4110e15..4e79466 100644 --- a/cpu/arm926ejs/at91cap9/timer.c +++ b/cpu/arm926ejs/at91sam9/timer.c @@ -24,36 +24,35 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch/at91_pit.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/io.h> /* - * We're using the AT91CAP9 PITC in 32 bit mode, by + * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by * setting the 20 bit counter period to its maximum (0xfffff). */ #define TIMER_LOAD_VAL 0xfffff -#define READ_RESET_TIMER (AT91C_BASE_PITC->PITC_PIVR) -#define READ_TIMER (AT91C_BASE_PITC->PITC_PIIR) +#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR) +#define READ_TIMER at91_sys_read(AT91_PIT_PIIR) #define TIMER_FREQ (AT91C_MASTER_CLOCK << 4) #define TICKS_TO_USEC(ticks) ((ticks) / 6) ulong get_timer_masked(void); ulong resettime; -AT91PS_PITC p_pitc; - /* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init(void) +int timer_init(void) { /* * Enable PITC Clock * The clock is already enabled for system controller in boot */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS; + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); /* Enable PITC */ - AT91C_BASE_PITC->PITC_PIMR = AT91C_PITC_PITEN; - - /* Load PITC_PIMR with the right timer value */ - AT91C_BASE_PITC->PITC_PIMR |= TIMER_LOAD_VAL; + at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN); reset_timer_masked(); @@ -67,6 +66,7 @@ int interrupt_init(void) static inline ulong get_timer_raw(void) { ulong now = READ_TIMER; + if (now >= resettime) return now - resettime; else @@ -129,20 +129,20 @@ unsigned long long get_ticks(void) ulong get_tbclk(void) { ulong tbclk; + tbclk = CFG_HZ; return tbclk; } /* - * Reset the cpu by setting up the watchdog timer and let him time out - * on the AT91CAP9ADK board + * Reset the cpu by setting up the watchdog timer and let him time out. */ void reset_cpu(ulong ignored) { /* this is the way Linux does it */ - AT91C_BASE_RSTC->RSTC_RCR = (0xA5 << 24) | - AT91C_RSTC_PROCRST | - AT91C_RSTC_PERRST; + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_PERRST); while (1); /* Never reached */ diff --git a/cpu/arm926ejs/at91cap9/usb.c b/cpu/arm926ejs/at91sam9/usb.c index 69da5f3..d678897 100644 --- a/cpu/arm926ejs/at91cap9/usb.c +++ b/cpu/arm926ejs/at91sam9/usb.c @@ -24,15 +24,16 @@ #include <common.h> #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) -#ifdef CONFIG_AT91CAP9 #include <asm/arch/hardware.h> +#include <asm/arch/io.h> +#include <asm/arch/at91_pmc.h> int usb_cpu_init(void) { /* Enable USB host clock. */ - AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UHP; - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_UHP; + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP); + at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP); return 0; } @@ -40,8 +41,8 @@ int usb_cpu_init(void) int usb_cpu_stop(void) { /* Disable USB host clock. */ - AT91C_BASE_PMC->PMC_PCDR = 1 << AT91C_ID_UHP; - AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_UHP; + at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP); + at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP); return 0; } @@ -50,5 +51,4 @@ int usb_cpu_init_fail(void) return usb_cpu_stop(); } -#endif /* CONFIG_AT91CAP9 */ #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c index 0971fea..1819f6b 100644 --- a/cpu/arm926ejs/interrupts.c +++ b/cpu/arm926ejs/interrupts.c @@ -38,7 +38,7 @@ #include <common.h> #include <arm926ejs.h> -#if defined(CONFIG_INTEGRATOR) || defined(CONFIG_AT91CAP9ADK) +#ifdef CONFIG_INTEGRATOR /* Timer functionality supplied by Integrator board (AP or CP) */ |