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-rw-r--r--cpu/mpc5xxx/cpu_init.c2
-rw-r--r--cpu/mpc5xxx/fec.c7
-rw-r--r--cpu/mpc8260/cpu.c9
-rw-r--r--cpu/mpc8260/cpu_init.c28
-rw-r--r--cpu/mpc8260/pci.c19
-rw-r--r--cpu/mpc8260/speed.c8
-rw-r--r--cpu/mpc8xx/serial.c13
-rw-r--r--cpu/ppc4xx/405gp_pci.c2
-rw-r--r--cpu/ppc4xx/440spe_pcie.c8
-rw-r--r--cpu/ppc4xx/4xx_enet.c139
-rw-r--r--cpu/ppc4xx/cpu.c30
-rw-r--r--cpu/ppc4xx/cpu_init.c13
-rw-r--r--cpu/ppc4xx/ndfc.c3
-rw-r--r--cpu/ppc4xx/sdram.c35
14 files changed, 219 insertions, 97 deletions
diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index b7e00b3..7e65821 100644
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -123,7 +123,7 @@ void cpu_init_f (void)
#endif
#if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
- *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START);
+ *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START);
*(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
addecr |= (1 << 27);
#endif
diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index 37fe3e7..71c1bfa 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -376,7 +376,7 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
- mpc5xxx_fec_phydump ();
+ mpc5xxx_fec_phydump (dev->name);
#endif
/*
@@ -575,7 +575,7 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
- mpc5xxx_fec_phydump ();
+ mpc5xxx_fec_phydump (dev->name);
#endif
/*
@@ -882,7 +882,8 @@ int mpc5xxx_fec_initialize(bd_t * bis)
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \
defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
- defined(CONFIG_TQM5200) || defined(CONFIG_V38B)
+ defined(CONFIG_TQM5200) || defined(CONFIG_V38B) || \
+ defined(CONFIG_UC101)
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
# else
diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c
index 4f23012..94651dc 100644
--- a/cpu/mpc8260/cpu.c
+++ b/cpu/mpc8260/cpu.c
@@ -49,6 +49,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_GET_CPU_STR_F)
+extern int get_cpu_str_f (char *buf);
+#endif
+
int checkcpu (void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
@@ -81,7 +85,12 @@ int checkcpu (void)
if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
return -1; /* whoops! someone moved the IMMR */
+#if defined(CONFIG_GET_CPU_STR_F)
+ get_cpu_str_f (buf);
+ printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
+#else
printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
+#endif
/*
* the bottom 16 bits of the immr are the Part Number and Mask Number
diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c
index 640026b..7dcc949 100644
--- a/cpu/mpc8260/cpu_init.c
+++ b/cpu/mpc8260/cpu_init.c
@@ -28,6 +28,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+extern unsigned long board_get_cpu_clk_f (void);
+#endif
+
static void config_8260_ioports (volatile immap_t * immr)
{
int portnum;
@@ -90,6 +94,7 @@ static void config_8260_ioports (volatile immap_t * immr)
}
}
+#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
/*
* Breath some life into the CPU...
*
@@ -102,6 +107,9 @@ void cpu_init_f (volatile immap_t * immr)
#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
uint sccr;
#endif
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+ unsigned long cpu_clk;
+#endif
volatile memctl8260_t *memctl = &immr->im_memctl;
extern void m8260_cpm_reset (void);
@@ -119,10 +127,27 @@ void cpu_init_f (volatile immap_t * immr)
immr->im_clkrst.car_rmr = CFG_RMR;
/* BCR - Bus Configuration Register (4-25) */
+#if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE)
+ if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
+ immr->im_siu_conf.sc_bcr = CFG_BCR_60x;
+ } else {
+ immr->im_siu_conf.sc_bcr = CFG_BCR_SINGLE;
+ }
+#else
immr->im_siu_conf.sc_bcr = CFG_BCR;
+#endif
/* SIUMCR - contains debug pin configuration (4-31) */
+#if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH)
+ cpu_clk = board_get_cpu_clk_f ();
+ if (cpu_clk >= 100000000) {
+ immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_HIGH;
+ } else {
+ immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_LOW;
+ }
+#else
immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
+#endif
config_8260_ioports (immr);
@@ -157,7 +182,8 @@ void cpu_init_f (volatile immap_t * immr)
#endif
/* now restrict to preliminary range */
- memctl->memc_br0 = CFG_BR0_PRELIM;
+ /* the PS came from the HRCW, don´t change it */
+ memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK);
memctl->memc_or0 = CFG_OR0_PRELIM;
#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index b14fc15..1edd6fb 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -274,7 +274,23 @@ void pci_mpc8250_init (struct pci_controller *hose)
| SIUMCR_CS10PC00
| SIUMCR_BCTLC00
| SIUMCR_MMR11;
-
+#elif defined(CONFIG_TQM8272)
+#if 0
+ immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_CS10PC11 &
+ ~SIUMCR_LBPC11) |
+ SIUMCR_LBPC01 |
+ SIUMCR_CS10PC01 |
+ SIUMCR_APPC10;
+#else
+#if 0
+ immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr |
+ SIUMCR_APPC10);
+#else
+ immap->im_siu_conf.sc_siumcr = 0x88000000;
+#endif
+#endif
#else
/*
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
@@ -288,6 +304,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
SIUMCR_CS10PC01 |
SIUMCR_APPC10;
#endif
+printf("%s siumcr: %x\n", __FUNCTION__, immap->im_siu_conf.sc_siumcr);
/* Make PCI lowest priority */
/* Each 4 bits is a device bus request and the MS 4bits
diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c
index 360404f..38cd0d9 100644
--- a/cpu/mpc8260/speed.c
+++ b/cpu/mpc8260/speed.c
@@ -25,6 +25,10 @@
#include <mpc8260.h>
#include <asm/processor.h>
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+extern unsigned long board_get_cpu_clk_f (void);
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
@@ -112,8 +116,12 @@ int get_clocks (void)
#if !defined(CONFIG_8260_CLKIN)
#error clock measuring not implemented yet - define CONFIG_8260_CLKIN
#else
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+ clkin = board_get_cpu_clk_f ();
+#else
clkin = CONFIG_8260_CLKIN;
#endif
+#endif
sccr = immap->im_clkrst.car_sccr;
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c
index 8ae584f..9d0fc6b 100644
--- a/cpu/mpc8xx/serial.c
+++ b/cpu/mpc8xx/serial.c
@@ -227,8 +227,17 @@ static int smc_init (void)
sp->smc_smcm = 0;
sp->smc_smce = 0xff;
-#ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */
- *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff;
+#ifdef CFG_SPC1920_SMC1_CLK4
+ /* clock source is PLD */
+
+ /* set freq to 19200 Baud */
+ *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0x3;
+ /* configure clk4 as input */
+ im->im_ioport.iop_pdpar |= 0x800;
+ im->im_ioport.iop_pddir &= ~0x800;
+
+ cp->cp_simode = 0x0000;
+ cp->cp_simode |= 0x7000;
#else
/* Set up the baud rate generator */
smc_setbrg ();
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 9b711e2..7134355 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -380,7 +380,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
}
-#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
+#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SOLIDCARD3))
/*
*As is these functs get called out of flash Not a horrible
diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c
index 6130cd2..d6c4be5 100644
--- a/cpu/ppc4xx/440spe_pcie.c
+++ b/cpu/ppc4xx/440spe_pcie.c
@@ -26,10 +26,9 @@
#include <common.h>
#include <pci.h>
-#include "440spe_pcie.h"
+#if defined(CONFIG_440SPE) && defined(CONFIG_PCI)
-#if defined(CONFIG_440SPE)
-#if defined(CONFIG_PCI)
+#include "440spe_pcie.h"
enum {
PTYPE_ENDPOINT = 0x0,
@@ -958,5 +957,4 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
return 0;
}
-#endif /* CONFIG_PCI */
-#endif /* CONFIG_440SPE */
+#endif /* CONFIG_440SPE && CONFIG_PCI */
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 427ea94..4f55583 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -166,6 +166,11 @@ struct eth_device *emac0_dev = NULL;
#define LAST_EMAC_NUM 1
#endif
+/* normal boards start with EMAC0 */
+#if !defined(CONFIG_EMAC_NR_START)
+#define CONFIG_EMAC_NR_START 0
+#endif
+
/*-----------------------------------------------------------------------------+
* Prototypes and externals.
*-----------------------------------------------------------------------------*/
@@ -601,6 +606,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/* end Vitesse/Cicada errata */
}
#endif
+
+#if defined(CONFIG_ET1011C_PHY)
+ /*
+ * Agere ET1011c PHY needs to have an extended register whacked
+ * for RGMII mode.
+ */
+ if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
+ miiphy_read (dev->name, reg, 0x16, &reg_short);
+ reg_short &= ~(0x7);
+ reg_short |= 0x6; /* RGMII DLL Delay*/
+ miiphy_write (dev->name, reg, 0x16, reg_short);
+
+ miiphy_read (dev->name, reg, 0x17, &reg_short);
+ reg_short &= ~(0x40);
+ miiphy_write (dev->name, reg, 0x17, reg_short);
+
+ miiphy_write(dev->name, reg, 0x1c, 0x74f0);
+ }
+#endif
+
#endif
/* Start/Restart autonegotiation */
phy_setup_aneg (dev->name, reg);
@@ -643,8 +668,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
if (hw_p->print_speed) {
hw_p->print_speed = 0;
- printf ("ENET Speed is %d Mbps - %s duplex connection\n",
- (int) speed, (duplex == HALF) ? "HALF" : "FULL");
+ printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
+ (int) speed, (duplex == HALF) ? "HALF" : "FULL",
+ hw_p->devnum);
}
#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
@@ -1493,6 +1519,8 @@ int ppc_4xx_eth_initialize (bd_t * bis)
struct eth_device *dev;
int eth_num = 0;
EMAC_4XX_HW_PST hw = NULL;
+ u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
+ u32 hw_addr[4];
#if defined(CONFIG_440GX)
unsigned long pfc1;
@@ -1502,59 +1530,69 @@ int ppc_4xx_eth_initialize (bd_t * bis)
pfc1 |= 0x01200000;
mtsdr (sdr_pfc1, pfc1);
#endif
- /* set phy num and mode */
- bis->bi_phynum[0] = CONFIG_PHY_ADDR;
- bis->bi_phymode[0] = 0;
-#if defined(CONFIG_PHY1_ADDR)
- bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
- bis->bi_phymode[1] = 0;
-#endif
-#if defined(CONFIG_440GX)
- bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
- bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
- bis->bi_phymode[2] = 2;
- bis->bi_phymode[3] = 2;
-
- ppc_4xx_eth_setup_bridge(0, bis);
-#endif
+ /* first clear all mac-addresses */
+ for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
+ memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
-
- /* See if we can actually bring up the interface, otherwise, skip it */
switch (eth_num) {
default: /* fall through */
case 0:
- if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
- bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
- continue;
- }
+ memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+ bis->bi_enetaddr, 6);
+ hw_addr[eth_num] = 0x0;
break;
#ifdef CONFIG_HAS_ETH1
case 1:
- if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
- bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
- continue;
- }
+ memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+ bis->bi_enet1addr, 6);
+ hw_addr[eth_num] = 0x100;
break;
#endif
#ifdef CONFIG_HAS_ETH2
case 2:
- if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
- bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
- continue;
- }
+ memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+ bis->bi_enet2addr, 6);
+ hw_addr[eth_num] = 0x400;
break;
#endif
#ifdef CONFIG_HAS_ETH3
case 3:
- if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
- bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
- continue;
- }
+ memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+ bis->bi_enet3addr, 6);
+ hw_addr[eth_num] = 0x600;
break;
#endif
}
+ }
+
+ /* set phy num and mode */
+ bis->bi_phynum[0] = CONFIG_PHY_ADDR;
+ bis->bi_phymode[0] = 0;
+
+#if defined(CONFIG_PHY1_ADDR)
+ bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
+ bis->bi_phymode[1] = 0;
+#endif
+#if defined(CONFIG_440GX)
+ bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
+ bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
+ bis->bi_phymode[2] = 2;
+ bis->bi_phymode[3] = 2;
+
+ ppc_4xx_eth_setup_bridge(0, bis);
+#endif
+
+ for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
+ /*
+ * See if we can actually bring up the interface,
+ * otherwise, skip it
+ */
+ if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
+ bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
+ continue;
+ }
/* Allocate device structure */
dev = (struct eth_device *) malloc (sizeof (*dev));
@@ -1576,36 +1614,12 @@ int ppc_4xx_eth_initialize (bd_t * bis)
}
memset(hw, 0, sizeof(*hw));
- switch (eth_num) {
- default: /* fall through */
- case 0:
- hw->hw_addr = 0;
- memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
- break;
-#ifdef CONFIG_HAS_ETH1
- case 1:
- hw->hw_addr = 0x100;
- memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
- break;
-#endif
-#ifdef CONFIG_HAS_ETH2
- case 2:
- hw->hw_addr = 0x400;
- memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
- break;
-#endif
-#ifdef CONFIG_HAS_ETH3
- case 3:
- hw->hw_addr = 0x600;
- memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
- break;
-#endif
- }
-
+ hw->hw_addr = hw_addr[eth_num];
+ memcpy (dev->enetaddr, ethaddr[eth_num], 6);
hw->devnum = eth_num;
hw->print_speed = 1;
- sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
+ sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
dev->priv = (void *) hw;
dev->init = ppc_4xx_eth_init;
dev->halt = ppc_4xx_eth_halt;
@@ -1663,7 +1677,6 @@ int ppc_4xx_eth_initialize (bd_t * bis)
return (1);
}
-
#if !defined(CONFIG_NET_MULTI)
void eth_halt (void) {
if (emac0_dev) {
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 9c5c910..57a7e8d 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -332,24 +332,44 @@ int checkcpu (void)
strcpy(addstr, "No Security/Kasumi support");
break;
- case PVR_440SP_RA:
- puts("SP Rev. A");
+ case PVR_440SP_6_RAB:
+ puts("SP Rev. A/B");
+ strcpy(addstr, "RAID 6 support");
break;
- case PVR_440SP_RB:
- puts("SP Rev. B");
+ case PVR_440SP_RAB:
+ puts("SP Rev. A/B");
+ strcpy(addstr, "No RAID 6 support");
+ break;
+
+ case PVR_440SP_6_RC:
+ puts("SP Rev. C");
+ strcpy(addstr, "RAID 6 support");
break;
case PVR_440SP_RC:
puts("SP Rev. C");
+ strcpy(addstr, "No RAID 6 support");
+ break;
+
+ case PVR_440SPe_6_RA:
+ puts("SPe Rev. A");
+ strcpy(addstr, "RAID 6 support");
break;
case PVR_440SPe_RA:
puts("SPe Rev. A");
+ strcpy(addstr, "No RAID 6 support");
+ break;
+
+ case PVR_440SPe_6_RB:
+ puts("SPe Rev. B");
+ strcpy(addstr, "RAID 6 support");
break;
case PVR_440SPe_RB:
puts("SPe Rev. B");
+ strcpy(addstr, "No RAID 6 support");
break;
default:
@@ -419,7 +439,7 @@ int ppc440spe_revB() {
unsigned int pvr;
pvr = get_pvr();
- if (pvr == PVR_440SPe_RB)
+ if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
return 1;
else
return 0;
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 4b746b0..ae24591 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -31,9 +31,6 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
-
-#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
-
#ifdef CFG_INIT_DCACHE_CS
# if (CFG_INIT_DCACHE_CS == 0)
# define PBxAP pb0ap
@@ -222,6 +219,10 @@ void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_M
void
cpu_init_f (void)
{
+#if defined(CONFIG_WATCHDOG)
+ unsigned long val;
+#endif
+
#if defined(CONFIG_405EP)
/*
* GPIO0 setup (select GPIO or alternate function)
@@ -312,9 +313,11 @@ cpu_init_f (void)
mtebc(pb7cr, CFG_EBC_PB7CR);
#endif
-#if defined(CONFIG_WATCHDOG)
- unsigned long val;
+#if defined (CFG_EBC_CFG)
+ mtebc(epcr, CFG_EBC_CFG);
+#endif
+#if defined(CONFIG_WATCHDOG)
val = mfspr(tcr);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index 3521731..b198ff4 100644
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -156,7 +156,7 @@ void board_nand_select_device(struct nand_chip *nand, int chip)
out32(base + NDFC_CCR, 0x00000000 | (cs << 24));
}
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
{
int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
@@ -188,6 +188,7 @@ void board_nand_init(struct nand_chip *nand)
*/
board_nand_select_device(nand, cs);
out32(base + NDFC_BCFG0 + (cs << 2), 0x80002222);
+ return 0;
}
#endif
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index f06038e..d520cd3 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2005-2006
+ * (C) Copyright 2005-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
@@ -32,9 +32,9 @@
#include <asm/processor.h>
#include "sdram.h"
-
#ifdef CONFIG_SDRAM_BANK0
+#ifndef CONFIG_440
#ifndef CFG_SDRAM_TABLE
sdram_conf_t mb0cf[] = {
@@ -50,9 +50,6 @@ sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
-
-#ifndef CONFIG_440
-
#ifdef CFG_SDRAM_CASL
static ulong ns2clks(ulong ns)
{
@@ -221,6 +218,26 @@ void sdram_init(void)
#else /* CONFIG_440 */
+/*
+ * Define some default values. Those can be overwritten in the
+ * board config file.
+ */
+
+#ifndef CFG_SDRAM_TABLE
+sdram_conf_t mb0cf[] = {
+ {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */
+ {(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */
+};
+#else
+sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
+#endif
+
+#ifndef CFG_SDRAM0_TR0
+#define CFG_SDRAM0_TR0 0x41094012
+#endif
+
+#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+
#define NUM_TRIES 64
#define NUM_READS 10
@@ -295,7 +312,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
*tr1_value = (first_good + last_bad) / 2;
}
-
#ifdef CONFIG_SDRAM_ECC
static void ecc_init(ulong start, ulong size)
{
@@ -351,7 +367,8 @@ long int initdram(int board_type)
int i;
int tr1_bank1;
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440SP)
/*
* Soft-reset SDRAM controller.
*/
@@ -378,9 +395,9 @@ long int initdram(int board_type)
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, mb0cf[i].reg);
- mtsdram(mem_tr0, 0x41094012);
+ mtsdram(mem_tr0, CFG_SDRAM0_TR0);
mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
- mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20µs @ 133MHz PLB*/
+ mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
udelay(400); /* Delay 200 usecs (min) */
generated by cgit v1.1 at 2024-11-28 04:45:53 +0000