23 files changed, 389 insertions, 831 deletions

diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c
index 2c0014f..befa0cd 100644
--- a/cpu/arm1176/cpu.c
+++ b/cpu/arm1176/cpu.c
@@ -33,7 +33,9 @@
 
 #include <common.h>
 #include <command.h>
+#ifdef CONFIG_S3C64XX
 #include <asm/arch/s3c6400.h>
+#endif
 #include <asm/system.h>
 
 static void cache_flush (void);
diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S
index 68a356d..e2b6c9b 100644
--- a/cpu/arm1176/start.S
+++ b/cpu/arm1176/start.S
@@ -35,7 +35,9 @@
 #ifdef CONFIG_ENABLE_MMU
 #include <asm/proc/domain.h>
 #endif
+#ifdef CONFIG_S3C64XX
 #include <asm/arch/s3c6400.h>
+#endif
 
 #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
 #define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
@@ -190,10 +192,12 @@ mmu_disable:
 #endif
 
 mmu_disable_phys:
+#ifdef CONFIG_S3C64XX
 	/* Peri port setup */
 	ldr	r0, =0x70000000
 	orr	r0, r0, #0x13
 	mcr	p15,0,r0,c15,c2,4       @ 256M (0x70000000 - 0x7fffffff)
+#endif
 
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c
index 31304b7..4a0ce4d 100644
--- a/cpu/arm920t/ep93xx/timer.c
+++ b/cpu/arm920t/ep93xx/timer.c
@@ -1,8 +1,7 @@
 /*
  * Cirrus Logic EP93xx timer support.
  *
- * Copyright (C) 2009, 2010
- * Matthias Kaehlcke <matthias@kaehlcke.net>
+ * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
  *
  * Copyright (C) 2004, 2005
  * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
@@ -42,17 +41,9 @@
 static struct ep93xx_timer
 {
 	unsigned long long ticks;
-	unsigned long last_update;
+	unsigned long last_read;
 } timer;
 
-static inline unsigned long clk_to_systicks(unsigned long long clk_ticks)
-{
-	unsigned long long sys_ticks = (clk_ticks * CONFIG_SYS_HZ);
-	do_div(sys_ticks, TIMER_FREQ);
-
-	return (unsigned long)sys_ticks;
-}
-
 static inline unsigned long long usecs_to_ticks(unsigned long usecs)
 {
 	unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
@@ -61,11 +52,18 @@ static inline unsigned long long usecs_to_ticks(unsigned long usecs)
 	return ticks;
 }
 
-static inline unsigned long read_timer(void)
+static inline void read_timer(void)
 {
-	struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
+	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+	const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
+
+	if (now >= timer.last_read)
+		timer.ticks += now - timer.last_read;
+	else
+		/* an overflow occurred */
+		timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
 
-	return TIMER_MAX_VAL - readl(&timer->timer3.value);
+	timer.last_read = now;
 }
 
 /*
@@ -73,17 +71,14 @@ static inline unsigned long read_timer(void)
  */
 unsigned long long get_ticks(void)
 {
-	const unsigned long now = read_timer();
+	unsigned long long sys_ticks;
 
-	if (now >= timer.last_update)
-		timer.ticks += now - timer.last_update;
-	else
-		/* an overflow occurred */
-		timer.ticks += TIMER_MAX_VAL - timer.last_update + now;
+	read_timer();
 
-	timer.last_update = now;
+	sys_ticks = timer.ticks * CONFIG_SYS_HZ;
+	do_div(sys_ticks, TIMER_FREQ);
 
-	return clk_to_systicks(timer.ticks);
+	return sys_ticks;
 }
 
 unsigned long get_timer_masked(void)
@@ -98,7 +93,7 @@ unsigned long get_timer(unsigned long base)
 
 void reset_timer_masked(void)
 {
-	timer.last_update = read_timer();
+	read_timer();
 	timer.ticks = 0;
 }
 
@@ -109,28 +104,29 @@ void reset_timer(void)
 
 void __udelay(unsigned long usec)
 {
-	/* read the timer and update timer.ticks */
-	get_ticks();
+	unsigned long long target;
+
+	read_timer();
 
-	const unsigned long long target = timer.ticks + usecs_to_ticks(usec);
+	target = timer.ticks + usecs_to_ticks(usec);
 
 	while (timer.ticks < target)
-		get_ticks();
+		read_timer();
 }
 
 int timer_init(void)
 {
-	struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
+	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
 
-	/* use timer 3 with 508KHz and free running */
-	writel(TIMER_CLKSEL, &timer->timer3.control);
+	/* use timer 3 with 508KHz and free running, not enabled now */
+	writel(TIMER_CLKSEL, &timer_regs->timer3.control);
 
-	/* set initial timer value 3 */
-	writel(TIMER_MAX_VAL, &timer->timer3.load);
+	/* set initial timer value */
+	writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
 
 	/* Enable the timer */
 	writel(TIMER_ENABLE | TIMER_CLKSEL,
-		&timer->timer3.control);
+		&timer_regs->timer3.control);
 
 	reset_timer_masked();
 
diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c
index b06d760..ecf91f5 100644
--- a/cpu/arm926ejs/at91/clock.c
+++ b/cpu/arm926ejs/at91/clock.c
@@ -203,7 +203,8 @@ int at91_clock_init(unsigned long main_clock)
 	if (mckr & AT91_PMC_MCKR_MDIV_MASK)
 		freq /= 2;			/* processor clock division */
 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
-	mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3
+	mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+		(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
 		? freq / 3
 		: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #else
diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c
index 047b9e3..1d98ef3 100644
--- a/cpu/arm926ejs/nomadik/timer.c
+++ b/cpu/arm926ejs/nomadik/timer.c
@@ -34,8 +34,8 @@
 #define TICKS_PER_HZ		(TIMER_CLOCK / CONFIG_SYS_HZ)
 #define TICKS_TO_HZ(x)		((x) / TICKS_PER_HZ)
 
-/* macro to read the 32 bit timer: since it decrements, we invert read value */
-#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
+/* macro to read the decrementing 32 bit timer as an increasing count */
+#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
 
 /* Configure a free-running, auto-wrap counter with no prescaler */
 int timer_init(void)
@@ -49,7 +49,16 @@ int timer_init(void)
 /* Restart counting from 0 */
 void reset_timer(void)
 {
-	writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */
+	ulong val;
+	writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
+	/*
+	 * The load-register isn't really immediate: it changes on clock
+	 * edges, so we must wait for our newly-written value to appear.
+	 * Since we might miss reading 0, wait for any change in value.
+	 */
+	val = READ_TIMER();
+	while (READ_TIMER() == val)
+		;
 }
 
 /* Return how many HZ passed since "base" */
diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile
index 4f922e6..01c93fe 100644
--- a/cpu/arm_cortexa8/s5pc1xx/Makefile
+++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
@@ -33,6 +33,8 @@ SOBJS	+= reset.o
 
 COBJS	+= clock.o
 COBJS	+= cpu_info.o
+COBJS	+= gpio.o
+COBJS	+= sromc.o
 COBJS	+= timer.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/cpu/arm_cortexa8/s5pc1xx/clock.c
index a9e78dd..19619f9 100644
--- a/cpu/arm_cortexa8/s5pc1xx/clock.c
+++ b/cpu/arm_cortexa8/s5pc1xx/clock.c
@@ -25,12 +25,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-
-#define APLL	0
-#define MPLL	1
-#define EPLL	2
-#define HPLL	3
-#define VPLL	4
+#include <asm/arch/clk.h>
 
 #define CLK_M	0
 #define CLK_D	1
diff --git a/cpu/arm_cortexa8/s5pc1xx/gpio.c b/cpu/arm_cortexa8/s5pc1xx/gpio.c
new file mode 100644
index 0000000..a97244b
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/gpio.c
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+#define CON_MASK(x)		(0xf << ((x) << 2))
+#define CON_SFR(x, v)		((v) << ((x) << 2))
+
+#define DAT_MASK(x)		(0x1 << (x))
+#define DAT_SET(x)		(0x1 << (x))
+
+#define PULL_MASK(x)		(0x3 << ((x) << 1))
+#define PULL_MODE(x, v)		((v) << ((x) << 1))
+
+#define DRV_MASK(x)		(0x3 << ((x) << 1))
+#define DRV_SET(x, m)		((m) << ((x) << 1))
+#define RATE_MASK(x)		(0x1 << (x + 16))
+#define RATE_SET(x)		(0x1 << (x + 16))
+
+void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg)
+{
+	unsigned int value;
+
+	value = readl(&bank->con);
+	value &= ~CON_MASK(gpio);
+	value |= CON_SFR(gpio, cfg);
+	writel(value, &bank->con);
+}
+
+void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en)
+{
+	unsigned int value;
+
+	gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
+
+	value = readl(&bank->dat);
+	value &= ~DAT_MASK(gpio);
+	if (en)
+		value |= DAT_SET(gpio);
+	writel(value, &bank->dat);
+}
+
+void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio)
+{
+	gpio_cfg_pin(bank, gpio, GPIO_INPUT);
+}
+
+void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en)
+{
+	unsigned int value;
+
+	value = readl(&bank->dat);
+	value &= ~DAT_MASK(gpio);
+	if (en)
+		value |= DAT_SET(gpio);
+	writel(value, &bank->dat);
+}
+
+unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio)
+{
+	unsigned int value;
+
+	value = readl(&bank->dat);
+	return !!(value & DAT_MASK(gpio));
+}
+
+void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+	unsigned int value;
+
+	value = readl(&bank->pull);
+	value &= ~PULL_MASK(gpio);
+
+	switch (mode) {
+	case GPIO_PULL_DOWN:
+	case GPIO_PULL_UP:
+		value |= PULL_MODE(gpio, mode);
+		break;
+	default:
+		return;
+	}
+
+	writel(value, &bank->pull);
+}
+
+void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+	unsigned int value;
+
+	value = readl(&bank->drv);
+	value &= ~DRV_MASK(gpio);
+
+	switch (mode) {
+	case GPIO_DRV_1X:
+	case GPIO_DRV_2X:
+	case GPIO_DRV_3X:
+	case GPIO_DRV_4X:
+		value |= DRV_SET(gpio, mode);
+		break;
+	default:
+		return;
+	}
+
+	writel(value, &bank->drv);
+}
+
+void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+	unsigned int value;
+
+	value = readl(&bank->drv);
+	value &= ~RATE_MASK(gpio);
+
+	switch (mode) {
+	case GPIO_DRV_FAST:
+	case GPIO_DRV_SLOW:
+		value |= RATE_SET(gpio);
+		break;
+	default:
+		return;
+	}
+
+	writel(value, &bank->drv);
+}
diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c b/cpu/arm_cortexa8/s5pc1xx/sromc.c
new file mode 100644
index 0000000..380be81
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/smc.h>
+
+/*
+ * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
+ * 		    band width control and bank control registers
+ * srom_bank	- SROM Bank 0 to 5
+ * smc_bw_conf  - SMC Band witdh reg configuration value
+ * smc_bc_conf  - SMC Bank Control reg configuration value
+ */
+void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
+{
+	u32 tmp;
+	struct s5pc1xx_smc *srom;
+
+	if (cpu_is_s5pc100())
+		srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE;
+	else
+		srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE;
+
+	/* Configure SMC_BW register to handle proper SROMC bank */
+	tmp = srom->bw;
+	tmp &= ~(0xF << (srom_bank * 4));
+	tmp |= smc_bw_conf;
+	srom->bw = tmp;
+
+	/* Configure SMC_BC register */
+	srom->bc[srom_bank] = smc_bc_conf;
+}
diff --git a/cpu/mpc512x/diu.c b/cpu/mpc512x/diu.c
index ca459a1..c2453c6 100644
--- a/cpu/mpc512x/diu.c
+++ b/cpu/mpc512x/diu.c
@@ -27,7 +27,6 @@
 #include <command.h>
 #include <asm/io.h>
 
-#include "../../board/freescale/common/pixis.h"
 #include "../../board/freescale/common/fsl_diu_fb.h"
 
 #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index 56de7eb..f064fee 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -50,7 +50,11 @@ COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
 COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
 COBJS-$(CONFIG_MPC8569)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1011)	+= ddr-gen3.o
+COBJS-$(CONFIG_P1012)	+= ddr-gen3.o
+COBJS-$(CONFIG_P1013)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1020)	+= ddr-gen3.o
+COBJS-$(CONFIG_P1021)	+= ddr-gen3.o
+COBJS-$(CONFIG_P1022)	+= ddr-gen3.o
 COBJS-$(CONFIG_P2010)	+= ddr-gen3.o
 COBJS-$(CONFIG_P2020)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index dab784e..0b5b9da 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  * Kumar Gala <kumar.gala@freescale.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -57,11 +57,19 @@ __secondary_start_page:
 
 #ifndef CONFIG_E500MC
 	li	r3,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
+	mfspr   r0,PVR
+	andi.	r0,r0,0xff
+	cmpwi	r0,0x50@l	/* if we are rev 5.0 or greater set MBDD */
+	blt 1f
+	/* Set MBDD bit also */
+	ori r3, r3, HID1_MBDD@l
+1:
 	mtspr	SPRN_HID1,r3
 #endif
 
 	/* Enable branch prediction */
-	li	r3,0x201
+	lis	r3,BUCSR_ENABLE@h
+	ori	r3,r3,BUCSR_ENABLE@l
 	mtspr	SPRN_BUCSR,r3
 
 	/* Ensure TB is 0 */
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index af18c1c..b3cb56a 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
  * Copyright (C) 2003  Motorola,Inc.
  *
  * See file CREDITS for list of people who contributed to this
@@ -208,13 +208,21 @@ _start_e500:
 
 #ifndef CONFIG_E500MC
 	li	r0,(HID1_ASTME|HID1_ABE)@l	/* Addr streaming & broadcast */
+	mfspr	r3,PVR
+	andi.	r3,r3, 0xff
+	cmpwi	r3,0x50@l	/* if we are rev 5.0 or greater set MBDD */
+	blt 1f
+	/* Set MBDD bit also */
+	ori r0, r0, HID1_MBDD@l
+1:
 	mtspr	HID1,r0
 #endif
 
 	/* Enable Branch Prediction */
 #if defined(CONFIG_BTB)
-	li	r0,0x201		/* BBFI = 1, BPEN = 1 */
-	mtspr	BUCSR,r0
+	lis	r0,BUCSR_ENABLE@h
+	ori	r0,r0,BUCSR_ENABLE@l
+	mtspr	SPRN_BUCSR,r0
 #endif
 
 #if defined(CONFIG_SYS_INIT_DBCR)
diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c
index d191263..47842e9 100644
--- a/cpu/mpc8xxx/cpu.c
+++ b/cpu/mpc8xxx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
  *
  * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c.
  * Basically this file contains cpu specific common code for 85xx/86xx
@@ -66,8 +66,16 @@ struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(8572, 8572_E, 2),
 	CPU_TYPE_ENTRY(P1011, P1011, 1),
 	CPU_TYPE_ENTRY(P1011, P1011_E, 1),
+	CPU_TYPE_ENTRY(P1012, P1012, 1),
+	CPU_TYPE_ENTRY(P1012, P1012_E, 1),
+	CPU_TYPE_ENTRY(P1013, P1013, 1),
+	CPU_TYPE_ENTRY(P1013, P1013_E, 1),
 	CPU_TYPE_ENTRY(P1020, P1020, 2),
 	CPU_TYPE_ENTRY(P1020, P1020_E, 2),
+	CPU_TYPE_ENTRY(P1021, P1021, 2),
+	CPU_TYPE_ENTRY(P1021, P1021_E, 2),
+	CPU_TYPE_ENTRY(P1022, P1022, 2),
+	CPU_TYPE_ENTRY(P1022, P1022_E, 2),
 	CPU_TYPE_ENTRY(P2010, P2010, 1),
 	CPU_TYPE_ENTRY(P2010, P2010_E, 1),
 	CPU_TYPE_ENTRY(P2020, P2020, 2),
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index adc4f6e..03f9c43 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1,9 +1,10 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
  */
 
 /*
@@ -934,7 +935,8 @@ static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
 }
 
 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
-static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
+static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
+				const memctl_options_t *popts)
 {
 	unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
 	unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
@@ -943,9 +945,15 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
 	unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
 
 #if defined(CONFIG_FSL_DDR3)
-	/* We need set BL/2 + 4 for BC4 or OTF */
-	rrt = 4;	/* BL/2 + 4 clocks */
-	wwt = 4;	/* BL/2 + 4 clocks */
+	if (popts->burst_length == DDR_BL8) {
+		/* We set BL/2 for fixed BL8 */
+		rrt = 0;	/* BL/2 clocks */
+		wwt = 0;	/* BL/2 clocks */
+	} else {
+		/* We need to set BL/2 + 2 to BC4 and OTF */
+		rrt = 2;	/* BL/2 + 2 clocks */
+		wwt = 2;	/* BL/2 + 2 clocks */
+	}
 	dll_lock = 1;	/* tDLLK = 512 clocks from spec */
 #endif
 	ddr->timing_cfg_4 = (0
@@ -1343,7 +1351,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	set_ddr_sdram_clk_cntl(ddr, popts);
 	set_ddr_init_addr(ddr);
 	set_ddr_init_ext_addr(ddr);
-	set_timing_cfg_4(ddr);
+	set_timing_cfg_4(ddr, popts);
 	set_timing_cfg_5(ddr);
 
 	set_ddr_zq_cntl(ddr, zq_en);
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 3dcd33d..46731c8 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -1,9 +1,10 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
  */
 
 #include <common.h>
@@ -109,8 +110,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 
 	/* Choose burst length. */
 #if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_E500MC)
+	popts->OTF_burst_chop_en = 0;	/* on-the-fly burst chop disable */
+	popts->burst_length = DDR_BL8;	/* Fixed 8-beat burst len */
+#else
 	popts->OTF_burst_chop_en = 1;	/* on-the-fly burst chop */
 	popts->burst_length = DDR_OTF;	/* on-the-fly BC4 and BL8 */
+#endif
 #else
 	popts->burst_length = DDR_BL4;	/* has to be 4 for DDR2 */
 #endif
diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c
index d53781b..9b7181d 100644
--- a/cpu/mpc8xxx/pci_cfg.c
+++ b/cpu/mpc8xxx/pci_cfg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,7 +25,7 @@
 #include <pci.h>
 
 struct pci_info {
-	u16	cfg;
+	u32	cfg;
 };
 
 /* The cfg field is a bit mask in which each bit represents the value of
@@ -153,7 +153,8 @@ static struct pci_info pci_config_info[] =
 			 (1 << 7) | (1 << 0xe) | (1 << 0xf),
 	},
 };
-#elif defined(CONFIG_P1011) || defined(CONFIG_P1020)
+#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
+      defined(CONFIG_P1012) || defined(CONFIG_P1021)
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCIE_1] = {
@@ -163,6 +164,29 @@ static struct pci_info pci_config_info[] =
 		.cfg =   (1 << 0xe),
 	},
 };
+#elif defined(CONFIG_P1013) || defined(CONFIG_P1022)
+static struct pci_info pci_config_info[] =
+{
+	[LAW_TRGT_IF_PCIE_1] = {
+		.cfg =   (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) |
+			 (1 << 0xb) | (1 << 0xd) | (1 << 0xe) |
+			 (1 << 0xf) | (1 << 0x15) | (1 << 0x16) |
+			 (1 << 0x17) | (1 << 0x18) | (1 << 0x19) |
+			 (1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) |
+			 (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
+	},
+	[LAW_TRGT_IF_PCIE_2] = {
+		.cfg =   (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) |
+			 (1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) |
+			 (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
+			 (1 << 0x18) | (1 << 0x1c),
+	},
+	[LAW_TRGT_IF_PCIE_3] = {
+		.cfg =   (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) |
+			 (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) |
+			 (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
+	},
+};
 #elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
 static struct pci_info pci_config_info[] =
 {
diff --git a/cpu/nios2/Makefile b/cpu/nios2/Makefile
index 75f30b4..3dfaa83 100644
--- a/cpu/nios2/Makefile
+++ b/cpu/nios2/Makefile
@@ -27,7 +27,7 @@ LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
 SOBJS	= exceptions.o
-COBJS	= cpu.o interrupts.o serial.o sysid.o traps.o epcs.o
+COBJS	= cpu.o interrupts.o sysid.o traps.o epcs.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c
index 483b249..ab7d746 100644
--- a/cpu/nios2/epcs.c
+++ b/cpu/nios2/epcs.c
@@ -85,7 +85,7 @@ static int epcs_cs (int assert)
 
 	if (assert) {
 		tmp = readl (&epcs->control);
-		writel (&epcs->control, tmp | NIOS_SPI_SSO);
+		writel (tmp | NIOS_SPI_SSO, &epcs->control);
 	} else {
 		/* Let all bits shift out */
 		start = get_timer (0);
@@ -93,7 +93,7 @@ static int epcs_cs (int assert)
 			if (get_timer (start) > EPCS_TIMEOUT)
 				return (-1);
 		tmp = readl (&epcs->control);
-		writel (&epcs->control, tmp & ~NIOS_SPI_SSO);
+		writel (tmp & ~NIOS_SPI_SSO, &epcs->control);
 	}
 	return (0);
 }
@@ -106,7 +106,7 @@ static int epcs_tx (unsigned char c)
 	while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0)
 		if (get_timer (start) > EPCS_TIMEOUT)
 			return (-1);
-	writel (&epcs->txdata, c);
+	writel (c, &epcs->txdata);
 	return (0);
 }
 
@@ -207,6 +207,8 @@ static void epcs_status_wr (unsigned char status)
 static struct epcs_devinfo_t devinfo[] = {
 	{ "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c },
 	{ "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c },
+	{ "EPCS16", 0x14, 21, 32, 16, 8, 0x1c },
+	{ "EPCS64", 0x16, 23,128, 16, 8, 0x1c },
 	{ 0, 0, 0, 0, 0, 0 }
 };
 
@@ -501,15 +503,17 @@ void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char *argv[])
 	}
 
 	/* Sector info */
-	for (i=0; i<dev->num_sects; i++) {
+	for (i=0; (i < dev->num_sects) && (argc > 1); i++) {
 		erased = epcs_sect_erased (i, &tmp, dev);
-		printf ("     %d: %06x ",
+		if ((i & 0x03) == 0) printf ("\n");
+		printf ("%4d: %07x ",
 			i, i*(1<<dev->sz_sect) );
 		if (erased)
-			printf ("erased\n");
+			printf ("E ");
 		else
-			printf ("data @ 0x%06x\n", tmp);
+			printf ("  ");
 	}
+	printf ("\n");
 
 	return;
 }
diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c
index 1c3566e..b552db4 100644
--- a/cpu/nios2/interrupts.c
+++ b/cpu/nios2/interrupts.c
@@ -56,7 +56,40 @@ volatile ulong timestamp = 0;
 
 void reset_timer (void)
 {
+	nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
+
+	/* From Embedded Peripherals Handbook:
+	 *
+	 * "When the hardware is configured with Writeable period
+	 * disabled, writing to one of the period_n registers causes
+	 * the counter to reset to the fixed Timeout Period specified
+	 * at system generation time."
+	 *
+	 * Here we force a reload to prevent early timeouts from
+	 * get_timer() when the interrupt period is greater than
+	 * than 1 msec.
+	 *
+	 * Simply write to periodl with its own value to force an
+	 * internal counter reload, THEN reset the timestamp.
+	 */
+	writel (readl (&tmr->periodl), &tmr->periodl);
 	timestamp = 0;
+
+	/* From Embedded Peripherals Handbook:
+	 *
+	 * "Writing to one of the period_n registers stops the internal
+	 * counter, except when the hardware is configured with Start/Stop
+	 * control bits off. If Start/Stop control bits is off, writing
+	 * either register does not stop the counter."
+	 *
+	 * In order to accomodate either configuration, the control
+	 * register is re-written. If the counter is stopped, it will
+	 * be restarted. If it is running, the write is essentially
+	 * a nop.
+	 */
+	writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
+			&tmr->control);
+
 }
 
 ulong get_timer (ulong base)
@@ -81,7 +114,7 @@ void tmr_isr (void *arg)
 	/* Interrupt is cleared by writing anything to the
 	 * status register.
 	 */
-	writel (&tmr->status, 0);
+	writel (0, &tmr->status);
 	timestamp += CONFIG_SYS_NIOS_TMRMS;
 #ifdef CONFIG_STATUS_LED
 	status_led_tick(timestamp);
@@ -92,16 +125,16 @@ static void tmr_init (void)
 {
 	nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
 
-	writel (&tmr->status, 0);
-	writel (&tmr->control, 0);
-	writel (&tmr->control, NIOS_TIMER_STOP);
+	writel (0, &tmr->status);
+	writel (0, &tmr->control);
+	writel (NIOS_TIMER_STOP, &tmr->control);
 
 #if defined(CONFIG_SYS_NIOS_TMRCNT)
-	writel (&tmr->periodl, CONFIG_SYS_NIOS_TMRCNT & 0xffff);
-	writel (&tmr->periodh, (CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff);
+	writel (CONFIG_SYS_NIOS_TMRCNT & 0xffff, &tmr->periodl);
+	writel ((CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff, &tmr->periodh);
 #endif
-	writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT |
-			  NIOS_TIMER_START );
+	writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
+			&tmr->control);
 	irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr);
 }
 
diff --git a/cpu/nios2/serial.c b/cpu/nios2/serial.c
deleted file mode 100644
index 6c835af..0000000
--- a/cpu/nios2/serial.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * YANU Support:
- * Copyright 2010, Renato Andreola <renato.andreola@imagos.it>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <watchdog.h>
-#include <asm/io.h>
-#include <nios2-io.h>
-#include <nios2-yanu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*------------------------------------------------------------------
- * JTAG acts as the serial port
- *-----------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
-
-static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE;
-
-void serial_setbrg( void ){ return; }
-int serial_init( void ) { return(0);}
-
-void serial_putc (char c)
-{
-	unsigned val;
-
-	while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0)
-		WATCHDOG_RESET ();
-	writel (&jtag->data, (unsigned char)c);
-}
-
-void serial_puts (const char *s)
-{
-	while (*s != 0)
-		serial_putc (*s++);
-}
-
-int serial_tstc (void)
-{
-	return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
-}
-
-int serial_getc (void)
-{
-	int c;
-	unsigned val;
-
-	while (1) {
-		WATCHDOG_RESET ();
-		val = readl (&jtag->data);
-		if (val & NIOS_JTAG_RVALID)
-			break;
-	}
-	c = val & 0x0ff;
-	return (c);
-}
-
-#elif defined(CONFIG_CONSOLE_YANU)
-/*-----------------------------------------------------------------*/
-/* YANU Imagos serial port */
-/*-----------------------------------------------------------------*/
-
-static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE;
-
-#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
-
-/* Everything's already setup for fixed-baud PTF assignment*/
-
-void serial_setbrg (void)
-{
-	int n, k;
-	const unsigned max_uns = 0xFFFFFFFF;
-	unsigned best_n, best_m, baud;
-
-	/* compute best N and M couple */
-	best_n = YANU_MAX_PRESCALER_N;
-	for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) {
-		if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >=
-		    (unsigned)CONFIG_BAUDRATE) {
-			best_n = n;
-			break;
-		}
-	}
-	for (k = 0;; k++) {
-		if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k)))
-			break;
-	}
-	best_m =
-	    ((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) /
-	    ((unsigned)CONFIG_SYS_CLK_FREQ >> k);
-
-	baud = best_m + best_n * YANU_BAUDE;
-	writel(&uart->baud, baud);
-
-	return;
-}
-
-#else
-
-void serial_setbrg (void)
-{	
-	int n, k;
-	const unsigned max_uns = 0xFFFFFFFF;
-	unsigned best_n, best_m, baud;
-
-	/* compute best N and M couple */
-	best_n = YANU_MAX_PRESCALER_N;
-	for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) {
-		if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >=
-		    gd->baudrate) {
-			best_n = n;
-			break;
-		}
-	}
-	for (k = 0;; k++) {
-		if (gd->baudrate <= (max_uns >> (15+n-k)))
-			break;
-	}
-	best_m =
-	    (gd->baudrate * (1 << (15 + n - k))) /
-	    ((unsigned)CONFIG_SYS_CLK_FREQ >> k);
-
-	baud = best_m + best_n * YANU_BAUDE;
-	writel(&uart->baud, baud);
-
-	return;
-}
-
-
-#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
-
-int serial_init (void)
-{
-	unsigned action,control;
-
-	/* status register cleanup */
-	action =  YANU_ACTION_RRRDY     |
-		YANU_ACTION_RTRDY       |
-		YANU_ACTION_ROE         |
-		YANU_ACTION_RBRK        |
-		YANU_ACTION_RFE         |
-		YANU_ACTION_RPE         |
-	    YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR;
-
-	writel(&uart->action, action);
-	
-	/*  control register cleanup */
-	/* no interrupts enabled */
-	/* one stop bit */
-	/* hardware flow control disabled */
-	/* 8 bits */
-	control = (0x7 << YANU_CONTROL_BITS_POS);
-	/* enven parity just to be clean */
-	control |= YANU_CONTROL_PAREVEN;
-	/* we set threshold for fifo */
-	control |= YANU_CONTROL_RDYDLY * YANU_RXFIFO_DLY;
-	control |= YANU_CONTROL_TXTHR *  YANU_TXFIFO_THR;
-
-	writel(&uart->control, control);
-
-	/* to set baud rate */
-	serial_setbrg();
-
-	return (0);
-}
-
-
-/*-----------------------------------------------------------------------
- * YANU CONSOLE
- *---------------------------------------------------------------------*/
-void serial_putc (char c)
-{
-	int tx_chars;
-	unsigned status;
-
-	if (c == '\n')
-		serial_putc ('\r');
-	
-	while (1) {
-		status = readl(&uart->status);
-		tx_chars = (status>>YANU_TFIFO_CHARS_POS)
-			& ((1<<YANU_TFIFO_CHARS_N)-1);
-		if (tx_chars < YANU_TXFIFO_SIZE-1)
-			break;
-		WATCHDOG_RESET ();
-	}
-
-	writel(&uart->data, (unsigned char)c);
-}
-
-void serial_puts (const char *s)
-{
-	while (*s != 0) {
-		serial_putc (*s++);
-	}
-}
-
-
-int serial_tstc(void)
-{
-	unsigned status ;
-
-	status = readl(&uart->status);
-	return (((status >> YANU_RFIFO_CHARS_POS) &
-		 ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0);
-}	
-
-int serial_getc (void)
-{
-	while (serial_tstc() == 0)
-		WATCHDOG_RESET ();
-	
-	/* first we pull the char */
-	writel(&uart->action, YANU_ACTION_RFIFO_PULL);
-
-	return(readl(&uart->data) & YANU_DATA_CHAR_MASK);
-}
-
-#else /*CONFIG_CONSOLE_YANU*/
-
-/*------------------------------------------------------------------
- * UART the serial port
- *-----------------------------------------------------------------*/
-
-static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE;
-
-#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
-
-/* Everything's already setup for fixed-baud PTF
- * assignment
- */
-void serial_setbrg (void){ return; }
-int serial_init (void) { return (0);}
-
-#else
-
-void serial_setbrg (void)
-{
-	unsigned div;
-
-	div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
-	writel (&uart->divisor,div);
-	return;
-}
-
-int serial_init (void)
-{
-	serial_setbrg ();
-	return (0);
-}
-
-#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
-
-
-/*-----------------------------------------------------------------------
- * UART CONSOLE
- *---------------------------------------------------------------------*/
-void serial_putc (char c)
-{
-	if (c == '\n')
-		serial_putc ('\r');
-	while ((readl (&uart->status) & NIOS_UART_TRDY) == 0)
-		WATCHDOG_RESET ();
-	writel (&uart->txdata,(unsigned char)c);
-}
-
-void serial_puts (const char *s)
-{
-	while (*s != 0) {
-		serial_putc (*s++);
-	}
-}
-
-int serial_tstc (void)
-{
-	return (readl (&uart->status) & NIOS_UART_RRDY);
-}
-
-int serial_getc (void)
-{
-	while (serial_tstc () == 0)
-		WATCHDOG_RESET ();
-	return (readl (&uart->rxdata) & 0x00ff );
-}
-
-#endif /* CONFIG_JTAG_CONSOLE */
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index 365f966..88d53fb 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -52,7 +52,6 @@ COBJS	+= denali_data_eye.o
 COBJS	+= denali_spd_ddr2.o
 COBJS	+= ecc.o
 COBJS	+= fdt.o
-COBJS	+= i2c.o
 COBJS	+= interrupts.o
 COBJS	+= iop480_uart.o
 ifdef CONFIG_CMD_REGINFO
diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
deleted file mode 100644
index 9b86187..0000000
--- a/cpu/ppc4xx/i2c.c
+++ /dev/null
@@ -1,439 +0,0 @@
-/*
- * (C) Copyright 2007-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
- *
- * (C) Copyright 2001
- * Bill Hunter,  Wave 7 Optics, williamhunter@mediaone.net
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <ppc4xx.h>
-#include <4xx_i2c.h>
-#include <i2c.h>
-#include <asm-ppc/io.h>
-
-#ifdef CONFIG_HARD_I2C
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_I2C_MULTI_BUS)
-/*
- * Initialize the bus pointer to whatever one the SPD EEPROM is on.
- * Default is bus 0.  This is necessary because the DDR initialization
- * runs from ROM, and we can't switch buses because we can't modify
- * the global variables.
- */
-#ifndef CONFIG_SYS_SPD_BUS_NUM
-#define CONFIG_SYS_SPD_BUS_NUM	0
-#endif
-static unsigned int i2c_bus_num __attribute__ ((section (".data"))) =
-	CONFIG_SYS_SPD_BUS_NUM;
-#endif /* CONFIG_I2C_MULTI_BUS */
-
-static void _i2c_bus_reset(void)
-{
-	struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
-	int i;
-	u8 dc;
-
-	/* Reset status register */
-	/* write 1 in SCMP and IRQA to clear these fields */
-	out_8(&i2c->sts, 0x0A);
-
-	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
-	out_8(&i2c->extsts, 0x8F);
-
-	/* Place chip in the reset state */
-	out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
-
-	/* Check if bus is free */
-	dc = in_8(&i2c->directcntl);
-	if (!DIRCTNL_FREE(dc)){
-		/* Try to set bus free state */
-		out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
-
-		/* Wait until we regain bus control */
-		for (i = 0; i < 100; ++i) {
-			dc = in_8(&i2c->directcntl);
-			if (DIRCTNL_FREE(dc))
-				break;
-
-			/* Toggle SCL line */
-			dc ^= IIC_DIRCNTL_SCC;
-			out_8(&i2c->directcntl, dc);
-			udelay(10);
-			dc ^= IIC_DIRCNTL_SCC;
-			out_8(&i2c->directcntl, dc);
-		}
-	}
-
-	/* Remove reset */
-	out_8(&i2c->xtcntlss, 0);
-}
-
-void i2c_init(int speed, int slaveaddr)
-{
-	struct ppc4xx_i2c *i2c;
-	int val, divisor;
-	int bus;
-
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-	/*
-	 * Call board specific i2c bus reset routine before accessing the
-	 * environment, which might be in a chip on that bus. For details
-	 * about this problem see doc/I2C_Edge_Conditions.
-	 */
-	i2c_init_board();
-#endif
-
-	for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) {
-		I2C_SET_BUS(bus);
-
-		/* Set i2c pointer after calling I2C_SET_BUS() */
-		i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
-
-		/* Handle possible failed I2C state */
-		/* FIXME: put this into i2c_init_board()? */
-		_i2c_bus_reset();
-
-		/* clear lo master address */
-		out_8(&i2c->lmadr, 0);
-
-		/* clear hi master address */
-		out_8(&i2c->hmadr, 0);
-
-		/* clear lo slave address */
-		out_8(&i2c->lsadr, 0);
-
-		/* clear hi slave address */
-		out_8(&i2c->hsadr, 0);
-
-		/* Clock divide Register */
-		/* set divisor according to freq_opb */
-		divisor = (get_OPB_freq() - 1) / 10000000;
-		if (divisor == 0)
-			divisor = 1;
-		out_8(&i2c->clkdiv, divisor);
-
-		/* no interrupts */
-		out_8(&i2c->intrmsk, 0);
-
-		/* clear transfer count */
-		out_8(&i2c->xfrcnt, 0);
-
-		/* clear extended control & stat */
-		/* write 1 in SRC SRS SWC SWS to clear these fields */
-		out_8(&i2c->xtcntlss, 0xF0);
-
-		/* Mode Control Register
-		   Flush Slave/Master data buffer */
-		out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
-
-		val = in_8(&i2c->mdcntl);
-
-		/* Ignore General Call, slave transfers are ignored,
-		 * disable interrupts, exit unknown bus state, enable hold
-		 * SCL 100kHz normaly or FastMode for 400kHz and above
-		 */
-
-		val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
-		if (speed >= 400000)
-			val |= IIC_MDCNTL_FSM;
-		out_8(&i2c->mdcntl, val);
-
-		/* clear control reg */
-		out_8(&i2c->cntl, 0x00);
-	}
-
-	/* set to SPD bus as default bus upon powerup */
-	I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
-}
-
-/*
- * This code tries to use the features of the 405GP i2c
- * controller. It will transfer up to 4 bytes in one pass
- * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
- * is possible to do out16(lhz) transfers.
- *
- * cmd_type is 0 for write 1 for read.
- *
- * addr_len can take any value from 0-255, it is only limited
- * by the char, we could make it larger if needed. If it is
- * 0 we skip the address write cycle.
- *
- * Typical case is a Write of an addr followd by a Read. The
- * IBM FAQ does not cover this. On the last byte of the write
- * we don't set the creg CHT bit, and on the first bytes of the
- * read we set the RPST bit.
- *
- * It does not support address only transfers, there must be
- * a data part. If you want to write the address yourself, put
- * it in the data pointer.
- *
- * It does not support transfer to/from address 0.
- *
- * It does not check XFRCNT.
- */
-static int i2c_transfer(unsigned char cmd_type,
-			unsigned char chip,
-			unsigned char addr[],
-			unsigned char addr_len,
-			unsigned char data[],
-			unsigned short data_len)
-{
-	struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
-	u8 *ptr;
-	int reading;
-	int tran, cnt;
-	int result;
-	int status;
-	int i;
-	u8 creg;
-
-	if (data == 0 || data_len == 0) {
-		/* Don't support data transfer of no length or to address 0 */
-		printf( "i2c_transfer: bad call\n" );
-		return IIC_NOK;
-	}
-	if (addr && addr_len) {
-		ptr = addr;
-		cnt = addr_len;
-		reading = 0;
-	} else {
-		ptr = data;
-		cnt = data_len;
-		reading = cmd_type;
-	}
-
-	/* Clear Stop Complete Bit */
-	out_8(&i2c->sts, IIC_STS_SCMP);
-
-	/* Check init */
-	i = 10;
-	do {
-		/* Get status */
-		status = in_8(&i2c->sts);
-		i--;
-	} while ((status & IIC_STS_PT) && (i > 0));
-
-	if (status & IIC_STS_PT) {
-		result = IIC_NOK_TOUT;
-		return(result);
-	}
-
-	/* flush the Master/Slave Databuffers */
-	out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) |
-	      IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB);
-
-	/* need to wait 4 OPB clocks? code below should take that long */
-
-	/* 7-bit adressing */
-	out_8(&i2c->hmadr, 0);
-	out_8(&i2c->lmadr, chip);
-
-	tran = 0;
-	result = IIC_OK;
-	creg = 0;
-
-	while (tran != cnt && (result == IIC_OK)) {
-		int  bc,j;
-
-		/*
-		 * Control register =
-		 * Normal transfer, 7-bits adressing, Transfer up to
-		 * bc bytes, Normal start, Transfer is a sequence of transfers
-		 */
-		creg |= IIC_CNTL_PT;
-
-		bc = (cnt - tran) > 4 ? 4 : cnt - tran;
-		creg |= (bc - 1) << 4;
-		/* if the real cmd type is write continue trans */
-		if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
-			creg |= IIC_CNTL_CHT;
-
-		if (reading) {
-			creg |= IIC_CNTL_READ;
-		} else {
-			for(j = 0; j < bc; j++) {
-				/* Set buffer */
-				out_8(&i2c->mdbuf, ptr[tran + j]);
-			}
-		}
-		out_8(&i2c->cntl, creg);
-
-		/*
-		 * Transfer is in progress
-		 * we have to wait for upto 5 bytes of data
-		 * 1 byte chip address+r/w bit then bc bytes
-		 * of data.
-		 * udelay(10) is 1 bit time at 100khz
-		 * Doubled for slop. 20 is too small.
-		 */
-		i = 2 * 5 * 8;
-		do {
-			/* Get status */
-			status = in_8(&i2c->sts);
-			udelay(10);
-			i--;
-		} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) &&
-			 (i > 0));
-
-		if (status & IIC_STS_ERR) {
-			result = IIC_NOK;
-			status = in_8(&i2c->extsts);
-			/* Lost arbitration? */
-			if (status & IIC_EXTSTS_LA)
-				result = IIC_NOK_LA;
-			/* Incomplete transfer? */
-			if (status & IIC_EXTSTS_ICT)
-				result = IIC_NOK_ICT;
-			/* Transfer aborted? */
-			if (status & IIC_EXTSTS_XFRA)
-				result = IIC_NOK_XFRA;
-		} else if ( status & IIC_STS_PT) {
-			result = IIC_NOK_TOUT;
-		}
-
-		/* Command is reading => get buffer */
-		if ((reading) && (result == IIC_OK)) {
-			/* Are there data in buffer */
-			if (status & IIC_STS_MDBS) {
-				/*
-				 * even if we have data we have to wait 4OPB
-				 * clocks for it to hit the front of the FIFO,
-				 * after that we can just read. We should check
-				 * XFCNT here and if the FIFO is full there is
-				 * no need to wait.
-				 */
-				udelay(1);
-				for (j = 0; j < bc; j++)
-					ptr[tran + j] = in_8(&i2c->mdbuf);
-			} else
-				result = IIC_NOK_DATA;
-		}
-		creg = 0;
-		tran += bc;
-		if (ptr == addr && tran == cnt) {
-			ptr = data;
-			cnt = data_len;
-			tran = 0;
-			reading = cmd_type;
-			if (reading)
-				creg = IIC_CNTL_RPST;
-		}
-	}
-	return result;
-}
-
-int i2c_probe(uchar chip)
-{
-	uchar buf[1];
-
-	buf[0] = 0;
-
-	/*
-	 * What is needed is to send the chip address and verify that the
-	 * address was <ACK>ed (i.e. there was a chip at that address which
-	 * drove the data line low).
-	 */
-	return (i2c_transfer(1, chip << 1, 0, 0, buf, 1) != 0);
-}
-
-static int ppc4xx_i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
-			       int len, int read)
-{
-	uchar xaddr[4];
-	int ret;
-
-	if (alen > 4) {
-		printf("I2C: addr len %d not supported\n", alen);
-		return 1;
-	}
-
-	if (alen > 0) {
-		xaddr[0] = (addr >> 24) & 0xFF;
-		xaddr[1] = (addr >> 16) & 0xFF;
-		xaddr[2] = (addr >> 8) & 0xFF;
-		xaddr[3] = addr & 0xFF;
-	}
-
-
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-	/*
-	 * EEPROM chips that implement "address overflow" are ones
-	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
-	 * address and the extra bits end up in the "chip address"
-	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
-	 * four 256 byte chips.
-	 *
-	 * Note that we consider the length of the address field to
-	 * still be one byte because the extra address bits are
-	 * hidden in the chip address.
-	 */
-	if (alen > 0)
-		chip |= ((addr >> (alen * 8)) &
-			 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
-#endif
-	if ((ret = i2c_transfer(read, chip << 1, &xaddr[4 - alen], alen,
-				buffer, len)) != 0) {
-		if (gd->have_console) {
-			printf("I2C %s: failed %d\n",
-			       read ? "read" : "write", ret);
-		}
-
-		return 1;
-	}
-
-	return 0;
-}
-
-int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
-	return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 1);
-}
-
-int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
-{
-	return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 0);
-}
-
-#if defined(CONFIG_I2C_MULTI_BUS)
-/*
- * Functions for multiple I2C bus handling
- */
-unsigned int i2c_get_bus_num(void)
-{
-	return i2c_bus_num;
-}
-
-int i2c_set_bus_num(unsigned int bus)
-{
-	if (bus >= CONFIG_SYS_MAX_I2C_BUS)
-		return -1;
-
-	i2c_bus_num = bus;
-
-	return 0;
-}
-#endif	/* CONFIG_I2C_MULTI_BUS */
-#endif	/* CONFIG_HARD_I2C */