summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'cpu')
-rw-r--r--cpu/74xx_7xx/cache.S21
-rw-r--r--cpu/arm1136/mx31/generic.c4
-rw-r--r--cpu/arm920t/s3c24x0/usb.c2
-rw-r--r--cpu/arm926ejs/at91sam9/Makefile2
-rw-r--r--cpu/arm926ejs/at91sam9/ether.c2
-rw-r--r--cpu/arm926ejs/at91sam9/lowlevel_init.S2
-rw-r--r--cpu/arm926ejs/at91sam9/timer.c2
-rw-r--r--cpu/arm926ejs/at91sam9/usb.c2
-rw-r--r--cpu/mips/cache.S6
-rw-r--r--cpu/mpc86xx/cache.S2
-rw-r--r--cpu/ppc4xx/fdt.c26
-rw-r--r--cpu/ppc4xx/speed.c2
12 files changed, 57 insertions, 16 deletions
diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S
index a793d79..3a745cb 100644
--- a/cpu/74xx_7xx/cache.S
+++ b/cpu/74xx_7xx/cache.S
@@ -329,14 +329,28 @@ _GLOBAL(dcache_status)
blr
/*
- * Invalidate L2 cache using L2I and polling L2IP
+ * Invalidate L2 cache using L2I and polling L2IP or L2I
*/
_GLOBAL(l2cache_invalidate)
sync
+ mfspr r3, l2cr
oris r3, r3, L2CR_L2I@h
sync
mtspr l2cr, r3
sync
+ mfspr r3, PVR
+ sync
+ rlwinm r3, r3, 16,16,31
+ cmpli 0,r3,0x8000 /* 7451, 7441 */
+ beq 0,inv_7450
+ cmpli 0,r3,0x8001 /* 7455, 7445 */
+ beq 0,inv_7450
+ cmpli 0,r3,0x8002 /* 7457, 7447 */
+ beq 0,inv_7450
+ cmpli 0,r3,0x8003 /* 7447A */
+ beq 0,inv_7450
+ cmpli 0,r3,0x8004 /* 7448 */
+ beq 0,inv_7450
invl2:
mfspr r3, l2cr
andi. r3, r3, L2CR_L2IP
@@ -348,6 +362,11 @@ invl2:
mtspr l2cr, r3
sync
blr
+inv_7450:
+ mfspr r3, l2cr
+ andis. r3, r3, L2CR_L2I@h
+ bne inv_7450
+ blr
/*
* Enable L2 cache
diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c
index 16b2cf1..29c08c1 100644
--- a/cpu/arm1136/mx31/generic.c
+++ b/cpu/arm1136/mx31/generic.c
@@ -39,7 +39,7 @@ static u32 mx31_decode_pll(u32 reg, u32 infreq)
(mfd * pd)) << 10;
}
-u32 mx31_get_mpl_dpdgck_clk(void)
+static u32 mx31_get_mpl_dpdgck_clk(void)
{
u32 infreq;
@@ -51,7 +51,7 @@ u32 mx31_get_mpl_dpdgck_clk(void)
return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
}
-u32 mx31_get_mcu_main_clk(void)
+static u32 mx31_get_mcu_main_clk(void)
{
/* For now we assume mpl_dpdgck_clk == mcu_main_clk
* which should be correct for most boards
diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c
index ef5d5bf..421ebb4 100644
--- a/cpu/arm920t/s3c24x0/usb.c
+++ b/cpu/arm920t/s3c24x0/usb.c
@@ -69,4 +69,4 @@ int usb_cpu_init_fail (void)
}
# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) */
diff --git a/cpu/arm926ejs/at91sam9/Makefile b/cpu/arm926ejs/at91sam9/Makefile
index 203abc2..44cde1a 100644
--- a/cpu/arm926ejs/at91sam9/Makefile
+++ b/cpu/arm926ejs/at91sam9/Makefile
@@ -1,6 +1,6 @@
#
# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
diff --git a/cpu/arm926ejs/at91sam9/ether.c b/cpu/arm926ejs/at91sam9/ether.c
index e4f5601..7e11fe4 100644
--- a/cpu/arm926ejs/at91sam9/ether.c
+++ b/cpu/arm926ejs/at91sam9/ether.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
diff --git a/cpu/arm926ejs/at91sam9/lowlevel_init.S b/cpu/arm926ejs/at91sam9/lowlevel_init.S
index 40a3f6a..ec6ad5d 100644
--- a/cpu/arm926ejs/at91sam9/lowlevel_init.S
+++ b/cpu/arm926ejs/at91sam9/lowlevel_init.S
@@ -2,7 +2,7 @@
* AT91CAP9/SAM9 setup stuff
*
* (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
diff --git a/cpu/arm926ejs/at91sam9/timer.c b/cpu/arm926ejs/at91sam9/timer.c
index 4e79466..c79ec7e 100644
--- a/cpu/arm926ejs/at91sam9/timer.c
+++ b/cpu/arm926ejs/at91sam9/timer.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
diff --git a/cpu/arm926ejs/at91sam9/usb.c b/cpu/arm926ejs/at91sam9/usb.c
index d678897..441349d 100644
--- a/cpu/arm926ejs/at91sam9/usb.c
+++ b/cpu/arm926ejs/at91sam9/usb.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2006
- * DENX Software Engineering <mk <at> denx.de>
+ * DENX Software Engineering <mk@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 428d251..1b0efc3 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -240,14 +240,16 @@ NESTED(mips_cache_reset, 0, ra)
*/
move a1, t2
move a2, t4
- bal mips_init_icache
+ PTR_LA t7, mips_init_icache
+ jalr t7
/*
* then initialize D-cache.
*/
move a1, t3
move a2, t5
- bal mips_init_dcache
+ PTR_LA t7, mips_init_dcache
+ jalr t7
jr RA
END(mips_cache_reset)
diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S
index f316b3e..2e4ea02 100644
--- a/cpu/mpc86xx/cache.S
+++ b/cpu/mpc86xx/cache.S
@@ -338,7 +338,7 @@ _GLOBAL(l2cache_invalidate)
invl2:
mfspr r3, l2cr
- andi. r3, r3, L2CR_L2I@h
+ andis. r3, r3, L2CR_L2I@h
bne invl2
blr
diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index 02dece0..ccc73d5 100644
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -27,7 +27,7 @@
#include <asm/cache.h>
#include <ppc4xx.h>
-#if defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
#include <libfdt.h>
#include <libfdt_env.h>
#include <fdt_support.h>
@@ -35,6 +35,26 @@
DECLARE_GLOBAL_DATA_PTR;
+void __ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 0; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = gd->bd->bi_flashstart;
+ val[3] = gd->bd->bi_flashsize;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
+}
+void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));
+
/*
* Fixup all PCIe nodes by setting the device_type property
* to "pci-endpoint" instead is "pci" for endpoint ports.
@@ -109,4 +129,4 @@ void ft_cpu_setup(void *blob, bd_t *bd)
*/
fdt_pcie_setup(blob);
}
-#endif /* CONFIG_OF_LIBFDT */
+#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 05b42fe..8b4e64a 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -238,7 +238,7 @@ static u8 pll_fbdv_multi_bits[] = {
/* values for: 101 - 200 */
0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
- 0x20, 0xc0, 0x01, 0x83, 0x77, 0xff, 0x1f, 0xbf, 0x7f, 0xfe,
+ 0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
generated by cgit v1.1 at 2024-12-27 02:05:45 +0000