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-rw-r--r--cpu/74xx_7xx/start.S8
-rw-r--r--cpu/i386/start.S20
-rw-r--r--cpu/mpc83xx/cpu.c2
-rw-r--r--cpu/mpc83xx/pci.c2
-rw-r--r--cpu/mpc85xx/cpu.c4
-rw-r--r--cpu/mpc85xx/ddr-gen3.c9
-rw-r--r--cpu/mpc85xx/release.S8
-rw-r--r--cpu/mpc85xx/start.S6
-rw-r--r--cpu/mpc86xx/start.S20
-rw-r--r--cpu/ppc4xx/start.S3
10 files changed, 44 insertions, 38 deletions
diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S
index 07bbe01..b5484e3 100644
--- a/cpu/74xx_7xx/start.S
+++ b/cpu/74xx_7xx/start.S
@@ -857,9 +857,9 @@ lock_ram_in_cache:
*/
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r2, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
- mtctr r2
+ mtctr r4
1:
dcbz r0, r3
addi r3, r3, 32
@@ -878,9 +878,9 @@ unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r2, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
- mtctr r2
+ mtctr r4
1: icbi r0, r3
addi r3, r3, 32
bdnz 1b
diff --git a/cpu/i386/start.S b/cpu/i386/start.S
index f5ad833..b6175b1 100644
--- a/cpu/i386/start.S
+++ b/cpu/i386/start.S
@@ -55,7 +55,7 @@ early_board_init_ret:
/* so we try to indicate progress */
movw $0x01, %ax
movl $.progress0, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress0:
/* size memory */
@@ -74,7 +74,7 @@ mem_init_ret:
/* indicate (lack of) progress */
movw $0x81, %ax
movl $.progress0a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress0a:
jmp die
mem_ok:
@@ -82,7 +82,7 @@ mem_ok:
/* indicate progress */
movw $0x02, %ax
movl $.progress1, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress1:
/* create a stack after the bss */
@@ -104,7 +104,7 @@ no_stack:
/* indicate (lack of) progress */
movw $0x82, %ax
movl $.progress1a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress1a:
jmp die
@@ -113,7 +113,7 @@ stack_ok:
/* indicate progress */
movw $0x03, %ax
movl $.progress2, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress2:
/* copy data section to ram, size must be 4-byte aligned */
@@ -136,7 +136,7 @@ data_fail:
/* indicate (lack of) progress */
movw $0x83, %ax
movl $.progress2a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress2a:
jmp die
@@ -145,7 +145,7 @@ data_ok:
/* indicate progress */
movw $0x04, %ax
movl $.progress3, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress3:
/* clear bss section in ram, size must be 4-byte aligned */
@@ -168,7 +168,7 @@ bss_fail:
/* indicate (lack of) progress */
movw $0x84, %ax
movl $.progress3a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress3a:
jmp die
@@ -180,7 +180,7 @@ bss_ok:
/* indicate progress */
movw $0x05, %ax
movl $.progress4, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress4:
call start_i386boot /* Enter, U-boot! */
@@ -188,7 +188,7 @@ bss_ok:
/* indicate (lack of) progress */
movw $0x85, %ax
movl $.progress4a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress4a:
die: hlt
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index aa9b18d..5e885ab 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -148,7 +148,7 @@ int checkcpu(void)
void upmconfig (uint upm, uint *table, uint size)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile lbus83xx_t *lbus = &immap->lbus;
+ volatile fsl_lbus_t *lbus = &immap->lbus;
volatile uchar *dummy = NULL;
const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
index 5b8eeb7..ab0760b 100644
--- a/cpu/mpc83xx/pci.c
+++ b/cpu/mpc83xx/pci.c
@@ -83,7 +83,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
pci_ctrl->pibar1 = 0;
pci_ctrl->piebar1 = 0;
pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+ PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
i = hose->region_count++;
hose->regions[i].bus_start = 0;
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index b8f9125..c780687 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -134,6 +134,10 @@ int checkcpu (void)
puts("Unknown");
break;
}
+
+ if (PVR_MEM(pvr) == 0x03)
+ puts("MC");
+
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);
diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c
index e0654bb..a2b45c5 100644
--- a/cpu/mpc85xx/ddr-gen3.c
+++ b/cpu/mpc85xx/ddr-gen3.c
@@ -79,15 +79,18 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
/*
- * 32-bit workaround for DDR2
- * 32_BE
+ * For 8572 DDR1 erratum - DDR controller may enter illegal state
+ * when operatiing in 32-bit bus mode with 4-beat bursts,
+ * This erratum does not affect DDR3 mode, only for DDR2 mode.
*/
+#ifdef CONFIG_MPC8572
if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
- && in_be32(&ddr->sdram_cfg_2) & 0x80000) {
+ && in_be32(&ddr->sdram_cfg) & 0x80000) {
/* set DEBUG_1[31] */
u32 temp = in_be32(&ddr->debug_1);
out_be32(&ddr->debug_1, temp | 1);
}
+#endif
/*
* 200 painful micro-seconds must elapse between
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index ec5e4da..7c3e8a1 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -24,14 +24,18 @@
__secondary_start_page:
/* First do some preliminary setup */
lis r3, HID0_EMCP@h /* enable machine check */
+#ifndef CONFIG_E500MC
ori r3,r3,HID0_TBEN@l /* enable Timebase */
+#endif
#ifdef CONFIG_PHYS_64BIT
ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
#endif
mtspr SPRN_HID0,r3
+#ifndef CONFIG_E500MC
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr SPRN_HID1,r3
+#endif
/* Enable branch prediction */
li r3,0x201
@@ -64,7 +68,11 @@ __secondary_start_page:
/* r10 has the base address for the entry */
mfspr r0,SPRN_PIR
+#ifdef CONFIG_E500MC
+ rlwinm r4,r0,27,27,31
+#else
mr r4,r0
+#endif
slwi r8,r4,5
add r10,r3,r8
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index fc3c336..651ff1c 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -163,8 +163,10 @@ _start_e500:
ori r0,r0,HID0_TBEN@l /* Enable Timebase */
mtspr HID0,r0
+#ifndef CONFIG_E500MC
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr HID1,r0
+#endif
/* Enable Branch Prediction */
#if defined(CONFIG_BTB)
@@ -998,8 +1000,8 @@ trap_reloc:
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
- lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
- ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+ lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
+ ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
mfspr r4,L1CFG0
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 159f3e1..75e4317 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -202,8 +202,12 @@ boot_warm:
mtmsr 0
#endif
+ /* Invalidate BATs */
bl invalidate_bats
sync
+ /* Invalidate all of TLB before MMU turn on */
+ bl clear_tlbs
+ sync
#ifdef CONFIG_SYS_L2
/* init the L2 cache */
@@ -275,7 +279,6 @@ in_flash:
/* setup the rest of the bats */
bl setup_bats
- bl clear_tlbs
sync
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
@@ -617,7 +620,6 @@ relocate_code:
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Global Data pointer */
- mr r2, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
@@ -644,16 +646,6 @@ relocate_code:
/*
* Now relocate code
*/
-#ifdef CONFIG_ECC
- bl board_relocate_rom
- sync
- mr r3, r10 /* Destination Address */
- lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
- lwz r5, GOT(__init_end)
- sub r5, r5, r4
- li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
-#else
cmplw cr1,r3,r4
addi r0,r5,3
srwi. r0,r0,2
@@ -675,7 +667,6 @@ relocate_code:
3: lwzu r0,-4(r8)
stwu r0,-4(r7)
bdnz 3b
-#endif
/*
* Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line.
@@ -708,9 +699,6 @@ relocate_code:
blr
in_ram:
-#ifdef CONFIG_ECC
- bl board_init_ecc
-#endif
/*
* Relocation Function, r14 point to got2+0x8000
*
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 31902a0..882ef21 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -918,7 +918,8 @@ _start:
ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
mtdccr r4
-#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
+#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
+ && !defined (CONFIG_XILINX_405)
/*----------------------------------------------------------------------- */
/* Tune the speed and size for flash CS0 */
/*----------------------------------------------------------------------- */
generated by cgit v1.1 at 2024-12-18 14:35:04 +0000