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-rw-r--r--cpu/mcf523x/cpu_init.c30
-rw-r--r--cpu/mcf523x/speed.c3
-rw-r--r--cpu/mcf52x2/cpu_init.c2
3 files changed, 18 insertions, 17 deletions
diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c
index a31054d..55c9cd3 100644
--- a/cpu/mcf523x/cpu_init.c
+++ b/cpu/mcf523x/cpu_init.c
@@ -127,19 +127,19 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- /* Setup Ports: */
- switch (CFG_UART_PORT) {
- case 0:
- gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
- break;
- case 1:
- gpio->par_uart =
- (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
- break;
- case 2:
- gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
- break;
- }
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+ break;
+ case 1:
+ gpio->par_uart =
+ (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
+ break;
+ case 2:
+ gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+ break;
+ }
}
diff --git a/cpu/mcf523x/speed.c b/cpu/mcf523x/speed.c
index 509109d..247d318 100644
--- a/cpu/mcf523x/speed.c
+++ b/cpu/mcf523x/speed.c
@@ -41,8 +41,9 @@ int get_clocks(void)
pll->syncr = PLL_SYNCR_MFD(1);
while (!(pll->synsr & PLL_SYNSR_LOCK));
-
+
gd->bus_clk = CFG_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
+
return (0);
}
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index f41d77b..458b85e 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -63,7 +63,7 @@ void cpu_init_f(void)
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
- /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */
+ /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
/*
* Setup chip selects...