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-rw-r--r--cpu/arm1136/Makefile2
-rw-r--r--cpu/arm1136/cpu.c11
-rw-r--r--cpu/arm1136/mx31/Makefile (renamed from cpu/bf533/Makefile)30
-rw-r--r--cpu/arm1136/mx31/generic.c99
-rw-r--r--cpu/arm1136/mx31/interrupts.c113
-rw-r--r--cpu/arm1136/mx31/serial.c230
-rw-r--r--cpu/arm1136/omap24xx/Makefile (renamed from cpu/bf561/Makefile)26
-rwxr-xr-x[-rw-r--r--]cpu/arm1136/omap24xx/interrupts.c (renamed from cpu/arm1136/interrupts.c)109
-rw-r--r--cpu/arm1136/omap24xx/start.S42
-rw-r--r--cpu/arm1136/start.S21
-rw-r--r--cpu/arm920t/at91rm9200/lowlevel_init.S6
-rw-r--r--cpu/arm926ejs/at91cap9/spi.c119
-rw-r--r--cpu/arm926ejs/at91sam9/Makefile (renamed from cpu/arm926ejs/at91cap9/Makefile)9
-rw-r--r--cpu/arm926ejs/at91sam9/config.mk (renamed from cpu/arm926ejs/at91cap9/config.mk)0
-rw-r--r--cpu/arm926ejs/at91sam9/ether.c (renamed from cpu/arm926ejs/at91cap9/ether.c)6
-rw-r--r--cpu/arm926ejs/at91sam9/lowlevel_init.S (renamed from cpu/arm926ejs/at91cap9/lowlevel_init.S)2
-rw-r--r--cpu/arm926ejs/at91sam9/spi.c157
-rw-r--r--cpu/arm926ejs/at91sam9/timer.c (renamed from cpu/arm926ejs/at91cap9/timer.c)32
-rw-r--r--cpu/arm926ejs/at91sam9/usb.c (renamed from cpu/arm926ejs/at91cap9/usb.c)12
-rw-r--r--cpu/arm926ejs/davinci/lowlevel_init.S79
-rw-r--r--cpu/arm926ejs/davinci/nand.c41
-rw-r--r--cpu/arm926ejs/davinci/timer.c69
-rw-r--r--cpu/arm926ejs/interrupts.c2
-rw-r--r--cpu/bf533/bf533_serial.h77
-rw-r--r--cpu/bf533/cache.S129
-rw-r--r--cpu/bf533/config.mk27
-rw-r--r--cpu/bf533/cpu.c213
-rw-r--r--cpu/bf533/cpu.h66
-rw-r--r--cpu/bf533/flush.S405
-rw-r--r--cpu/bf533/init_sdram.S183
-rw-r--r--cpu/bf533/init_sdram_bootrom_initblock.S183
-rw-r--r--cpu/bf533/interrupt.S244
-rw-r--r--cpu/bf533/interrupts.c165
-rw-r--r--cpu/bf533/ints.c112
-rw-r--r--cpu/bf533/serial.c186
-rw-r--r--cpu/bf533/start.S313
-rw-r--r--cpu/bf533/start1.S38
-rw-r--r--cpu/bf533/traps.c238
-rw-r--r--cpu/bf533/video.c194
-rw-r--r--cpu/bf533/video.h25
-rw-r--r--cpu/bf537/Makefile52
-rw-r--r--cpu/bf537/cache.S129
-rw-r--r--cpu/bf537/config.mk27
-rw-r--r--cpu/bf537/cpu.c219
-rw-r--r--cpu/bf537/cpu.h66
-rw-r--r--cpu/bf537/flush.S403
-rw-r--r--cpu/bf537/init_sdram.S178
-rw-r--r--cpu/bf537/init_sdram_bootrom_initblock.S203
-rw-r--r--cpu/bf537/interrupt.S244
-rw-r--r--cpu/bf537/interrupts.c170
-rw-r--r--cpu/bf537/ints.c112
-rw-r--r--cpu/bf537/serial.c186
-rw-r--r--cpu/bf537/serial.h77
-rw-r--r--cpu/bf537/start.S576
-rw-r--r--cpu/bf537/start1.S38
-rw-r--r--cpu/bf537/traps.c239
-rw-r--r--cpu/bf537/video.c194
-rw-r--r--cpu/bf537/video.h25
-rw-r--r--cpu/bf561/cache.S129
-rw-r--r--cpu/bf561/config.mk27
-rw-r--r--cpu/bf561/cpu.c212
-rw-r--r--cpu/bf561/cpu.h66
-rw-r--r--cpu/bf561/flush.S402
-rw-r--r--cpu/bf561/init_sdram.S175
-rw-r--r--cpu/bf561/init_sdram_bootrom_initblock.S189
-rw-r--r--cpu/bf561/interrupt.S244
-rw-r--r--cpu/bf561/ints.c112
-rw-r--r--cpu/bf561/serial.c188
-rw-r--r--cpu/bf561/serial.h77
-rw-r--r--cpu/bf561/start.S303
-rw-r--r--cpu/bf561/traps.c238
-rw-r--r--cpu/bf561/video.c194
-rw-r--r--cpu/bf561/video.h25
-rw-r--r--cpu/blackfin/.gitignore1
-rw-r--r--cpu/blackfin/Makefile65
-rwxr-xr-xcpu/blackfin/bootrom-asm-offsets.awk41
-rw-r--r--cpu/blackfin/bootrom-asm-offsets.c.in12
-rw-r--r--cpu/blackfin/cache.S61
-rw-r--r--cpu/blackfin/cpu.c141
-rw-r--r--cpu/blackfin/cpu.h (renamed from cpu/bf561/start1.S)28
-rw-r--r--cpu/blackfin/flush.S230
-rw-r--r--cpu/blackfin/i2c.c (renamed from cpu/bf537/i2c.c)98
-rw-r--r--cpu/blackfin/initcode.c353
-rw-r--r--cpu/blackfin/interrupt.S33
-rw-r--r--cpu/blackfin/interrupts.c (renamed from cpu/bf561/interrupts.c)50
-rw-r--r--cpu/blackfin/reset.c96
-rw-r--r--cpu/blackfin/serial.c124
-rw-r--r--cpu/blackfin/serial.h275
-rw-r--r--cpu/blackfin/start.S219
-rw-r--r--cpu/blackfin/system_map.S18
-rw-r--r--cpu/blackfin/traps.c353
-rw-r--r--cpu/blackfin/watchdog.c25
-rw-r--r--cpu/mcf5227x/start.S1
-rw-r--r--cpu/mcf523x/start.S1
-rw-r--r--cpu/mcf52x2/config.mk4
-rw-r--r--cpu/mcf52x2/cpu.c66
-rw-r--r--cpu/mcf52x2/cpu_init.c111
-rw-r--r--cpu/mcf52x2/interrupts.c4
-rw-r--r--cpu/mcf52x2/speed.c12
-rw-r--r--cpu/mcf52x2/start.S65
-rw-r--r--cpu/mcf532x/start.S1
-rw-r--r--cpu/mcf5445x/Makefile2
-rw-r--r--cpu/mcf5445x/dspi.c73
-rw-r--r--cpu/mcf5445x/start.S1
-rw-r--r--cpu/mcf547x_8x/start.S1
-rw-r--r--cpu/mpc83xx/cpu.c166
-rw-r--r--cpu/mpc83xx/spd_sdram.c21
-rw-r--r--cpu/mpc83xx/speed.c16
-rw-r--r--cpu/mpc83xx/start.S11
-rw-r--r--cpu/ppc4xx/4xx_enet.c72
-rw-r--r--cpu/ppc4xx/cpu_init.c102
-rw-r--r--cpu/ppc4xx/denali_spd_ddr2.c27
-rw-r--r--cpu/ppc4xx/interrupts.c7
-rw-r--r--cpu/sh4/cpu.c3
114 files changed, 3542 insertions, 9182 deletions
diff --git a/cpu/arm1136/Makefile b/cpu/arm1136/Makefile
index d5ac7d3..7701b03 100644
--- a/cpu/arm1136/Makefile
+++ b/cpu/arm1136/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
-COBJS = interrupts.o cpu.o
+COBJS = cpu.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
index fa78eaa..90e9553 100644
--- a/cpu/arm1136/cpu.c
+++ b/cpu/arm1136/cpu.c
@@ -33,9 +33,6 @@
#include <common.h>
#include <command.h>
-#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
-#include <asm/arch/omap2420.h>
-#endif
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
@@ -47,10 +44,10 @@ static unsigned long read_p15_c1 (void)
unsigned long value;
__asm__ __volatile__(
- "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
- : "=r" (value)
- :
- : "memory");
+ "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
+ : "=r" (value)
+ :
+ : "memory");
return value;
}
diff --git a/cpu/bf533/Makefile b/cpu/arm1136/mx31/Makefile
index ad48f1c..1fc8eea 100644
--- a/cpu/bf533/Makefile
+++ b/cpu/arm1136/mx31/Makefile
@@ -1,8 +1,5 @@
-# U-boot - Makefile
#
-# Copyright (c) 2005-2007 Analog Devices Inc.
-#
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -10,43 +7,38 @@
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
+# published by the Free Software Foundatio; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
-
-SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
-COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o
+LIB = $(obj)lib$(SOC).a
-EXTRA = init_sdram_bootrom_initblock.o
+COBJS = interrupts.o serial.o generic.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-START := $(addprefix $(obj),$(START))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
+all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
-#########################################################################
+#######################################################################
+##
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c
new file mode 100644
index 0000000..297d616
--- /dev/null
+++ b/cpu/arm1136/mx31/generic.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx31-regs.h>
+
+static u32 mx31_decode_pll(u32 reg, u32 infreq)
+{
+ u32 mfi = (reg >> 10) & 0xf;
+ u32 mfn = reg & 0x3f;
+ u32 mfd = (reg >> 16) & 0x3f;
+ u32 pd = (reg >> 26) & 0xf;
+
+ mfi = mfi <= 5 ? 5 : mfi;
+ mfd += 1;
+ pd += 1;
+
+ return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
+ (mfd * pd)) << 10;
+}
+
+u32 mx31_get_mpl_dpdgck_clk(void)
+{
+ u32 infreq;
+
+ if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
+ infreq = CONFIG_MX31_CLK32 * 1024;
+ else
+ infreq = CONFIG_MX31_HCLK_FREQ;
+
+ return mx31_decode_pll(__REG(CCM_MPCTL), infreq); }
+
+u32 mx31_get_mcu_main_clk(void)
+{
+ /* For now we assume mpl_dpdgck_clk == mcu_main_clk
+ * which should be correct for most boards
+ */
+ return mx31_get_mpl_dpdgck_clk();
+}
+
+u32 mx31_get_ipg_clk(void)
+{
+ u32 freq = mx31_get_mcu_main_clk();
+ u32 pdr0 = __REG(CCM_PDR0);
+
+ freq /= ((pdr0 >> 3) & 0x7) + 1;
+ freq /= ((pdr0 >> 6) & 0x3) + 1;
+
+ return freq;
+}
+
+void mx31_dump_clocks(void)
+{
+ u32 cpufreq = mx31_get_mcu_main_clk();
+ printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
+ printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
+}
+
+void mx31_gpio_mux(unsigned long mode)
+{
+ unsigned long reg, shift, tmp;
+
+ reg = IOMUXC_BASE + (mode & 0xfc);
+ shift = (~mode & 0x3) * 8;
+
+ tmp = __REG(reg);
+ tmp &= ~(0xff << shift);
+ tmp |= ((mode >> 8) & 0xff) << shift;
+ __REG(reg) = tmp;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ printf("CPU: Freescale i.MX31 at %d MHz\n",
+ mx31_get_mcu_main_clk() / 1000000);
+ return 0;
+}
+#endif
diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c
new file mode 100644
index 0000000..189f601
--- /dev/null
+++ b/cpu/arm1136/mx31/interrupts.c
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx31-regs.h>
+
+#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
+
+/* General purpose timers registers */
+#define GPTCR __REG(TIMER_BASE) /* Control register */
+#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
+#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
+#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR (1<<15) /* Software reset */
+#define GPTCR_FRR (1<<9) /* Freerun / restart */
+#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
+#define GPTCR_TEN (1) /* Timer enable */
+
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ */
+int interrupt_init(void)
+{
+ int i;
+
+ /* setup GP Timer 1 */
+ GPTCR = GPTCR_SWR;
+ for (i = 0; i < 100; i++) GPTCR = 0; /* We have no udelay by now */
+ GPTPR = 0; /* 32Khz */
+ /* Freerun Mode, PERCLK1 input */
+ GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+
+ return 0;
+}
+
+void reset_timer_masked(void)
+{
+ GPTCR = 0;
+ /* Freerun Mode, PERCLK1 input*/
+ GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong val = GPTCNT;
+ return val;
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay(unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ if (usec >= 1000) {
+ /* "big" number, spread normalization to seconds */
+ /* start to normalize for usec to ticks per sec */
+ tmo = usec / 1000;
+ /* find number of "ticks" to wait to achieve target */
+ tmo *= CFG_HZ;
+ tmo /= 1000; /* finish normalize. */
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CFG_HZ;
+ tmo /= (1000*1000);
+ }
+
+ tmp = get_timer(0); /* get current timestamp */
+ if ((tmo + tmp + 1) < tmp)
+ /* setting this forward will roll time stamp */
+ /* reset "advancing" timestamp to 0, set lastinc value */
+ reset_timer_masked();
+ else
+ /* else, set advancing stamp wake up time */
+ tmo += tmp;
+ while (get_timer_masked() < tmo)/* loop till event */
+ /*NOP*/;
+}
+
+void reset_cpu(ulong addr)
+{
+ __REG16(WDOG_BASE) = 4;
+}
diff --git a/cpu/arm1136/mx31/serial.c b/cpu/arm1136/mx31/serial.c
new file mode 100644
index 0000000..f7e1b3b
--- /dev/null
+++ b/cpu/arm1136/mx31/serial.c
@@ -0,0 +1,230 @@
+/*
+ * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+
+#if defined CONFIG_MX31_UART
+
+#include <asm/arch/mx31.h>
+
+#define __REG(x) (*((volatile u32 *)(x)))
+
+#ifdef CFG_MX31_UART1
+#define UART_PHYS 0x43f90000
+#elif defined(CFG_MX31_UART2)
+#define UART_PHYS 0x43f94000
+#elif defined(CFG_MX31_UART3)
+#define UART_PHYS 0x5000c000
+#elif defined(CFG_MX31_UART4)
+#define UART_PHYS 0x43fb0000
+#elif defined(CFG_MX31_UART5)
+#define UART_PHYS 0x43fb4000
+#else
+#error "define CFG_MX31_UARTx to use the mx31 UART driver"
+#endif
+
+/* Register definitions */
+#define URXD 0x0 /* Receiver Register */
+#define UTXD 0x40 /* Transmitter Register */
+#define UCR1 0x80 /* Control Register 1 */
+#define UCR2 0x84 /* Control Register 2 */
+#define UCR3 0x88 /* Control Register 3 */
+#define UCR4 0x8c /* Control Register 4 */
+#define UFCR 0x90 /* FIFO Control Register */
+#define USR1 0x94 /* Status Register 1 */
+#define USR2 0x98 /* Status Register 2 */
+#define UESC 0x9c /* Escape Character Register */
+#define UTIM 0xa0 /* Escape Timer Register */
+#define UBIR 0xa4 /* BRM Incremental Register */
+#define UBMR 0xa8 /* BRM Modulator Register */
+#define UBRC 0xac /* Baud Rate Count Register */
+#define UTS 0xb4 /* UART Test Register (mx31) */
+
+/* UART Control Register Bit Fields.*/
+#define URXD_CHARRDY (1<<15)
+#define URXD_ERR (1<<14)
+#define URXD_OVRRUN (1<<13)
+#define URXD_FRMERR (1<<12)
+#define URXD_BRK (1<<11)
+#define URXD_PRERR (1<<10)
+#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
+#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
+#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
+#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
+#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
+#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
+#define UCR1_IREN (1<<7) /* Infrared interface enable */
+#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
+#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
+#define UCR1_SNDBRK (1<<4) /* Send break */
+#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
+#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
+#define UCR1_DOZE (1<<1) /* Doze */
+#define UCR1_UARTEN (1<<0) /* UART enabled */
+#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
+#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
+#define UCR2_CTSC (1<<13) /* CTS pin control */
+#define UCR2_CTS (1<<12) /* Clear to send */
+#define UCR2_ESCEN (1<<11) /* Escape enable */
+#define UCR2_PREN (1<<8) /* Parity enable */
+#define UCR2_PROE (1<<7) /* Parity odd/even */
+#define UCR2_STPB (1<<6) /* Stop */
+#define UCR2_WS (1<<5) /* Word size */
+#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
+#define UCR2_TXEN (1<<2) /* Transmitter enabled */
+#define UCR2_RXEN (1<<1) /* Receiver enabled */
+#define UCR2_SRST (1<<0) /* SW reset */
+#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
+#define UCR3_PARERREN (1<<12) /* Parity enable */
+#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
+#define UCR3_DSR (1<<10) /* Data set ready */
+#define UCR3_DCD (1<<9) /* Data carrier detect */
+#define UCR3_RI (1<<8) /* Ring indicator */
+#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
+#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
+#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
+#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
+#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
+#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
+#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
+#define UCR3_BPEN (1<<0) /* Preset registers enable */
+#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
+#define UCR4_INVR (1<<9) /* Inverted infrared reception */
+#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
+#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
+#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
+#define UCR4_IRSC (1<<5) /* IR special case */
+#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
+#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
+#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
+#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
+#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
+#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
+#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
+#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
+#define USR1_RTSS (1<<14) /* RTS pin status */
+#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
+#define USR1_RTSD (1<<12) /* RTS delta */
+#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
+#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
+#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
+#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
+#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
+#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
+#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
+#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
+#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
+#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
+#define USR2_IDLE (1<<12) /* Idle condition */
+#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
+#define USR2_WAKE (1<<7) /* Wake */
+#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
+#define USR2_TXDC (1<<3) /* Transmitter complete */
+#define USR2_BRCD (1<<2) /* Break condition */
+#define USR2_ORE (1<<1) /* Overrun error */
+#define USR2_RDR (1<<0) /* Recv data ready */
+#define UTS_FRCPERR (1<<13) /* Force parity error */
+#define UTS_LOOP (1<<12) /* Loop tx and rx */
+#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
+#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
+#define UTS_TXFULL (1<<4) /* TxFIFO full */
+#define UTS_RXFULL (1<<3) /* RxFIFO full */
+#define UTS_SOFTRST (1<<0) /* Software reset */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void serial_setbrg(void)
+{
+ u32 clk = mx31_get_ipg_clk();
+
+ if (!gd->baudrate)
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
+ __REG(UART_PHYS + UBIR) = 0xf;
+ __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
+
+}
+
+int serial_getc(void)
+{
+ while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
+ return __REG(UART_PHYS + URXD);
+}
+
+void serial_putc(const char c)
+{
+ __REG(UART_PHYS + UTXD) = c;
+
+ /* wait for transmitter to be ready */
+ while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY));
+
+ /* If \n, also do \r */
+ if (c == '\n')
+ serial_putc('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer */
+int serial_tstc(void)
+{
+ /* If receive fifo is empty, return false */
+ if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+ return 0;
+ return 1;
+}
+
+void serial_puts(const char *s)
+{
+ while (*s) {
+ serial_putc(*s++);
+ }
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int serial_init(void)
+{
+ __REG(UART_PHYS + UCR1) = 0x0;
+ __REG(UART_PHYS + UCR2) = 0x0;
+
+ while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
+
+ __REG(UART_PHYS + UCR3) = 0x0704;
+ __REG(UART_PHYS + UCR4) = 0x8000;
+ __REG(UART_PHYS + UESC) = 0x002b;
+ __REG(UART_PHYS + UTIM) = 0x0;
+
+ __REG(UART_PHYS + UTS) = 0x0;
+
+ serial_setbrg();
+
+ __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | \
+ UCR2_TXEN | UCR2_SRST;
+
+ __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
+
+ return 0;
+}
+
+
+#endif /* CONFIG_MX31 */
diff --git a/cpu/bf561/Makefile b/cpu/arm1136/omap24xx/Makefile
index 418a437..39b0a82 100644
--- a/cpu/bf561/Makefile
+++ b/cpu/arm1136/omap24xx/Makefile
@@ -1,8 +1,5 @@
-# U-boot - Makefile
#
-# Copyright (c) 2005-2007 Analog Devices Inc.
-#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -10,34 +7,31 @@
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
+# published by the Free Software Foundatio; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(CPU).a
-
-SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
-COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o
+LIB = $(obj)lib$(SOC).a
-EXTRA = init_sdram_bootrom_initblock.o
+COBJS = interrupts.o
+SOBJS = start.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-START := $(addprefix $(obj),$(START))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
+all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
diff --git a/cpu/arm1136/interrupts.c b/cpu/arm1136/omap24xx/interrupts.c
index 491c902..8503b24 100644..100755
--- a/cpu/arm1136/interrupts.c
+++ b/cpu/arm1136/omap24xx/interrupts.c
@@ -32,31 +32,28 @@
#include <common.h>
#include <asm/arch/bits.h>
-
-#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
-# include <asm/arch/omap2420.h>
-#endif
+#include <asm/arch/omap2420.h>
#define TIMER_LOAD_VAL 0
/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR))
-
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
-/* Use the IntegratorCP function from board/integratorcp.c */
-#else
+#define READ_TIMER (*((volatile ulong*)(CFG_TIMERBASE+TCRR)))
static ulong timestamp;
static ulong lastinc;
-/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init (void)
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ */
+int interrupt_init(void)
{
int32_t val;
/* Start the counter ticking up */
- *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/
- val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/
+ /* reload value on overflow*/
+ *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;
+ /* mask to enable timer*/
+ val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0;
*((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */
reset_timer_masked(); /* init the timestamp and lastinc value */
@@ -66,82 +63,99 @@ int interrupt_init (void)
/*
* timer without interrupts
*/
-void reset_timer (void)
+void reset_timer(void)
{
- reset_timer_masked ();
+ reset_timer_masked();
}
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
- return get_timer_masked () - base;
+ return get_timer_masked() - base;
}
-void set_timer (ulong t)
+void set_timer(ulong t)
{
timestamp = t;
}
/* delay x useconds AND perserve advance timstamp value */
-void udelay (unsigned long usec)
+void udelay(unsigned long usec)
{
ulong tmo, tmp;
- if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- } else { /* else small number, don't kill it prior to HZ multiply */
+ /* if "big" number, spread normalization to seconds */
+ if (usec >= 1000) {
+ /* start to normalize for usec to ticks per sec */
+ tmo = usec / 1000;
+ /* find number of "ticks" to wait to achieve target */
+ tmo *= CFG_HZ;
+ /* finish normalize. */
+ tmo /= 1000;
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo /= (1000*1000);
}
-
- tmp = get_timer (0); /* get current timestamp */
- if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
- reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */
+ /* get current timestamp */
+ tmp = get_timer(0);
+ if ((tmo + tmp + 1) < tmp)
+ /* setting this forward will roll time stamp */
+ /* reset "advancing" timestamp to 0, set lastinc value */
+ reset_timer_masked();
else
- tmo += tmp; /* else, set advancing stamp wake up time */
- while (get_timer_masked () < tmo)/* loop till event */
+ /* else, set advancing stamp wake up time */
+ tmo += tmp;
+ while (get_timer_masked() < tmo)/* loop till event */
/*NOP*/;
}
-void reset_timer_masked (void)
+void reset_timer_masked(void)
{
/* reset time */
- lastinc = READ_TIMER; /* capture current incrementer value time */
- timestamp = 0; /* start "advancing" time stamp from 0 */
+ /* capture current incrementer value time */
+ lastinc = READ_TIMER;
+ /* start "advancing" time stamp from 0 */
+ timestamp = 0;
}
-ulong get_timer_masked (void)
+ulong get_timer_masked(void)
{
- ulong now = READ_TIMER; /* current tick value */
+ ulong now = READ_TIMER; /* current tick value */
- if (now >= lastinc) /* normal mode (non roll) */
- timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */
- else /* we have rollover of incrementer */
+ /* normal mode (non roll) */
+ if (now >= lastinc)
+ /* move stamp forward with absolute diff ticks */
+ timestamp += (now - lastinc);
+ else
+ /* we have rollover of incrementer */
timestamp += (0xFFFFFFFF - lastinc) + now;
lastinc = now;
return timestamp;
}
/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
+void udelay_masked(unsigned long usec)
{
ulong tmo;
ulong endtime;
signed long diff;
- if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- } else { /* else small number, don't kill it prior to HZ multiply */
+ if (usec >= 1000) {
+ /* "big" number, spread normalization to seconds */
+ /* start to normalize for usec to ticks per sec */
+ tmo = usec / 1000;
+ /* find number of "ticks" to wait to achieve target */
+ tmo *= CFG_HZ;
+ tmo /= 1000;/* finish normalize. */
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo /= (1000*1000);
}
- endtime = get_timer_masked () + tmo;
+ endtime = get_timer_masked() + tmo;
do {
- ulong now = get_timer_masked ();
+ ulong now = get_timer_masked();
diff = endtime - now;
} while (diff >= 0);
}
@@ -158,10 +172,9 @@ unsigned long long get_ticks(void)
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
-ulong get_tbclk (void)
+ulong get_tbclk(void)
{
ulong tbclk;
tbclk = CFG_HZ;
return tbclk;
}
-#endif /* !Integrator/CP */
diff --git a/cpu/arm1136/omap24xx/start.S b/cpu/arm1136/omap24xx/start.S
new file mode 100644
index 0000000..5634312
--- /dev/null
+++ b/cpu/arm1136/omap24xx/start.S
@@ -0,0 +1,42 @@
+/*
+ * armboot - Startup Code for OMP2420/ARM1136 CPU-core
+ *
+ * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
+ *
+ * Copyright (c) 2001 Marius Gr??ger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Z??pke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/omap2420.h>
+
+.globl reset_cpu
+reset_cpu:
+ ldr r1, rstctl /* get addr for global reset reg */
+ mov r3, #0x2 /* full reset pll+mpu */
+ str r3, [r1] /* force reset */
+ mov r0, r0
+_loop_forever:
+ b _loop_forever
+rstctl:
+ .word PM_RSTCTRL_WKUP
diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S
index 8b765f1..56009d0 100644
--- a/cpu/arm1136/start.S
+++ b/cpu/arm1136/start.S
@@ -30,9 +30,6 @@
#include <config.h>
#include <version.h>
-#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
-#include <asm/arch/omap2420.h>
-#endif
.globl _start
_start: b reset
#ifdef CONFIG_ONENAND_IPL
@@ -438,22 +435,4 @@ fiq:
arm1136_cache_flush:
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
mov pc, lr @ back to caller
-
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR)
-/* Use the IntegratorCP function from board/integratorcp/platform.S */
-#else
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r1, rstctl /* get addr for global reset reg */
- mov r3, #0x2 /* full reset pll+mpu */
- str r3, [r1] /* force reset */
- mov r0, r0
-_loop_forever:
- b _loop_forever
-rstctl:
- .word PM_RSTCTRL_WKUP
-
-#endif
#endif /* CONFIG_ONENAND_IPL */
diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S
index 1902bd0..98363eb 100644
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
@@ -46,7 +46,7 @@
#define MC_ASR 0xFFFFFF04
#define MC_AASR 0xFFFFFF08
#define EBI_CFGR 0xFFFFFF64
-#define SMC2_CSR 0xFFFFFF70
+#define SMC_CSR0 0xFFFFFF70
/* clocks */
#define PLLAR 0xFFFFFC28
@@ -146,8 +146,8 @@ SMRDATA:
.word MC_AASR_VAL
.word EBI_CFGR
.word EBI_CFGR_VAL
- .word SMC2_CSR
- .word SMC2_CSR_VAL
+ .word SMC_CSR0
+ .word SMC_CSR0_VAL
.word PLLAR
.word PLLAR_VAL
.word PLLBR
diff --git a/cpu/arm926ejs/at91cap9/spi.c b/cpu/arm926ejs/at91cap9/spi.c
deleted file mode 100644
index 0953820..0000000
--- a/cpu/arm926ejs/at91cap9/spi.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Driver for ATMEL DataFlash support
- * Author : Hamid Ikdoumi (Atmel)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/hardware.h>
-
-#ifdef CONFIG_HAS_DATAFLASH
-#include <dataflash.h>
-
-/* Max Value = 10MHz to be compliant to the Continuous Array Read function */
-#define AT91C_SPI_CLK 10000000
-
-/* AC Characteristics: DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
-#define DATAFLASH_TCSS (0xFA << 16)
-#define DATAFLASH_TCHS (0x8 << 24)
-
-#define AT91C_TIMEOUT_WRDY 200000
-#define AT91C_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
-#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
-
-void AT91F_SpiInit(void)
-{
- /* Reset the SPI */
- AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SWRST;
-
- /* Configure SPI in Master Mode with No CS selected !!! */
- AT91C_BASE_SPI0->SPI_MR =
- AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
-
- /* Configure CS0 */
- AT91C_BASE_SPI0->SPI_CSR[0] =
- AT91C_SPI_CPOL |
- (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
- (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
- ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-}
-
-void AT91F_SpiEnable(int cs)
-{
- switch (cs) {
- case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
- AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF;
- AT91C_BASE_SPI0->SPI_MR |=
- ((AT91C_SPI_PCS0_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
- break;
- case 3:
- AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF;
- AT91C_BASE_SPI0->SPI_MR |=
- ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
- break;
- }
-
- /* SPI_Enable */
- AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
-{
- unsigned int timeout;
-
- pDesc->state = BUSY;
-
- AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-
- /* Initialize the Transmit and Receive Pointer */
- AT91C_BASE_SPI0->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt;
- AT91C_BASE_SPI0->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt;
-
- /* Intialize the Transmit and Receive Counters */
- AT91C_BASE_SPI0->SPI_RCR = pDesc->rx_cmd_size;
- AT91C_BASE_SPI0->SPI_TCR = pDesc->tx_cmd_size;
-
- if (pDesc->tx_data_size != 0) {
- /* Initialize the Next Transmit and Next Receive Pointer */
- AT91C_BASE_SPI0->SPI_RNPR = (unsigned int)pDesc->rx_data_pt;
- AT91C_BASE_SPI0->SPI_TNPR = (unsigned int)pDesc->tx_data_pt;
-
- /* Intialize the Next Transmit and Next Receive Counters */
- AT91C_BASE_SPI0->SPI_RNCR = pDesc->rx_data_size;
- AT91C_BASE_SPI0->SPI_TNCR = pDesc->tx_data_size;
- }
-
- /* arm simple, non interrupt dependent timer */
- reset_timer_masked();
- timeout = 0;
-
- AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
- while (!(AT91C_BASE_SPI0->SPI_SR & AT91C_SPI_RXBUFF) &&
- ((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT));
- AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
- pDesc->state = IDLE;
-
- if (timeout >= CFG_SPI_WRITE_TOUT) {
- printf("Error Timeout\n\r");
- return DATAFLASH_ERROR;
- }
-
- return DATAFLASH_OK;
-}
-#endif
diff --git a/cpu/arm926ejs/at91cap9/Makefile b/cpu/arm926ejs/at91sam9/Makefile
index bf15e1e..203abc2 100644
--- a/cpu/arm926ejs/at91cap9/Makefile
+++ b/cpu/arm926ejs/at91sam9/Makefile
@@ -25,11 +25,14 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
-COBJS = ether.o timer.o spi.o usb.o
+COBJS-y += ether.o
+COBJS-y += timer.o
+COBJS-$(CONFIG_HAS_DATAFLASH) +=spi.o
+COBJS-y += usb.o
SOBJS = lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
all: $(obj).depend $(LIB)
diff --git a/cpu/arm926ejs/at91cap9/config.mk b/cpu/arm926ejs/at91sam9/config.mk
index ca2cae1..ca2cae1 100644
--- a/cpu/arm926ejs/at91cap9/config.mk
+++ b/cpu/arm926ejs/at91sam9/config.mk
diff --git a/cpu/arm926ejs/at91cap9/ether.c b/cpu/arm926ejs/at91sam9/ether.c
index b7958d5..e4f5601 100644
--- a/cpu/arm926ejs/at91cap9/ether.c
+++ b/cpu/arm926ejs/at91sam9/ether.c
@@ -23,13 +23,13 @@
*/
#include <common.h>
-#include <asm/arch/AT91CAP9.h>
+#include <asm/arch/hardware.h>
extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
-void at91cap9_eth_initialize(bd_t *bi)
+void at91sam9_eth_initialize(bd_t *bi)
{
- macb_eth_initialize(0, (void *)AT91C_BASE_MACB, 0x00);
+ macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
}
#endif
diff --git a/cpu/arm926ejs/at91cap9/lowlevel_init.S b/cpu/arm926ejs/at91sam9/lowlevel_init.S
index 24d950c..40a3f6a 100644
--- a/cpu/arm926ejs/at91cap9/lowlevel_init.S
+++ b/cpu/arm926ejs/at91sam9/lowlevel_init.S
@@ -1,5 +1,5 @@
/*
- * AT91CAP9 setup stuff
+ * AT91CAP9/SAM9 setup stuff
*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop <at> leadtechdesign.com>
diff --git a/cpu/arm926ejs/at91sam9/spi.c b/cpu/arm926ejs/at91sam9/spi.c
new file mode 100644
index 0000000..c9fe6d8
--- /dev/null
+++ b/cpu/arm926ejs/at91sam9/spi.c
@@ -0,0 +1,157 @@
+/*
+ * Driver for ATMEL DataFlash support
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_spi.h>
+
+#include <dataflash.h>
+
+#define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
+#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 0: NPCS0%1101 */
+#define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
+
+void AT91F_SpiInit(void)
+{
+ /* Reset the SPI */
+ writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR);
+
+ /* Configure SPI in Master Mode with No CS selected !!! */
+ writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
+ AT91_BASE_SPI + AT91_SPI_MR);
+
+ /* Configure CS0 */
+ writel(AT91_SPI_NCPHA |
+ (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
+ AT91_BASE_SPI + AT91_SPI_CSR(0));
+
+#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS1
+ /* Configure CS1 */
+ writel(AT91_SPI_NCPHA |
+ (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
+ AT91_BASE_SPI + AT91_SPI_CSR(1));
+#endif
+
+#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS3
+ /* Configure CS3 */
+ writel(AT91_SPI_NCPHA |
+ (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
+ AT91_BASE_SPI + AT91_SPI_CSR(3));
+#endif
+
+ /* SPI_Enable */
+ writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
+
+ while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS));
+
+ /*
+ * Add tempo to get SPI in a safe state.
+ * Should not be needed for new silicon (Rev B)
+ */
+ udelay(500000);
+ readl(AT91_BASE_SPI + AT91_SPI_SR);
+ readl(AT91_BASE_SPI + AT91_SPI_RDR);
+
+}
+
+void AT91F_SpiEnable(int cs)
+{
+ unsigned long mode;
+
+ switch (cs) {
+ case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
+ mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
+ mode &= 0xFFF0FFFF;
+ writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
+ AT91_BASE_SPI + AT91_SPI_MR);
+ break;
+ case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
+ mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
+ mode &= 0xFFF0FFFF;
+ writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
+ AT91_BASE_SPI + AT91_SPI_MR);
+ break;
+ case 3:
+ mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
+ mode &= 0xFFF0FFFF;
+ writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
+ AT91_BASE_SPI + AT91_SPI_MR);
+ break;
+ }
+
+ /* SPI_Enable */
+ writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
+}
+
+unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
+
+unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
+{
+ unsigned int timeout;
+
+ pDesc->state = BUSY;
+
+ writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
+
+ /* Initialize the Transmit and Receive Pointer */
+ writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR);
+ writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR);
+
+ /* Intialize the Transmit and Receive Counters */
+ writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR);
+ writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR);
+
+ if (pDesc->tx_data_size != 0) {
+ /* Initialize the Next Transmit and Next Receive Pointer */
+ writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR);
+ writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR);
+
+ /* Intialize the Next Transmit and Next Receive Counters */
+ writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR);
+ writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR);
+ }
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+ timeout = 0;
+
+ writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
+ while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
+ ((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT));
+ writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
+ pDesc->state = IDLE;
+
+ if (timeout >= CFG_SPI_WRITE_TOUT) {
+ printf("Error Timeout\n\r");
+ return DATAFLASH_ERROR;
+ }
+
+ return DATAFLASH_OK;
+}
diff --git a/cpu/arm926ejs/at91cap9/timer.c b/cpu/arm926ejs/at91sam9/timer.c
index 4110e15..4e79466 100644
--- a/cpu/arm926ejs/at91cap9/timer.c
+++ b/cpu/arm926ejs/at91sam9/timer.c
@@ -24,36 +24,35 @@
#include <common.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/io.h>
/*
- * We're using the AT91CAP9 PITC in 32 bit mode, by
+ * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
* setting the 20 bit counter period to its maximum (0xfffff).
*/
#define TIMER_LOAD_VAL 0xfffff
-#define READ_RESET_TIMER (AT91C_BASE_PITC->PITC_PIVR)
-#define READ_TIMER (AT91C_BASE_PITC->PITC_PIIR)
+#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR)
+#define READ_TIMER at91_sys_read(AT91_PIT_PIIR)
#define TIMER_FREQ (AT91C_MASTER_CLOCK << 4)
#define TICKS_TO_USEC(ticks) ((ticks) / 6)
ulong get_timer_masked(void);
ulong resettime;
-AT91PS_PITC p_pitc;
-
/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init(void)
+int timer_init(void)
{
/*
* Enable PITC Clock
* The clock is already enabled for system controller in boot
*/
- AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
/* Enable PITC */
- AT91C_BASE_PITC->PITC_PIMR = AT91C_PITC_PITEN;
-
- /* Load PITC_PIMR with the right timer value */
- AT91C_BASE_PITC->PITC_PIMR |= TIMER_LOAD_VAL;
+ at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN);
reset_timer_masked();
@@ -67,6 +66,7 @@ int interrupt_init(void)
static inline ulong get_timer_raw(void)
{
ulong now = READ_TIMER;
+
if (now >= resettime)
return now - resettime;
else
@@ -129,20 +129,20 @@ unsigned long long get_ticks(void)
ulong get_tbclk(void)
{
ulong tbclk;
+
tbclk = CFG_HZ;
return tbclk;
}
/*
- * Reset the cpu by setting up the watchdog timer and let him time out
- * on the AT91CAP9ADK board
+ * Reset the cpu by setting up the watchdog timer and let him time out.
*/
void reset_cpu(ulong ignored)
{
/* this is the way Linux does it */
- AT91C_BASE_RSTC->RSTC_RCR = (0xA5 << 24) |
- AT91C_RSTC_PROCRST |
- AT91C_RSTC_PERRST;
+ at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_PERRST);
while (1);
/* Never reached */
diff --git a/cpu/arm926ejs/at91cap9/usb.c b/cpu/arm926ejs/at91sam9/usb.c
index 69da5f3..d678897 100644
--- a/cpu/arm926ejs/at91cap9/usb.c
+++ b/cpu/arm926ejs/at91sam9/usb.c
@@ -24,15 +24,16 @@
#include <common.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
-#ifdef CONFIG_AT91CAP9
#include <asm/arch/hardware.h>
+#include <asm/arch/io.h>
+#include <asm/arch/at91_pmc.h>
int usb_cpu_init(void)
{
/* Enable USB host clock. */
- AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UHP;
- AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_UHP;
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP);
+ at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP);
return 0;
}
@@ -40,8 +41,8 @@ int usb_cpu_init(void)
int usb_cpu_stop(void)
{
/* Disable USB host clock. */
- AT91C_BASE_PMC->PMC_PCDR = 1 << AT91C_ID_UHP;
- AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_UHP;
+ at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP);
+ at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP);
return 0;
}
@@ -50,5 +51,4 @@ int usb_cpu_init_fail(void)
return usb_cpu_stop();
}
-#endif /* CONFIG_AT91CAP9 */
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/cpu/arm926ejs/davinci/lowlevel_init.S
index a87c112..79bc692 100644
--- a/cpu/arm926ejs/davinci/lowlevel_init.S
+++ b/cpu/arm926ejs/davinci/lowlevel_init.S
@@ -3,6 +3,11 @@
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
+ * Copyright (C) 2008 Prodrive BV <pv@prodrive.nl>
+ * Changed:
+ * Made board specific defines such as DDR timing and PLL
+ * dividers. These should be set in the board config file
+ *
* Partially based on TI sources, original copyrights follow:
*/
@@ -156,17 +161,17 @@ WaitPPL2Loop:
/* Program the PLL Multiplier */
ldr r6, PLL2_PLLM
- mov r2, $0x17 /* 162 MHz */
+ mov r2, $CFG_DAVINCI_PLL2_PLLM
str r2, [r6]
/* Program the PLL2 Divisor Value */
ldr r6, PLL2_DIV2
- mov r3, $0x01
+ mov r3, $CFG_DAVINCI_PLL2_DIV2
str r3, [r6]
/* Program the PLL2 Divisor Value */
ldr r6, PLL2_DIV1
- mov r4, $0x0b /* 54 MHz */
+ mov r4, $CFG_DAVINCI_PLL2_DIV1
str r4, [r6]
/* PLL2 DIV2 MMR */
@@ -273,7 +278,7 @@ checkDDRStatClkStop:
bne checkDDRStatClkStop
/*------------------------------------------------------*
- * Program DDR2 MMRs for 162MHz Setting *
+ * Program DDR2 MMRs *
*------------------------------------------------------*/
/* Program PHY Control Register */
@@ -288,12 +293,12 @@ checkDDRStatClkStop:
/* Program SDRAM TIM-0 Config Register */
ldr r6, SDTIM0
- ldr r7, SDTIM0_VAL_162MHz
+ ldr r7, SDTIM0_VAL
str r7, [r6]
/* Program SDRAM TIM-1 Config Register */
ldr r6, SDTIM1
- ldr r7, SDTIM1_VAL_162MHz
+ ldr r7, SDTIM1_VAL
str r7, [r6]
/* Program the SDRAM Bank Config Control Register */
@@ -435,7 +440,7 @@ WaitLoop:
/* Program the PLL Multiplier */
ldr r6, PLL1_PLLM
- mov r3, $0x15 /* For 594MHz */
+ mov r3, $CFG_DAVINCI_PLL1_PLLM
str r3, [r6]
/* Wait for PLL to Reset Properly */
@@ -467,7 +472,7 @@ PLL1Lock:
nop
/*------------------------------------------------------*
- * AEMIF configuration for NOR Flash (double check) *
+ * AEMIF configuration for NAND/NOR Flash *
*------------------------------------------------------*/
ldr r0, _PINMUX0
ldr r1, _DEV_SETTING
@@ -479,6 +484,12 @@ PLL1Lock:
orr r2, r2, r1
str r2, [r0]
+ ldr r0, ACFG2
+ ldr r1, ACFG2_VAL
+ ldr r2, [r0]
+ and r1, r2, r1
+ str r1, [r0]
+
ldr r0, ACFG3
ldr r1, ACFG3_VAL
ldr r2, [r0]
@@ -497,6 +508,12 @@ PLL1Lock:
and r1, r2, r1
str r1, [r0]
+ ldr r0, NANDFCR
+ ldr r1, NANDFCR_VAL
+ ldr r2, [r0]
+ and r1, r2, r1
+ str r1, [r0]
+
/*--------------------------------------*
* VTP manual Calibration *
*--------------------------------------*/
@@ -560,24 +577,36 @@ _PINMUX1:
.word 0x01c40004 /* Device Configuration Registers */
_DEV_SETTING:
- .word 0x00000c1f
+ .word CFG_DAVINCI_PINMUX_0
WAITCFG:
.word 0x01e00004
WAITCFG_VAL:
- .word 0
+ .word CFG_DAVINCI_WAITCFG
+ACFG2:
+ .word 0x01e00010
+ACFG2_VAL:
+ .word CFG_DAVINCI_ACFG2
ACFG3:
.word 0x01e00014
ACFG3_VAL:
- .word 0x3ffffffd
+ .word CFG_DAVINCI_ACFG3
ACFG4:
.word 0x01e00018
ACFG4_VAL:
- .word 0x3ffffffd
+ .word CFG_DAVINCI_ACFG4
ACFG5:
.word 0x01e0001c
ACFG5_VAL:
- .word 0x3ffffffd
+ .word CFG_DAVINCI_ACFG5
+NANDFCR:
+ .word 0x01e00060
+NANDFCR_VAL:
+#ifdef CFG_DAVINCI_NANDCE
+ .word (1 << (CFG_DAVINCI_NANDCE - 2))
+#else
+ .word 0x00000000
+#endif
MDCTL_DDR2:
.word 0x01c41a34
@@ -599,33 +628,27 @@ PSC_FLAG_CLEAR:
PSC_GEM_FLAG_CLEAR:
.word 0xfffffeff
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
+/* DDR2 MMR & CONFIGURATION VALUES */
DDRCTL:
.word 0x200000e4
DDRCTL_VAL:
- .word 0x50006405
+ .word CFG_DAVINCI_DDRCTL
SDREF:
.word 0x2000000c
SDREF_VAL:
- .word 0x000005c3
+ .word CFG_DAVINCI_SDREF
SDCFG:
.word 0x20000008
SDCFG_VAL:
-#ifdef DDR_4BANKS
- .word 0x00178622
-#elif defined DDR_8BANKS
- .word 0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
+ .word CFG_DAVINCI_SDCFG
SDTIM0:
.word 0x20000010
-SDTIM0_VAL_162MHz:
- .word 0x28923211
+SDTIM0_VAL:
+ .word CFG_DAVINCI_SDTIM0
SDTIM1:
.word 0x20000014
-SDTIM1_VAL_162MHz:
- .word 0x0016c722
+SDTIM1_VAL:
+ .word CFG_DAVINCI_SDTIM1
VTPIOCR:
.word 0x200000f0 /* VTP IO Control register */
DDRVTPR:
@@ -699,7 +722,7 @@ PLL2_DIV_MASK:
MMARG_BRF0:
.word 0x01c42010 /* BRF margin mode 0 (R/W)*/
MMARG_BRF0_VAL:
- .word 0x00444400
+ .word CFG_DAVINCI_MMARG_BRF0
DDR2_START_ADDR:
.word 0x80000000
diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c
index 127be9f..3257f83 100644
--- a/cpu/arm926ejs/davinci/nand.c
+++ b/cpu/arm926ejs/davinci/nand.c
@@ -117,7 +117,7 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
dummy = emif_addr->NANDF3ECC;
dummy = emif_addr->NANDF4ECC;
- emif_addr->NANDFCR |= (1 << 8);
+ emif_addr->NANDFCR |= (1 << (CFG_DAVINCI_NANDCE + 6));
}
static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
@@ -147,7 +147,7 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
- region = 1;
+ region = (CFG_DAVINCI_NANDCE - 1);
while (n--) {
tmp = nand_davinci_readecc(mtd, region);
*ecc_code++ = tmp;
@@ -311,40 +311,9 @@ static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, i
static void nand_flash_init(void)
{
- u_int32_t acfg1 = 0x3ffffffc;
- u_int32_t acfg2 = 0x3ffffffc;
- u_int32_t acfg3 = 0x3ffffffc;
- u_int32_t acfg4 = 0x3ffffffc;
- emifregs emif_regs;
-
- /*------------------------------------------------------------------*
- * NAND FLASH CHIP TIMEOUT @ 459 MHz *
- * *
- * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
- * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
- * *
- *------------------------------------------------------------------*/
- acfg1 = 0
- | (0 << 31 ) /* selectStrobe */
- | (0 << 30 ) /* extWait */
- | (1 << 26 ) /* writeSetup 10 ns */
- | (3 << 20 ) /* writeStrobe 40 ns */
- | (1 << 17 ) /* writeHold 10 ns */
- | (1 << 13 ) /* readSetup 10 ns */
- | (5 << 7 ) /* readStrobe 60 ns */
- | (1 << 4 ) /* readHold 10 ns */
- | (3 << 2 ) /* turnAround ?? ns */
- | (0 << 0 ) /* asyncSize 8-bit bus */
- ;
-
- emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
- emif_regs->AWCCR |= 0x10000000;
- emif_regs->AB1CR = acfg1; /* 0x08244128 */;
- emif_regs->AB2CR = acfg2;
- emif_regs->AB3CR = acfg3;
- emif_regs->AB4CR = acfg4;
- emif_regs->NANDFCR = 0x00000101;
+ /* All EMIF initialization is done in lowlevel_init.S
+ * and config values are in the board config files
+ */
}
int board_nand_init(struct nand_chip *nand)
diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c
index 8bb8b45..4797797 100644
--- a/cpu/arm926ejs/davinci/timer.c
+++ b/cpu/arm926ejs/davinci/timer.c
@@ -42,9 +42,9 @@
typedef volatile struct {
u_int32_t pid12;
- u_int32_t emumgt_clksped;
- u_int32_t gpint_en;
- u_int32_t gpdir_dat;
+ u_int32_t emumgt;
+ u_int32_t na1;
+ u_int32_t na2;
u_int32_t tim12;
u_int32_t tim34;
u_int32_t prd12;
@@ -52,21 +52,12 @@ typedef volatile struct {
u_int32_t tcr;
u_int32_t tgcr;
u_int32_t wdtcr;
- u_int32_t tlgc;
- u_int32_t tlmr;
} davinci_timer;
davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE;
#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ)
-#define READ_TIMER timer->tim34
-
-/*
- * Timer runs with CFG_HZ_CLOCK, currently 27MHz. To avoid wrap
- * around of timestamp already after min ~159s, divide it, e.g. by 16.
- * timestamp will then wrap around all min ~42min
- */
-#define DIV(x) ((x) >> 4)
+#define TIM_CLK_DIV 16
static ulong timestamp;
static ulong lastinc;
@@ -76,63 +67,50 @@ int timer_init(void)
/* We are using timer34 in unchained 32-bit mode, full speed */
timer->tcr = 0x0;
timer->tgcr = 0x0;
- timer->tgcr = 0x06;
+ timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8);
timer->tim34 = 0x0;
timer->prd34 = TIMER_LOAD_VAL;
lastinc = 0;
- timer->tcr = 0x80 << 16;
timestamp = 0;
+ timer->tcr = 2 << 22;
return(0);
}
void reset_timer(void)
{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- return(get_timer_masked() - base);
-}
-
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
-void udelay(unsigned long usec)
-{
- udelay_masked(usec);
-}
-
-void reset_timer_masked(void)
-{
- lastinc = DIV(READ_TIMER);
+ timer->tcr = 0x0;
+ timer->tim34 = 0;
+ lastinc = 0;
timestamp = 0;
+ timer->tcr = 2 << 22;
}
-ulong get_timer_raw(void)
+static ulong get_timer_raw(void)
{
- ulong now = DIV(READ_TIMER);
+ ulong now = timer->tim34;
if (now >= lastinc) {
/* normal mode */
timestamp += now - lastinc;
} else {
/* overflow ... */
- timestamp += now + DIV(TIMER_LOAD_VAL) - lastinc;
+ timestamp += now + TIMER_LOAD_VAL - lastinc;
}
lastinc = now;
return timestamp;
}
-ulong get_timer_masked(void)
+ulong get_timer(ulong base)
+{
+ return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base); }
+
+void set_timer(ulong t)
{
- return(get_timer_raw() / DIV(TIMER_LOAD_VAL));
+ timestamp = t;
}
-void udelay_masked(unsigned long usec)
+void udelay(unsigned long usec)
{
ulong tmo;
ulong endtime;
@@ -140,7 +118,7 @@ void udelay_masked(unsigned long usec)
tmo = CFG_HZ_CLOCK / 1000;
tmo *= usec;
- tmo /= 1000;
+ tmo /= (1000 * TIM_CLK_DIV);
endtime = get_timer_raw() + tmo;
@@ -165,8 +143,5 @@ unsigned long long get_ticks(void)
*/
ulong get_tbclk(void)
{
- ulong tbclk;
-
- tbclk = CFG_HZ;
- return(tbclk);
+ return CFG_HZ;
}
diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c
index 0971fea..1819f6b 100644
--- a/cpu/arm926ejs/interrupts.c
+++ b/cpu/arm926ejs/interrupts.c
@@ -38,7 +38,7 @@
#include <common.h>
#include <arm926ejs.h>
-#if defined(CONFIG_INTEGRATOR) || defined(CONFIG_AT91CAP9ADK)
+#ifdef CONFIG_INTEGRATOR
/* Timer functionality supplied by Integrator board (AP or CP) */
diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h
deleted file mode 100644
index 9970b72..0000000
--- a/cpu/bf533/bf533_serial.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * U-boot - bf533_serial.h Serial Driver defines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
- * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl>
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on:
- * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
- *
- * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com
- * Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328serial.c which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _Bf533_SERIAL_H
-#define _Bf533_SERIAL_H
-
-#include <linux/config.h>
-#include <asm/blackfin.h>
-
-#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
-#define ACCESS_LATCH *pUART_LCR |= DLAB;
-#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB);
-
-void serial_setbrg(void);
-static void local_put_char(char ch);
-void calc_baud(void);
-void serial_setbrg(void);
-int serial_init(void);
-void serial_putc(const char c);
-int serial_tstc(void);
-int serial_getc(void);
-void serial_puts(const char *s);
-static void local_put_char(char ch);
-
-int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
-
-struct {
- unsigned char dl_high;
- unsigned char dl_low;
-} hw_baud_table[5];
-
-#ifdef CONFIG_STAMP
-extern unsigned long pll_div_fact;
-#endif
-
-#endif
diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S
deleted file mode 100644
index d9015c6..0000000
--- a/cpu/bf533/cache.S
+++ /dev/null
@@ -1,129 +0,0 @@
-#define ASSEMBLY
-#include <asm/linkage.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/mpu.h>
-
-.text
-.align 2
-ENTRY(_blackfin_icache_flush_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
- 1:
- IFLUSH[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
- IFLUSH[P0];
- SSYNC;
- RTS;
-
-ENTRY(_blackfin_dcache_flush_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
-1:
- FLUSH[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
- FLUSH[P0];
- SSYNC;
- RTS;
-
-ENTRY(_icache_invalidate)
-ENTRY(_invalidate_entire_icache)
- [--SP] = (R7:5);
-
- P0.L = (IMEM_CONTROL & 0xFFFF);
- P0.H = (IMEM_CONTROL >> 16);
- R7 =[P0];
-
- /*
- * Clear the IMC bit , All valid bits in the instruction
- * cache are set to the invalid state
- */
- BITCLR(R7, IMC_P);
- CLI R6;
- /* SSYNC required before invalidating cache. */
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- /* Configures the instruction cache agian */
- R6 = (IMC | ENICPLB);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- (R7:5) =[SP++];
- RTS;
-
-/*
- * Invalidate the Entire Data cache by
- * clearing DMC[1:0] bits
- */
-ENTRY(_invalidate_entire_dcache)
-ENTRY(_dcache_invalidate)
- [--SP] = (R7:6);
-
- P0.L = (DMEM_CONTROL & 0xFFFF);
- P0.H = (DMEM_CONTROL >> 16);
- R7 =[P0];
-
- /*
- * Clear the DMC[1:0] bits, All valid bits in the data
- * cache are set to the invalid state
- */
- BITCLR(R7, DMC0_P);
- BITCLR(R7, DMC1_P);
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
- /* Configures the data cache again */
-
- R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- (R7:6) =[SP++];
- RTS;
-
-ENTRY(_blackfin_dcache_invalidate_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
-1:
- FLUSHINV[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
-
- /*
- * If the data crosses a cache line, then we'll be pointing to
- * the last cache line, but won't have flushed/invalidated it yet, so do
- * one more.
- */
- FLUSHINV[P0];
- SSYNC;
- RTS;
diff --git a/cpu/bf533/config.mk b/cpu/bf533/config.mk
deleted file mode 100644
index 2caa3cc..0000000
--- a/cpu/bf533/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-# U-boot - config.mk
-#
-# Copyright (c) 2005-2007 Analog Devices Inc.
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-PLATFORM_RELFLAGS += -mcpu=bf533
diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c
deleted file mode 100644
index edb771e..0000000
--- a/cpu/bf533/cpu.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * U-boot - cpu.c CPU specific functions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <command.h>
-#include <asm/entry.h>
-#include <asm/cplb.h>
-#include <asm/io.h>
-
-#define CACHE_ON 1
-#define CACHE_OFF 0
-
-extern unsigned int icplb_table[page_descriptor_table_size][2];
-extern unsigned int dcplb_table[page_descriptor_table_size][2];
-
-int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
- );
-
- return 0;
-}
-
-/* These functions are just used to satisfy the linker */
-int cpu_init(void)
-{
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- return 0;
-}
-
-void icache_enable(void)
-{
- unsigned int *I0, *I1;
- int i, j = 0;
-
- /* Before enable icache, disable it first */
- icache_disable();
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
-
- /* make sure the locked ones go in first */
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (CPLB_LOCK & icplb_table[i][1]) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- icplb_table[i][0], icplb_table[i][1]);
- *I0++ = icplb_table[i][0];
- *I1++ = icplb_table[i][1];
- j++;
- }
- }
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (!(CPLB_LOCK & icplb_table[i][1])) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- icplb_table[i][0], icplb_table[i][1]);
- *I0++ = icplb_table[i][0];
- *I1++ = icplb_table[i][1];
- j++;
- if (j == 16) {
- break;
- }
- }
- }
-
- /* Fill the rest with invalid entry */
- if (j <= 15) {
- for (; j < 16; j++) {
- debug("filling %i with 0", j);
- *I1++ = 0x0;
- }
-
- }
-
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
- SSYNC();
-}
-
-void icache_disable(void)
-{
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
- SSYNC();
-}
-
-int icache_status(void)
-{
- unsigned int value;
- value = *(unsigned int *)IMEM_CONTROL;
-
- if (value & (IMC | ENICPLB))
- return CACHE_ON;
- else
- return CACHE_OFF;
-}
-
-void dcache_enable(void)
-{
- unsigned int *I0, *I1;
- unsigned int temp;
- int i, j = 0;
-
- /* Before enable dcache, disable it first */
- dcache_disable();
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
-
- /* make sure the locked ones go in first */
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (CPLB_LOCK & dcplb_table[i][1]) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- *I0++ = dcplb_table[i][0];
- *I1++ = dcplb_table[i][1];
- j++;
- } else {
- debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- }
- }
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (!(CPLB_LOCK & dcplb_table[i][1])) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- *I0++ = dcplb_table[i][0];
- *I1++ = dcplb_table[i][1];
- j++;
- if (j == 16) {
- break;
- }
- }
- }
-
- /* Fill the rest with invalid entry */
- if (j <= 15) {
- for (; j < 16; j++) {
- debug("filling %i with 0", j);
- *I1++ = 0x0;
- }
- }
-
- temp = *(unsigned int *)DMEM_CONTROL;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL =
- ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
- SSYNC();
-}
-
-void dcache_disable(void)
-{
- unsigned int *I0, *I1;
- int i;
-
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL &=
- ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
-
- /* after disable dcache,
- * clear it so we don't confuse the next application
- */
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
-
- for (i = 0; i < 16; i++) {
- *I0++ = 0x0;
- *I1++ = 0x0;
- }
-}
-
-int dcache_status(void)
-{
- unsigned int value;
- value = *(unsigned int *)DMEM_CONTROL;
- if (value & (ENDCPLB))
- return CACHE_ON;
- else
- return CACHE_OFF;
-}
diff --git a/cpu/bf533/cpu.h b/cpu/bf533/cpu.h
deleted file mode 100644
index b6b73b1..0000000
--- a/cpu/bf533/cpu.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * U-boot - cpu.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _CPU_H_
-#define _CPU_H_
-
-#include <command.h>
-
-#define INTERNAL_IRQS (32)
-#define NUM_IRQ_NODES 16
-#define DEF_INTERRUPT_FLAGS 1
-#define MAX_TIM_LOAD 0xFFFFFFFF
-
-void blackfin_irq_panic(int reason, struct pt_regs *reg);
-extern void dump(struct pt_regs *regs);
-void display_excp(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_exception(void);
-asmlinkage void trap(void);
-asmlinkage void evt_ivhw(void);
-asmlinkage void evt_rst(void);
-asmlinkage void evt_timer(void);
-asmlinkage void evt_evt7(void);
-asmlinkage void evt_evt8(void);
-asmlinkage void evt_evt9(void);
-asmlinkage void evt_evt10(void);
-asmlinkage void evt_evt11(void);
-asmlinkage void evt_evt12(void);
-asmlinkage void evt_evt13(void);
-asmlinkage void evt_soft_int1(void);
-asmlinkage void evt_system_call(void);
-void blackfin_irq_panic(int reason, struct pt_regs *regs);
-void blackfin_free_irq(unsigned int irq, void *dev_id);
-void call_isr(int irq, struct pt_regs *fp);
-void blackfin_do_irq(int vec, struct pt_regs *fp);
-void blackfin_init_IRQ(void);
-void blackfin_enable_irq(unsigned int irq);
-void blackfin_disable_irq(unsigned int irq);
-extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
-int blackfin_request_irq(unsigned int irq,
- void (*handler) (int, void *, struct pt_regs *),
- unsigned long flags, const char *devname,
- void *dev_id);
-void timer_init(void);
-#endif
diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S
deleted file mode 100644
index 62e3d65..0000000
--- a/cpu/bf533/flush.S
+++ /dev/null
@@ -1,405 +0,0 @@
-/* Copyright (C) 2003-2007 Analog Devices Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.
- */
-
-#define ASSEMBLY
-
-#include <asm/linkage.h>
-#include <asm/cplb.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-.text
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the instruction cache.
- */
-
-ENTRY(_flush_instruction_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = (ICPLB_ADDR0 >> 16);
- P5.L = (ICPLB_ADDR0 & 0xFFFF);
- P4.H = (ICPLB_DATA0 >> 16);
- P4.L = (ICPLB_DATA0 & 0xFFFF);
- R7 = CPLB_VALID | CPLB_L1_CHBL;
- R6 = 16;
-inext: R0 = [P5++];
- R1 = [P4++];
- [--SP] = RETS;
- CALL _icplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-iskip: R6 += -1;
- CC = R6;
- IF CC JUMP inext;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular ICPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_icplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP iflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /* Anamoly 05000209 */
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */
-
- /* Save in extraction pattern for later deposit. */
- R3.H = R4.L << 0;
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = (ITEST_COMMAND & 0xFFFF);
- P5.H = (ITEST_COMMAND >> 16);
- P4.L = (ITEST_DATA0 & 0xFFFF);
- P4.H = (ITEST_DATA0 >> 16);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 4;
- LSETUP (ifs1, ife1) LC1 = P2;
-ifs1: P0 = 32; /* iterate over all sets*/
- LSETUP (ifs0, ife0) LC0 = P0;
-ifs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- [P5] = R6; /* Issue Command*/
- SSYNC; /* CSYNC will not work here :(*/
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP ifskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- IFLUSH [P3]; /* And flush the entry*/
-ifskip:
-ife0: R5 += 1; /* Advance to next Set*/
-ife1: NOP;
-
-ifinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-iflush_whole_page:
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- IFLUSH [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (isall, ieall) LC0 = P1;
-isall:
- IFLUSH [P0++];
-ieall:
- NOP;
- SSYNC;
- JUMP ifinished;
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the data cache.
- */
-
-ENTRY(_flush_data_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = (DCPLB_ADDR0 >> 16);
- P5.L = (DCPLB_ADDR0 & 0xFFFF);
- P4.H = (DCPLB_DATA0 >> 16);
- P4.L = (DCPLB_DATA0 & 0xFFFF);
- R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
- R6 = 16;
-next: R0 = [P5++];
- R1 = [P4++];
- CC = BITTST(R1, 14); /* Is it write-through?*/
- IF CC JUMP skip; /* If so, ignore it.*/
- R2 = R1 & R7; /* Is it a dirty, cached page?*/
- CC = R2;
- IF !CC JUMP skip; /* If not, ignore it.*/
- [--SP] = RETS;
- CALL _dcplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-skip: R6 += -1;
- CC = R6;
- IF CC JUMP next;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular DCPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_dcplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP dflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* The page could be mapped into Bank A or Bank B, depending
- * on (a) whether both banks are configured as cache, and
- * (b) on whether address bit A[x] is set. x is determined
- * by DCBS in DMEM_CONTROL
- */
-
- R2 = 0; /* Default to Bank A (Bank B would be 1)*/
-
- P0.L = (DMEM_CONTROL & 0xFFFF);
- P0.H = (DMEM_CONTROL >> 16);
-
- R3 = [P0]; /* If Bank B is not enabled as cache*/
- CC = BITTST(R3, 2); /* then Bank A is our only option.*/
- IF CC JUMP bank_chosen;
-
- R4 = 1<<14; /* If DCBS==0, use A[14].*/
- R5 = R4 << 7; /* If DCBS==1, use A[23];*/
- CC = BITTST(R3, 4);
- IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
- R5 = R0 & R4; /* Use it to test the Page address*/
- CC = R5; /* and if that bit is set, we use Bank B,*/
- R2 = CC; /* else we use Bank A.*/
- R2 <<= 23; /* The Bank selection's at posn 23.*/
-
-bank_chosen:
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /*Anamoly 05000209*/
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
- /* Save in extraction pattern for later deposit.*/
- R3.H = R4.L << 0;
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R2 = Bank select mask
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = (DTEST_COMMAND & 0xFFFF);
- P5.H = (DTEST_COMMAND >> 16);
- P4.L = (DTEST_DATA0 & 0xFFFF);
- P4.H = (DTEST_DATA0 >> 16);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 2;
- LSETUP (fs1, fe1) LC1 = P2;
-fs1: P0 = 64; /* iterate over all sets*/
- LSETUP (fs0, fe0) LC0 = P0;
-fs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
- BITSET(R6,14);
- [P5] = R6; /* Issue Command*/
- SSYNC;
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP fskip; /* and skip if not.*/
- CC = BITTST(R7, 1); /* Check if dirty*/
- IF !CC JUMP fskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP fskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- SSYNC;
- FLUSHINV [P3]; /* And flush the entry*/
-fskip:
-fe0: R5 += 1; /* Advance to next Set*/
-fe1: BITSET(R2, 26); /* Go to next Way.*/
-
-dfinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-dflush_whole_page:
-
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (eall, eall) LC0 = P1;
-eall: FLUSHINV [P0++];
- SSYNC;
- JUMP dfinished;
-
-.align 4;
-page_prefix_table:
-.byte4 0xFFFFFC00; /* 1K */
-.byte4 0xFFFFF000; /* 4K */
-.byte4 0xFFF00000; /* 1M */
-.byte4 0xFFC00000; /* 4M */
-.page_prefix_table.end:
diff --git a/cpu/bf533/init_sdram.S b/cpu/bf533/init_sdram.S
deleted file mode 100644
index 67a99e4..0000000
--- a/cpu/bf533/init_sdram.S
+++ /dev/null
@@ -1,183 +0,0 @@
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
-.global init_sdram;
-
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-
-init_sdram:
- [--SP] = ASTAT;
- [--SP] = RETS;
- [--SP] = (R7:0);
- [--SP] = (P5:0);
-
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
- p0.h = hi(SPI_BAUD);
- p0.l = lo(SPI_BAUD);
- r0.l = CONFIG_SPI_BAUD;
- w[p0] = r0.l;
- SSYNC;
-#endif
-
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over, */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-
- /*
- * We now are running at speed, time to set the Async mem bank wait states
- * This will speed up execution, since we are normally running from FLASH.
- */
-
- p2.h = (EBIU_AMBCTL1 >> 16);
- p2.l = (EBIU_AMBCTL1 & 0xFFFF);
- r0.h = (AMBCTL1VAL >> 16);
- r0.l = (AMBCTL1VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMBCTL0 >> 16);
- p2.l = (EBIU_AMBCTL0 & 0xFFFF);
- r0.h = (AMBCTL0VAL >> 16);
- r0.l = (AMBCTL0VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMGCTL >> 16);
- p2.l = (EBIU_AMGCTL & 0xffff);
- r0 = AMGCTLVAL;
- w[p2] = r0;
- ssync;
-
- /*
- * Now, Initialize the SDRAM,
- * start with the SDRAM Refresh Rate Control Register
- */
- p0.l = lo(EBIU_SDRRC);
- p0.h = hi(EBIU_SDRRC);
- r0 = mem_SDRRC;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Memory Bank Control Register - bank specific parameters
- */
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16);
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Global Control Register - global programmable parameters
- * Disable self-refresh
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITCLR (R0, 24);
-
- /*
- * Check if SDRAM is already powered up, if it is, enable self-refresh
- */
- p0.h = hi(EBIU_SDSTAT);
- p0.l = lo(EBIU_SDSTAT);
- r2.l = w[p0];
- cc = bittst(r2,3);
- if !cc jump skip;
- NOP;
- BITSET (R0, 23);
-skip:
- [P2] = R0;
- SSYNC;
-
- /* Write in the new value in the register */
- R0.L = lo(mem_SDGCTL);
- R0.H = hi(mem_SDGCTL);
- [P2] = R0;
- SSYNC;
- nop;
-
- (P5:0) = [SP++];
- (R7:0) = [SP++];
- RETS = [SP++];
- ASTAT = [SP++];
- RTS;
diff --git a/cpu/bf533/init_sdram_bootrom_initblock.S b/cpu/bf533/init_sdram_bootrom_initblock.S
deleted file mode 100644
index 8694ca2..0000000
--- a/cpu/bf533/init_sdram_bootrom_initblock.S
+++ /dev/null
@@ -1,183 +0,0 @@
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
-.global init_sdram;
-
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-
-init_sdram:
- [--SP] = ASTAT;
- [--SP] = RETS;
- [--SP] = (R7:0);
- [--SP] = (P5:0);
-
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
- p0.h = hi(SPI_BAUD);
- p0.l = lo(SPI_BAUD);
- r0.l = CONFIG_SPI_BAUD_INITBLOCK;
- w[p0] = r0.l;
- SSYNC;
-#endif
-
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over, */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-
- /*
- * We now are running at speed, time to set the Async mem bank wait states
- * This will speed up execution, since we are normally running from FLASH.
- */
-
- p2.h = (EBIU_AMBCTL1 >> 16);
- p2.l = (EBIU_AMBCTL1 & 0xFFFF);
- r0.h = (AMBCTL1VAL >> 16);
- r0.l = (AMBCTL1VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMBCTL0 >> 16);
- p2.l = (EBIU_AMBCTL0 & 0xFFFF);
- r0.h = (AMBCTL0VAL >> 16);
- r0.l = (AMBCTL0VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMGCTL >> 16);
- p2.l = (EBIU_AMGCTL & 0xffff);
- r0 = AMGCTLVAL;
- w[p2] = r0;
- ssync;
-
- /*
- * Now, Initialize the SDRAM,
- * start with the SDRAM Refresh Rate Control Register
- */
- p0.l = lo(EBIU_SDRRC);
- p0.h = hi(EBIU_SDRRC);
- r0 = mem_SDRRC;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Memory Bank Control Register - bank specific parameters
- */
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16);
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Global Control Register - global programmable parameters
- * Disable self-refresh
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITCLR (R0, 24);
-
- /*
- * Check if SDRAM is already powered up, if it is, enable self-refresh
- */
- p0.h = hi(EBIU_SDSTAT);
- p0.l = lo(EBIU_SDSTAT);
- r2.l = w[p0];
- cc = bittst(r2,3);
- if !cc jump skip;
- NOP;
- BITSET (R0, 23);
-skip:
- [P2] = R0;
- SSYNC;
-
- /* Write in the new value in the register */
- R0.L = lo(mem_SDGCTL);
- R0.H = hi(mem_SDGCTL);
- [P2] = R0;
- SSYNC;
- nop;
-
- (P5:0) = [SP++];
- (R7:0) = [SP++];
- RETS = [SP++];
- ASTAT = [SP++];
- RTS;
diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S
deleted file mode 100644
index 7556ec9..0000000
--- a/cpu/bf533/interrupt.S
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * U-boot - interrupt.S Processing of interrupts and exception handling
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on interrupt.S
- *
- * Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com>
- * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- *
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * This file is also based on exception.asm
- * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#define ASSEMBLY
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/entry.h>
-
-.global _blackfin_irq_panic;
-
-.text
-.align 2
-
-#ifndef CONFIG_KGDB
-.global _evt_emulation
-_evt_emulation:
- SAVE_CONTEXT
- r0 = 0;
- r1 = seqstat;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
- rte;
-#endif
-
-.global _evt_nmi
-_evt_nmi:
- SAVE_CONTEXT
- r0 = 2;
- r1 = RETN;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
-
-_evt_nmi_exit:
- rtn;
-
-.global _trap
-_trap:
- SAVE_ALL_SYS
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- sp += -12;
- call _trap_c
- sp += 12;
- RESTORE_ALL_SYS
- rtx;
-
-.global _evt_rst
-_evt_rst:
- SAVE_CONTEXT
- r0 = 1;
- r1 = RETN;
- sp += -12;
- call _do_reset;
- sp += 12;
-
-_evt_rst_exit:
- rtn;
-
-irq_panic:
- r0 = 3;
- r1 = sp;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
-
-.global _evt_ivhw
-_evt_ivhw:
- SAVE_CONTEXT
- RAISE 14;
-
-_evt_ivhw_exit:
- rti;
-
-.global _evt_timer
-_evt_timer:
- SAVE_CONTEXT
- r0 = 6;
- sp += -12;
- /* Polling method used now. */
- /* call timer_int; */
- sp += 12;
- RESTORE_CONTEXT
- rti;
- nop;
-
-.global _evt_evt7
-_evt_evt7:
- SAVE_CONTEXT
- r0 = 7;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt7_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt8
-_evt_evt8:
- SAVE_CONTEXT
- r0 = 8;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt8_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt9
-_evt_evt9:
- SAVE_CONTEXT
- r0 = 9;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt9_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt10
-_evt_evt10:
- SAVE_CONTEXT
- r0 = 10;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt10_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt11
-_evt_evt11:
- SAVE_CONTEXT
- r0 = 11;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt11_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt12
-_evt_evt12:
- SAVE_CONTEXT
- r0 = 12;
- sp += -12;
- call _process_int;
- sp += 12;
-evt_evt12_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt13
-_evt_evt13:
- SAVE_CONTEXT
- r0 = 13;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt13_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_system_call
-_evt_system_call:
- [--sp] = r0;
- [--SP] = RETI;
- r0 = [sp++];
- r0 += 2;
- [--sp] = r0;
- RETI = [SP++];
- r0 = [SP++];
- SAVE_CONTEXT
- sp += -12;
- call _exception_handle;
- sp += 12;
- RESTORE_CONTEXT
- RTI;
-
-evt_system_call_exit:
- rti;
-
-.global _evt_soft_int1
-_evt_soft_int1:
- [--sp] = r0;
- [--SP] = RETI;
- r0 = [sp++];
- r0 += 2;
- [--sp] = r0;
- RETI = [SP++];
- r0 = [SP++];
- SAVE_CONTEXT
- sp += -12;
- call _exception_handle;
- sp += 12;
- RESTORE_CONTEXT
- RTI;
-
-evt_soft_int1_exit:
- rti;
diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c
deleted file mode 100644
index 3d1c3bc..0000000
--- a/cpu/bf533/interrupts.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * U-boot - interrupts.c Interrupt related routines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on interrupts.c
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-static ulong timestamp;
-static ulong last_time;
-static int int_flag;
-
-int irq_flags; /* needed by asm-blackfin/system.h */
-
-/* Functions just to satisfy the linker */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On BF533 it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On BF533 it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- ulong tbclk;
-
- tbclk = CFG_HZ;
- return tbclk;
-}
-
-void enable_interrupts(void)
-{
-}
-
-int disable_interrupts(void)
-{
- return 1;
-}
-
-int interrupt_init(void)
-{
- return (0);
-}
-
-void udelay(unsigned long usec)
-{
- unsigned long delay, start, stop;
- unsigned long cclk;
- cclk = (CONFIG_CCLK_HZ);
-
- while (usec > 1) {
- /*
- * how many clock ticks to delay?
- * - request(in useconds) * clock_ticks(Hz) / useconds/second
- */
- if (usec < 1000) {
- delay = (usec * (cclk / 244)) >> 12;
- usec = 0;
- } else {
- delay = (1000 * (cclk / 244)) >> 12;
- usec -= 1000;
- }
-
- asm volatile (" %0 = CYCLES;":"=r" (start));
- do {
- asm volatile (" %0 = CYCLES; ":"=r" (stop));
- } while (stop - start < delay);
- }
-
- return;
-}
-
-void timer_init(void)
-{
- *pTCNTL = 0x1;
- *pTSCALE = 0x0;
- *pTCOUNT = MAX_TIM_LOAD;
- *pTPERIOD = MAX_TIM_LOAD;
- *pTCNTL = 0x7;
- asm("CSYNC;");
-
- timestamp = 0;
- last_time = 0;
-}
-
-/* Any network command or flash
- * command is started get_timer shall
- * be called before TCOUNT gets reset,
- * to implement the accurate timeouts.
- *
- * How ever milliconds doesn't return
- * the number that has been elapsed from
- * the last reset.
- *
- * As get_timer is used in the u-boot
- * only for timeouts this should be
- * sufficient
- */
-ulong get_timer(ulong base)
-{
- ulong milisec;
-
- /* Number of clocks elapsed */
- ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
-
- /**
- * Find if the TCOUNT is reset
- * timestamp gives the number of times
- * TCOUNT got reset
- */
- if (clocks < last_time)
- timestamp++;
- last_time = clocks;
-
- /* Get the number of milliseconds */
- milisec = clocks / (CONFIG_CCLK_HZ / 1000);
-
- /**
- * Find the number of millisonds
- * that got elapsed before this TCOUNT cycle
- */
- milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
-
- return (milisec - base);
-}
diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c
deleted file mode 100644
index 05d9a1b..0000000
--- a/cpu/bf533/ints.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * U-boot - ints.c Interrupt related routines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on ints.c
- *
- * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
- * drivers
- *
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <linux/stddef.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-void blackfin_irq_panic(int reason, struct pt_regs *regs)
-{
- printf("\n\nException: IRQ 0x%x entered\n", reason);
- printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
- printf("stack frame=0x%x, ", (unsigned int)regs);
- printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
- dump(regs);
- printf("Unhandled IRQ or exceptions!\n");
- printf("Please reset the board \n");
-}
-
-void blackfin_init_IRQ(void)
-{
- *(unsigned volatile long *)(SIC_IMASK) = 0;
-#ifndef CONFIG_KGDB
- *(unsigned volatile long *)(EVT1) = 0x0;
-#endif
- *(unsigned volatile long *)(EVT2) =
- (unsigned volatile long)evt_nmi;
- *(unsigned volatile long *)(EVT3) =
- (unsigned volatile long)trap;
- *(unsigned volatile long *)(EVT5) =
- (unsigned volatile long)evt_ivhw;
- *(unsigned volatile long *)(EVT0) =
- (unsigned volatile long)evt_rst;
- *(unsigned volatile long *)(EVT6) =
- (unsigned volatile long)evt_timer;
- *(unsigned volatile long *)(EVT7) =
- (unsigned volatile long)evt_evt7;
- *(unsigned volatile long *)(EVT8) =
- (unsigned volatile long)evt_evt8;
- *(unsigned volatile long *)(EVT9) =
- (unsigned volatile long)evt_evt9;
- *(unsigned volatile long *)(EVT10) =
- (unsigned volatile long)evt_evt10;
- *(unsigned volatile long *)(EVT11) =
- (unsigned volatile long)evt_evt11;
- *(unsigned volatile long *)(EVT12) =
- (unsigned volatile long)evt_evt12;
- *(unsigned volatile long *)(EVT13) =
- (unsigned volatile long)evt_evt13;
- *(unsigned volatile long *)(EVT14) =
- (unsigned volatile long)evt_system_call;
- *(unsigned volatile long *)(EVT15) =
- (unsigned volatile long)evt_soft_int1;
- *(volatile unsigned long *)ILAT = 0;
- asm("csync;");
- *(volatile unsigned long *)IMASK = 0xffbf;
- asm("csync;");
-}
-
-void exception_handle(void)
-{
-#if defined (CONFIG_PANIC_HANG)
- display_excp();
-#else
- udelay(100000); /* allow messages to go out */
- do_reset(NULL, 0, 0, NULL);
-#endif
-}
-
-void display_excp(void)
-{
- printf("Exception!\n");
-}
diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c
deleted file mode 100644
index 05fcfcc..0000000
--- a/cpu/bf533/serial.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * U-boot - serial.c Serial driver for BF533
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART.
- * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on blkfinserial.c
- * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
- * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
- * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
- * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328 version serial driver imlpementation which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/bitops.h>
-#include <asm/delay.h>
-#include <asm/io.h>
-#include "bf533_serial.h"
-#include <asm/mach-common/bits/uart.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long pll_div_fact;
-
-void calc_baud(void)
-{
- unsigned char i;
- int temp;
- u_long sclk = get_sclk();
-
- for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
- temp = sclk / (baud_table[i] * 8);
- if ((temp & 0x1) == 1) {
- temp++;
- }
- temp = temp / 2;
- hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
- hw_baud_table[i].dl_low = (temp) & 0xFF;
- }
-}
-
-void serial_setbrg(void)
-{
- int i;
-
- calc_baud();
-
- for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
- if (gd->baudrate == baud_table[i])
- break;
- }
-
- /* Enable UART */
- *pUART_GCTL |= UCEN;
- SSYNC();
-
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH;
- SSYNC();
-
- *pUART_DLL = hw_baud_table[i].dl_low;
- SSYNC();
- *pUART_DLH = hw_baud_table[i].dl_high;
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER;
- SSYNC();
-
- /* Enable ERBFI and ELSI interrupts
- * to poll SIC_ISR register*/
- *pUART_IER = ELSI | ERBFI | ETBEI;
- SSYNC();
-
- /* Set LCR to Word Lengh 8-bit word select */
- *pUART_LCR = WLS_8;
- SSYNC();
-
- return;
-}
-
-int serial_init(void)
-{
- serial_setbrg();
- return (0);
-}
-
-void serial_putc(const char c)
-{
- if ((*pUART_LSR) & TEMT) {
- if (c == '\n')
- serial_putc('\r');
-
- local_put_char(c);
- }
-
- while (!((*pUART_LSR) & TEMT))
- SYNC_ALL;
-
- return;
-}
-
-int serial_tstc(void)
-{
- if (*pUART_LSR & DR)
- return 1;
- else
- return 0;
-}
-
-int serial_getc(void)
-{
- unsigned short uart_lsr_val, uart_rbr_val;
- unsigned long isr_val;
- int ret;
-
- /* Poll for RX Interrupt */
- while (!serial_tstc())
- continue;
- asm("csync;");
-
- uart_lsr_val = *pUART_LSR; /* Clear status bit */
- uart_rbr_val = *pUART_RBR; /* getc() */
-
- if (uart_lsr_val & (OE|PE|FE|BI)) {
- ret = -1;
- } else {
- ret = uart_rbr_val & 0xff;
- }
-
- return ret;
-}
-
-void serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
-static void local_put_char(char ch)
-{
- int flags = 0;
- unsigned long isr_val;
-
- /* Poll for TX Interruput */
- while (!(*pUART_LSR & THRE))
- continue;
- asm("csync;");
-
- *pUART_THR = ch; /* putc() */
-
- return;
-}
diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S
deleted file mode 100644
index c32fef6..0000000
--- a/cpu/bf533/start.S
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * U-boot - start.S Startup file of u-boot for BF533/BF561
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on head.S
- * Copyright (c) 2003 Metrowerks/Motorola
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * Note: A change in this file subsequently requires a change in
- * board/$(board_name)/config.mk for a valid u-boot.bin
- */
-
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/dma.h>
-#include <asm/mach-common/bits/pll.h>
-
-.global _stext;
-.global __bss_start;
-.global start;
-.global _start;
-.global edata;
-.global _exit;
-.global init_sdram;
-
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-
-.text
-_start:
-start:
-_stext:
-
- R0 = 0x32;
- SYSCFG = R0;
- SSYNC;
-
- /* As per HW reference manual DAG registers,
- * DATA and Address resgister shall be zero'd
- * in initialization, after a reset state
- */
- r1 = 0; /* Data registers zero'd */
- r2 = 0;
- r3 = 0;
- r4 = 0;
- r5 = 0;
- r6 = 0;
- r7 = 0;
-
- p0 = 0; /* Address registers zero'd */
- p1 = 0;
- p2 = 0;
- p3 = 0;
- p4 = 0;
- p5 = 0;
-
- i0 = 0; /* DAG Registers zero'd */
- i1 = 0;
- i2 = 0;
- i3 = 0;
- m0 = 0;
- m1 = 0;
- m3 = 0;
- m3 = 0;
- l0 = 0;
- l1 = 0;
- l2 = 0;
- l3 = 0;
- b0 = 0;
- b1 = 0;
- b2 = 0;
- b3 = 0;
-
- /* Set loop counters to zero, to make sure that
- * hw loops are disabled.
- */
- r0 = 0;
- lc0 = r0;
- lc1 = r0;
-
- SSYNC;
-
- /* Check soft reset status */
- p0.h = SWRST >> 16;
- p0.l = SWRST & 0xFFFF;
- r0.l = w[p0];
-
- cc = bittst(r0, 15);
- if !cc jump no_soft_reset;
-
- /* Clear Soft reset */
- r0 = 0x0000;
- w[p0] = r0;
- ssync;
-
-no_soft_reset:
- nop;
-
- /* Clear EVT registers */
- p0.h = (EVT0 >> 16);
- p0.l = (EVT0 & 0xFFFF);
- p0 += 8;
- p1 = 14;
- r1 = 0;
- LSETUP(4,4) lc0 = p1;
- [ p0 ++ ] = r1;
-
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-
- sp.l = (0xffb01000 & 0xFFFF);
- sp.h = (0xffb01000 >> 16);
-
- call init_sdram;
-
- /* relocate into to RAM */
- call get_pc;
-offset:
- r2.l = offset;
- r2.h = offset;
- r3.l = start;
- r3.h = start;
- r1 = r2 - r3;
-
- r0 = r0 - r1;
- p1 = r0;
-
- p2.l = (CFG_MONITOR_BASE & 0xffff);
- p2.h = (CFG_MONITOR_BASE >> 16);
-
- p3 = 0x04;
- p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
- p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
-loop1:
- r1 = [p1 ++ p3];
- [p2 ++ p3] = r1;
- cc=p2==p4;
- if !cc jump loop1;
- /*
- * configure STACK
- */
- r0.h = (CONFIG_STACKBASE >> 16);
- r0.l = (CONFIG_STACKBASE & 0xFFFF);
- sp = r0;
- fp = sp;
-
- /*
- * This next section keeps the processor in supervisor mode
- * during kernel boot. Switches to user mode at end of boot.
- * See page 3-9 of Hardware Reference manual for documentation.
- */
-
- /* To keep ourselves in the supervisor mode */
- p0.l = (EVT15 & 0xFFFF);
- p0.h = (EVT15 >> 16);
-
- p1.l = _real_start;
- p1.h = _real_start;
- [p0] = p1;
-
- p0.l = (IMASK & 0xFFFF);
- p0.h = (IMASK >> 16);
- r0.l = LO(EVT_IVG15);
- r0.h = HI(EVT_IVG15);
- [p0] = r0;
- raise 15;
- p0.l = WAIT_HERE;
- p0.h = WAIT_HERE;
- reti = p0;
- rti;
-
-WAIT_HERE:
- jump WAIT_HERE;
-
-.global _real_start;
-_real_start:
- [ -- sp ] = reti;
-
- /* DMA reset code to Hi of L1 SRAM */
-copy:
- /* P1 Points to the beginning of SYSTEM MMR Space */
- P1.H = hi(SYSMMR_BASE);
- P1.L = lo(SYSMMR_BASE);
-
- R0.H = reset_start; /* Source Address (high) */
- R0.L = reset_start; /* Source Address (low) */
- R1.H = reset_end;
- R1.L = reset_end;
- R2 = R1 - R0; /* Count */
- R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
- R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
- R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
- /* Destination DMAConfig Value (8-bit words) */
- R4.L = (DI_EN | WNR | DMAEN);
-
-DMA:
- R6 = 0x1 (Z);
- W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
- W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
-
- [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
- W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
- /* Set Source DMAConfig = DMA Enable,
- Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
- W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
-
- /* Set Destination Base Address */
- [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;
- W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
- /* Set Destination DMAConfig = DMA Enable,
- Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
- W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-
-WAIT_DMA_DONE:
- p0.h = hi(MDMA_D0_IRQ_STATUS);
- p0.l = lo(MDMA_D0_IRQ_STATUS);
- R0 = W[P0](Z);
- CC = BITTST(R0, 0);
- if ! CC jump WAIT_DMA_DONE
-
- R0 = 0x1;
-
- /* Write 1 to clear DMA interrupt */
- W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;
-
- /* Initialize BSS Section with 0 s */
- p1.l = __bss_start;
- p1.h = __bss_start;
- p2.l = _end;
- p2.h = _end;
- r1 = p1;
- r2 = p2;
- r3 = r2 - r1;
- r3 = r3 >> 2;
- p3 = r3;
- lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
- CC = p2<=p1;
- if CC jump _clear_bss_skip;
- r0 = 0;
-_clear_bss:
-_clear_bss_end:
- [p1++] = r0;
-_clear_bss_skip:
-
- p0.l = _start1;
- p0.h = _start1;
- jump (p0);
-
-reset_start:
- p0.h = WDOG_CNT >> 16;
- p0.l = WDOG_CNT & 0xffff;
- r0 = 0x0010;
- w[p0] = r0;
- p0.h = WDOG_CTL >> 16;
- p0.l = WDOG_CTL & 0xffff;
- r0 = 0x0000;
- w[p0] = r0;
-reset_wait:
- jump reset_wait;
-
-reset_end: nop;
-
-_exit:
- jump.s _exit;
-get_pc:
- r0 = rets;
- rts;
diff --git a/cpu/bf533/start1.S b/cpu/bf533/start1.S
deleted file mode 100644
index 6d4731b..0000000
--- a/cpu/bf533/start1.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * U-boot - start1.S Code running out of RAM after relocation
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#define ASSEMBLY
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-.global start1;
-.global _start1;
-
-.text
-_start1:
-start1:
- sp += -12;
- call _board_init_f;
- sp += 12;
diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c
deleted file mode 100644
index 7e156d5..0000000
--- a/cpu/bf533/traps.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * U-boot - traps.c Routines related to interrupts and exceptions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * No original Copyright holder listed,
- * Probabily original (C) Roman Zippel (assigned DJD, 1999)
- *
- * Copyright 2003 Metrowerks - for Blackfin
- * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
- * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <asm/errno.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include "cpu.h"
-#include <asm/cplb.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
-
-void init_IRQ(void)
-{
- blackfin_init_IRQ();
- return;
-}
-
-void process_int(unsigned long vec, struct pt_regs *fp)
-{
- printf("interrupt\n");
- return;
-}
-
-extern unsigned int icplb_table[page_descriptor_table_size][2];
-extern unsigned int dcplb_table[page_descriptor_table_size][2];
-
-unsigned long last_cplb_fault_retx;
-
-static unsigned int cplb_sizes[4] =
- { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
-
-void trap_c(struct pt_regs *regs)
-{
- unsigned int addr;
- unsigned long trapnr = (regs->seqstat) & EXCAUSE;
- unsigned int i, j, size, *I0, *I1;
- unsigned short data = 0;
-
- switch (trapnr) {
- /* 0x26 - Data CPLB Miss */
- case VEC_CPLB_M:
-
-#if ANOMALY_05000261
- /*
- * Work around an anomaly: if we see a new DCPLB fault,
- * return without doing anything. Then,
- * if we get the same fault again, handle it.
- */
- addr = last_cplb_fault_retx;
- last_cplb_fault_retx = regs->retx;
- printf("this time, curr = 0x%08x last = 0x%08x\n",
- addr, last_cplb_fault_retx);
- if (addr != last_cplb_fault_retx)
- goto trap_c_return;
-#endif
- data = 1;
-
- case VEC_CPLB_I_M:
-
- if (data) {
- addr = *(unsigned int *)pDCPLB_FAULT_ADDR;
- } else {
- addr = *(unsigned int *)pICPLB_FAULT_ADDR;
- }
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (data) {
- size = cplb_sizes[dcplb_table[i][1] >> 16];
- j = dcplb_table[i][0];
- } else {
- size = cplb_sizes[icplb_table[i][1] >> 16];
- j = icplb_table[i][0];
- }
- if ((j <= addr) && ((j + size) > addr)) {
- debug("found %i 0x%08x\n", i, j);
- break;
- }
- }
- if (i == page_descriptor_table_size) {
- printf("something is really wrong\n");
- do_reset(NULL, 0, 0, NULL);
- }
-
- /* Turn the cache off */
- if (data) {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL &=
- ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
- } else {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
- SSYNC();
- }
-
- if (data) {
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
- } else {
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
- }
-
- j = 0;
- while (*I1 & CPLB_LOCK) {
- debug("skipping %i %08p - %08x\n", j, I1, *I1);
- *I0++;
- *I1++;
- j++;
- }
-
- debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
-
- for (; j < 15; j++) {
- debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
- *I0++ = *(I0 + 1);
- *I1++ = *(I1 + 1);
- }
-
- if (data) {
- *I0 = dcplb_table[i][0];
- *I1 = dcplb_table[i][1];
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
- } else {
- *I0 = icplb_table[i][0];
- *I1 = icplb_table[i][1];
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
- }
-
- for (j = 0; j < 16; j++) {
- debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
- }
-
- /* Turn the cache back on */
- if (data) {
- j = *(unsigned int *)DMEM_CONTROL;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL =
- ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
- SSYNC();
- } else {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
- SSYNC();
- }
-
- break;
- default:
- /* All traps come here */
- printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
- printf("stack frame=0x%x, ", (unsigned int)regs);
- printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
- dump(regs);
- printf("\n\n");
-
- printf("Unhandled IRQ or exceptions!\n");
- printf("Please reset the board \n");
- do_reset(NULL, 0, 0, NULL);
- }
-
- return;
-
-}
-
-void dump(struct pt_regs *fp)
-{
- debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n",
- fp->rete, fp->retn, fp->retx, fp->rets);
- debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
- debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
- debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
- fp->r0, fp->r1, fp->r2, fp->r3);
- debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
- fp->r4, fp->r5, fp->r6, fp->r7);
- debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
- fp->p0, fp->p1, fp->p2, fp->p3);
- debug("P4: %08lx P5: %08lx FP: %08lx\n",
- fp->p4, fp->p5, fp->fp);
- debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
- fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
- debug("LB0: %08lx LT0: %08lx LC0: %08lx\n",
- fp->lb0, fp->lt0, fp->lc0);
- debug("LB1: %08lx LT1: %08lx LC1: %08lx\n",
- fp->lb1, fp->lt1, fp->lc1);
- debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n",
- fp->b0, fp->l0, fp->m0, fp->i0);
- debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n",
- fp->b1, fp->l1, fp->m1, fp->i1);
- debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n",
- fp->b2, fp->l2, fp->m2, fp->i2);
- debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n",
- fp->b3, fp->l3, fp->m3, fp->i3);
-
- debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
- debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
-
-}
diff --git a/cpu/bf533/video.c b/cpu/bf533/video.c
deleted file mode 100644
index 3ff0151..0000000
--- a/cpu/bf533/video.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
- * (C) Copyright 2002
- * Wolfgang Denk, wd@denx.de
- * (C) Copyright 2006
- * Aubrey Li, aubrey.li@analog.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <devices.h>
-
-#ifdef CONFIG_VIDEO
-#define NTSC_FRAME_ADDR 0x06000000
-#include "video.h"
-
-/* NTSC OUTPUT SIZE 720 * 240 */
-#define VERTICAL 2
-#define HORIZONTAL 4
-
-int is_vblank_line(const int line)
-{
- /*
- * This array contains a single bit for each line in
- * an NTSC frame.
- */
- if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
- return true;
-
- return false;
-}
-
-int NTSC_framebuffer_init(char *base_address)
-{
- const int NTSC_frames = 1;
- const int NTSC_lines = 525;
- char *dest = base_address;
- int frame_num, line_num;
-
- for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
- for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
- unsigned int code;
- int offset = 0;
- int i;
-
- if (is_vblank_line(line_num))
- offset++;
-
- if (line_num > 266 || line_num < 3)
- offset += 2;
-
- /* Output EAV code */
- code = SystemCodeMap[offset].EAV;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output horizontal blanking */
- for (i = 0; i < 67 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
-
- /* Output SAV */
- code = SystemCodeMap[offset].SAV;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output empty horizontal data */
- for (i = 0; i < 360 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
- }
- }
-
- return dest - base_address;
-}
-
-void fill_frame(char *Frame, int Value)
-{
- int *OddPtr32;
- int OddLine;
- int *EvenPtr32;
- int EvenLine;
- int i;
- int *data;
- int m, n;
-
- /* fill odd and even frames */
- for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
- OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
- EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
- for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
- *OddPtr32 = Value;
- *EvenPtr32 = Value;
- }
- }
-
- for (m = 0; m < VERTICAL; m++) {
- data = (int *)u_boot_logo.data;
- for (OddLine = (22 + m), EvenLine = (285 + m);
- OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
- OddLine += VERTICAL, EvenLine += VERTICAL) {
- OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
- EvenPtr32 =
- (int *)((Frame + ((EvenLine) * 1716)) + 276);
- for (i = 0; i < u_boot_logo.width / 2; i++) {
- /* enlarge one pixel to m x n */
- for (n = 0; n < HORIZONTAL; n++) {
- *OddPtr32++ = *data;
- *EvenPtr32++ = *data;
- }
- data++;
- }
- }
- }
-}
-
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
-static int video_init(void)
-{
- char *NTSCFrame;
- NTSCFrame = (char *)NTSC_FRAME_ADDR;
- NTSC_framebuffer_init(NTSCFrame);
- fill_frame(NTSCFrame, BLUE);
-
- *pPPI_CONTROL = 0x0082;
- *pPPI_FRAME = 0x020D;
-
- *pDMA0_START_ADDR = NTSCFrame;
- *pDMA0_X_COUNT = 0x035A;
- *pDMA0_X_MODIFY = 0x0002;
- *pDMA0_Y_COUNT = 0x020D;
- *pDMA0_Y_MODIFY = 0x0002;
- *pDMA0_CONFIG = 0x1015;
- *pPPI_CONTROL = 0x0083;
- return 0;
-}
-
-int drv_video_init(void)
-{
- int error, devices = 1;
-
- device_t videodev;
-
- video_init(); /* Video initialization */
-
- memset(&videodev, 0, sizeof(videodev));
-
- strcpy(videodev.name, "video");
- videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
- videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */
- videodev.putc = video_putc; /* 'putc' function */
- videodev.puts = video_puts; /* 'puts' function */
-
- error = device_register(&videodev);
-
- return (error == 0) ? devices : error;
-}
-#endif
diff --git a/cpu/bf533/video.h b/cpu/bf533/video.h
deleted file mode 100644
index d237f6a..0000000
--- a/cpu/bf533/video.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#include <video_logo.h>
-#define write_dest_byte(val) {*dest++=val;}
-#define BLACK (0x01800180) /* black pixel pattern */
-#define BLUE (0x296E29F0) /* blue pixel pattern */
-#define RED (0x51F0515A) /* red pixel pattern */
-#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
-#define GREEN (0x91229136) /* green pixel pattern */
-#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
-#define YELLOW (0xD292D210) /* yellow pixel pattern */
-#define WHITE (0xFE80FE80) /* white pixel pattern */
-
-#define true 1
-#define false 0
-
-typedef struct {
- unsigned int SAV;
- unsigned int EAV;
-} SystemCodeType;
-
-const SystemCodeType SystemCodeMap[4] = {
- {0xFF000080, 0xFF00009D},
- {0xFF0000AB, 0xFF0000B6},
- {0xFF0000C7, 0xFF0000DA},
- {0xFF0000EC, 0xFF0000F1}
-};
diff --git a/cpu/bf537/Makefile b/cpu/bf537/Makefile
deleted file mode 100644
index 06d1aae..0000000
--- a/cpu/bf537/Makefile
+++ /dev/null
@@ -1,52 +0,0 @@
-# U-boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Devices Inc.
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(CPU).a
-
-SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
-COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o i2c.o
-
-EXTRA = init_sdram_bootrom_initblock.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-START := $(addprefix $(obj),$(START))
-
-all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
-
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/bf537/cache.S b/cpu/bf537/cache.S
deleted file mode 100644
index d9015c6..0000000
--- a/cpu/bf537/cache.S
+++ /dev/null
@@ -1,129 +0,0 @@
-#define ASSEMBLY
-#include <asm/linkage.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/mpu.h>
-
-.text
-.align 2
-ENTRY(_blackfin_icache_flush_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
- 1:
- IFLUSH[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
- IFLUSH[P0];
- SSYNC;
- RTS;
-
-ENTRY(_blackfin_dcache_flush_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
-1:
- FLUSH[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
- FLUSH[P0];
- SSYNC;
- RTS;
-
-ENTRY(_icache_invalidate)
-ENTRY(_invalidate_entire_icache)
- [--SP] = (R7:5);
-
- P0.L = (IMEM_CONTROL & 0xFFFF);
- P0.H = (IMEM_CONTROL >> 16);
- R7 =[P0];
-
- /*
- * Clear the IMC bit , All valid bits in the instruction
- * cache are set to the invalid state
- */
- BITCLR(R7, IMC_P);
- CLI R6;
- /* SSYNC required before invalidating cache. */
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- /* Configures the instruction cache agian */
- R6 = (IMC | ENICPLB);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- (R7:5) =[SP++];
- RTS;
-
-/*
- * Invalidate the Entire Data cache by
- * clearing DMC[1:0] bits
- */
-ENTRY(_invalidate_entire_dcache)
-ENTRY(_dcache_invalidate)
- [--SP] = (R7:6);
-
- P0.L = (DMEM_CONTROL & 0xFFFF);
- P0.H = (DMEM_CONTROL >> 16);
- R7 =[P0];
-
- /*
- * Clear the DMC[1:0] bits, All valid bits in the data
- * cache are set to the invalid state
- */
- BITCLR(R7, DMC0_P);
- BITCLR(R7, DMC1_P);
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
- /* Configures the data cache again */
-
- R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- (R7:6) =[SP++];
- RTS;
-
-ENTRY(_blackfin_dcache_invalidate_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
-1:
- FLUSHINV[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
-
- /*
- * If the data crosses a cache line, then we'll be pointing to
- * the last cache line, but won't have flushed/invalidated it yet, so do
- * one more.
- */
- FLUSHINV[P0];
- SSYNC;
- RTS;
diff --git a/cpu/bf537/config.mk b/cpu/bf537/config.mk
deleted file mode 100644
index fbbe75d..0000000
--- a/cpu/bf537/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-# U-boot - config.mk
-#
-# Copyright (c) 2005-2007 Analog Devices Inc.
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-PLATFORM_RELFLAGS += -mcpu=bf537
diff --git a/cpu/bf537/cpu.c b/cpu/bf537/cpu.c
deleted file mode 100644
index 7233908..0000000
--- a/cpu/bf537/cpu.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * U-boot - cpu.c CPU specific functions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <command.h>
-#include <asm/entry.h>
-#include <asm/cplb.h>
-#include <asm/io.h>
-
-#define CACHE_ON 1
-#define CACHE_OFF 0
-
-extern unsigned int icplb_table[page_descriptor_table_size][2];
-extern unsigned int dcplb_table[page_descriptor_table_size][2];
-
-int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
- );
-
- return 0;
-}
-
-/* These functions are just used to satisfy the linker */
-int cpu_init(void)
-{
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- return 0;
-}
-
-void icache_enable(void)
-{
- unsigned int *I0, *I1;
- int i, j = 0;
-
- if ((*pCHIPID >> 28) < 2)
- return;
-
- /* Before enable icache, disable it first */
- icache_disable();
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
-
- /* make sure the locked ones go in first */
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (CPLB_LOCK & icplb_table[i][1]) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- icplb_table[i][0], icplb_table[i][1]);
- *I0++ = icplb_table[i][0];
- *I1++ = icplb_table[i][1];
- j++;
- }
- }
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (!(CPLB_LOCK & icplb_table[i][1])) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- icplb_table[i][0], icplb_table[i][1]);
- *I0++ = icplb_table[i][0];
- *I1++ = icplb_table[i][1];
- j++;
- if (j == 16) {
- break;
- }
- }
- }
-
- /* Fill the rest with invalid entry */
- if (j <= 15) {
- for (; j < 16; j++) {
- debug("filling %i with 0", j);
- *I1++ = 0x0;
- }
-
- }
-
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
- SSYNC();
-}
-
-void icache_disable(void)
-{
- if ((*pCHIPID >> 28) < 2)
- return;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
- SSYNC();
-}
-
-int icache_status(void)
-{
- unsigned int value;
- value = *(unsigned int *)IMEM_CONTROL;
-
- if (value & (IMC | ENICPLB))
- return CACHE_ON;
- else
- return CACHE_OFF;
-}
-
-void dcache_enable(void)
-{
- unsigned int *I0, *I1;
- unsigned int temp;
- int i, j = 0;
-
- /* Before enable dcache, disable it first */
- dcache_disable();
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
-
- /* make sure the locked ones go in first */
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (CPLB_LOCK & dcplb_table[i][1]) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- *I0++ = dcplb_table[i][0];
- *I1++ = dcplb_table[i][1];
- j++;
- } else {
- debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- }
- }
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (!(CPLB_LOCK & dcplb_table[i][1])) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- *I0++ = dcplb_table[i][0];
- *I1++ = dcplb_table[i][1];
- j++;
- if (j == 16) {
- break;
- }
- }
- }
-
- /* Fill the rest with invalid entry */
- if (j <= 15) {
- for (; j < 16; j++) {
- debug("filling %i with 0", j);
- *I1++ = 0x0;
- }
- }
-
- temp = *(unsigned int *)DMEM_CONTROL;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL =
- ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
- SSYNC();
-}
-
-void dcache_disable(void)
-{
- unsigned int *I0, *I1;
- int i;
-
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL &=
- ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
-
- /* after disable dcache,
- * clear it so we don't confuse the next application
- */
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
-
- for (i = 0; i < 16; i++) {
- *I0++ = 0x0;
- *I1++ = 0x0;
- }
-}
-
-int dcache_status(void)
-{
- unsigned int value;
- value = *(unsigned int *)DMEM_CONTROL;
-
- if (value & (ENDCPLB))
- return CACHE_ON;
- else
- return CACHE_OFF;
-}
diff --git a/cpu/bf537/cpu.h b/cpu/bf537/cpu.h
deleted file mode 100644
index b6b73b1..0000000
--- a/cpu/bf537/cpu.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * U-boot - cpu.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _CPU_H_
-#define _CPU_H_
-
-#include <command.h>
-
-#define INTERNAL_IRQS (32)
-#define NUM_IRQ_NODES 16
-#define DEF_INTERRUPT_FLAGS 1
-#define MAX_TIM_LOAD 0xFFFFFFFF
-
-void blackfin_irq_panic(int reason, struct pt_regs *reg);
-extern void dump(struct pt_regs *regs);
-void display_excp(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_exception(void);
-asmlinkage void trap(void);
-asmlinkage void evt_ivhw(void);
-asmlinkage void evt_rst(void);
-asmlinkage void evt_timer(void);
-asmlinkage void evt_evt7(void);
-asmlinkage void evt_evt8(void);
-asmlinkage void evt_evt9(void);
-asmlinkage void evt_evt10(void);
-asmlinkage void evt_evt11(void);
-asmlinkage void evt_evt12(void);
-asmlinkage void evt_evt13(void);
-asmlinkage void evt_soft_int1(void);
-asmlinkage void evt_system_call(void);
-void blackfin_irq_panic(int reason, struct pt_regs *regs);
-void blackfin_free_irq(unsigned int irq, void *dev_id);
-void call_isr(int irq, struct pt_regs *fp);
-void blackfin_do_irq(int vec, struct pt_regs *fp);
-void blackfin_init_IRQ(void);
-void blackfin_enable_irq(unsigned int irq);
-void blackfin_disable_irq(unsigned int irq);
-extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
-int blackfin_request_irq(unsigned int irq,
- void (*handler) (int, void *, struct pt_regs *),
- unsigned long flags, const char *devname,
- void *dev_id);
-void timer_init(void);
-#endif
diff --git a/cpu/bf537/flush.S b/cpu/bf537/flush.S
deleted file mode 100644
index fbd26cc..0000000
--- a/cpu/bf537/flush.S
+++ /dev/null
@@ -1,403 +0,0 @@
-/* Copyright (C) 2003-2007 Analog Devices Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.
- */
-
-#define ASSEMBLY
-
-#include <asm/linkage.h>
-#include <asm/cplb.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-.text
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the instruction cache.
- */
-
-ENTRY(_flush_instruction_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = (ICPLB_ADDR0 >> 16);
- P5.L = (ICPLB_ADDR0 & 0xFFFF);
- P4.H = (ICPLB_DATA0 >> 16);
- P4.L = (ICPLB_DATA0 & 0xFFFF);
- R7 = CPLB_VALID | CPLB_L1_CHBL;
- R6 = 16;
-inext: R0 = [P5++];
- R1 = [P4++];
- [--SP] = RETS;
- CALL _icplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-iskip: R6 += -1;
- CC = R6;
- IF CC JUMP inext;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular ICPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_icplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP iflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /* Anamoly 05000209 */
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */
-
- /* Save in extraction pattern for later deposit. */
- R3.H = R4.L << 0;
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = (ITEST_COMMAND & 0xFFFF);
- P5.H = (ITEST_COMMAND >> 16);
- P4.L = (ITEST_DATA0 & 0xFFFF);
- P4.H = (ITEST_DATA0 >> 16);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 4;
- LSETUP (ifs1, ife1) LC1 = P2;
-ifs1: P0 = 32; /* iterate over all sets*/
- LSETUP (ifs0, ife0) LC0 = P0;
-ifs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- [P5] = R6; /* Issue Command*/
- SSYNC; /* CSYNC will not work here :(*/
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP ifskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- IFLUSH [P3]; /* And flush the entry*/
-ifskip:
-ife0: R5 += 1; /* Advance to next Set*/
-ife1: NOP;
-
-ifinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-iflush_whole_page:
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- IFLUSH [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (isall, ieall) LC0 = P1;
-isall:IFLUSH [P0++];
-ieall: NOP;
- SSYNC;
- JUMP ifinished;
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the data cache.
- */
-
-ENTRY(_flush_data_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = (DCPLB_ADDR0 >> 16);
- P5.L = (DCPLB_ADDR0 & 0xFFFF);
- P4.H = (DCPLB_DATA0 >> 16);
- P4.L = (DCPLB_DATA0 & 0xFFFF);
- R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
- R6 = 16;
-next: R0 = [P5++];
- R1 = [P4++];
- CC = BITTST(R1, 14); /* Is it write-through?*/
- IF CC JUMP skip; /* If so, ignore it.*/
- R2 = R1 & R7; /* Is it a dirty, cached page?*/
- CC = R2;
- IF !CC JUMP skip; /* If not, ignore it.*/
- [--SP] = RETS;
- CALL _dcplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-skip: R6 += -1;
- CC = R6;
- IF CC JUMP next;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular DCPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_dcplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP dflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* The page could be mapped into Bank A or Bank B, depending
- * on (a) whether both banks are configured as cache, and
- * (b) on whether address bit A[x] is set. x is determined
- * by DCBS in DMEM_CONTROL
- */
-
- R2 = 0; /* Default to Bank A (Bank B would be 1)*/
-
- P0.L = (DMEM_CONTROL & 0xFFFF);
- P0.H = (DMEM_CONTROL >> 16);
-
- R3 = [P0]; /* If Bank B is not enabled as cache*/
- CC = BITTST(R3, 2); /* then Bank A is our only option.*/
- IF CC JUMP bank_chosen;
-
- R4 = 1<<14; /* If DCBS==0, use A[14].*/
- R5 = R4 << 7; /* If DCBS==1, use A[23];*/
- CC = BITTST(R3, 4);
- IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
- R5 = R0 & R4; /* Use it to test the Page address*/
- CC = R5; /* and if that bit is set, we use Bank B,*/
- R2 = CC; /* else we use Bank A.*/
- R2 <<= 23; /* The Bank selection's at posn 23.*/
-
-bank_chosen:
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /*Anamoly 05000209*/
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
- /* Save in extraction pattern for later deposit.*/
- R3.H = R4.L << 0;
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R2 = Bank select mask
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = (DTEST_COMMAND & 0xFFFF);
- P5.H = (DTEST_COMMAND >> 16);
- P4.L = (DTEST_DATA0 & 0xFFFF);
- P4.H = (DTEST_DATA0 >> 16);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 2;
- LSETUP (fs1, fe1) LC1 = P2;
-fs1: P0 = 64; /* iterate over all sets*/
- LSETUP (fs0, fe0) LC0 = P0;
-fs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
- BITSET(R6,14);
- [P5] = R6; /* Issue Command*/
- SSYNC;
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP fskip; /* and skip if not.*/
- CC = BITTST(R7, 1); /* Check if dirty*/
- IF !CC JUMP fskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP fskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- SSYNC;
- FLUSHINV [P3]; /* And flush the entry*/
-fskip:
-fe0: R5 += 1; /* Advance to next Set*/
-fe1: BITSET(R2, 26); /* Go to next Way.*/
-
-dfinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-dflush_whole_page:
-
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (eall, eall) LC0 = P1;
-eall: FLUSHINV [P0++];
- SSYNC;
- JUMP dfinished;
-
-.align 4;
-page_prefix_table:
-.byte4 0xFFFFFC00; /* 1K */
-.byte4 0xFFFFF000; /* 4K */
-.byte4 0xFFF00000; /* 1M */
-.byte4 0xFFC00000; /* 4M */
-.page_prefix_table.end:
diff --git a/cpu/bf537/init_sdram.S b/cpu/bf537/init_sdram.S
deleted file mode 100644
index e997500..0000000
--- a/cpu/bf537/init_sdram.S
+++ /dev/null
@@ -1,178 +0,0 @@
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
-.global init_sdram;
-
-#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-#endif
-
-init_sdram:
- [--SP] = ASTAT;
- [--SP] = RETS;
- [--SP] = (R7:0);
- [--SP] = (P5:0);
-
-#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-
- p0.h = hi(SPI_BAUD);
- p0.l = lo(SPI_BAUD);
- r0.l = CONFIG_SPI_BAUD;
- w[p0] = r0.l;
- SSYNC;
-#endif
-
-#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
-
-#ifdef CONFIG_BF537
- /* Enable PHY CLK buffer output */
- p0.h = hi(VR_CTL);
- p0.l = lo(VR_CTL);
- r0.l = w[p0];
- bitset(r0, 14);
- w[p0] = r0.l;
- ssync;
-#endif
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-#endif
-
- /*
- * Now, Initialize the SDRAM,
- * start with the SDRAM Refresh Rate Control Register
- */
- p0.l = lo(EBIU_SDRRC);
- p0.h = hi(EBIU_SDRRC);
- r0 = mem_SDRRC;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Memory Bank Control Register - bank specific parameters
- */
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16);
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Global Control Register - global programmable parameters
- * Disable self-refresh
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITCLR (R0, 24);
-
- /*
- * Check if SDRAM is already powered up, if it is, enable self-refresh
- */
- p0.h = hi(EBIU_SDSTAT);
- p0.l = lo(EBIU_SDSTAT);
- r2.l = w[p0];
- cc = bittst(r2,3);
- if !cc jump skip;
- NOP;
- BITSET (R0, 23);
-skip:
- [P2] = R0;
- SSYNC;
-
- /* Write in the new value in the register */
- R0.L = lo(mem_SDGCTL);
- R0.H = hi(mem_SDGCTL);
- [P2] = R0;
- SSYNC;
- nop;
-
- (P5:0) = [SP++];
- (R7:0) = [SP++];
- RETS = [SP++];
- ASTAT = [SP++];
- RTS;
diff --git a/cpu/bf537/init_sdram_bootrom_initblock.S b/cpu/bf537/init_sdram_bootrom_initblock.S
deleted file mode 100644
index 197b836..0000000
--- a/cpu/bf537/init_sdram_bootrom_initblock.S
+++ /dev/null
@@ -1,203 +0,0 @@
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
-.global init_sdram;
-
-#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-#endif
-
-init_sdram:
- [--SP] = ASTAT;
- [--SP] = RETS;
- [--SP] = (R7:0);
- [--SP] = (P5:0);
-
-#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-
- p0.h = hi(SPI_BAUD);
- p0.l = lo(SPI_BAUD);
- r0.l = CONFIG_SPI_BAUD_INITBLOCK;
- w[p0] = r0.l;
- SSYNC;
-#endif
-
-#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
-
-#ifdef CONFIG_BF537
- /* Enable PHY CLK buffer output */
- p0.h = hi(VR_CTL);
- p0.l = lo(VR_CTL);
- r0.l = w[p0];
- bitset(r0, 14);
- w[p0] = r0.l;
- ssync;
-#endif
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-#endif
-
- /*
- * We now are running at speed, time to set the Async mem bank wait states
- * This will speed up execution, since we are normally running from FLASH.
- */
-
- p2.h = (EBIU_AMBCTL1 >> 16);
- p2.l = (EBIU_AMBCTL1 & 0xFFFF);
- r0.h = (AMBCTL1VAL >> 16);
- r0.l = (AMBCTL1VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMBCTL0 >> 16);
- p2.l = (EBIU_AMBCTL0 & 0xFFFF);
- r0.h = (AMBCTL0VAL >> 16);
- r0.l = (AMBCTL0VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMGCTL >> 16);
- p2.l = (EBIU_AMGCTL & 0xffff);
- r0 = AMGCTLVAL;
- w[p2] = r0;
- ssync;
-
- /*
- * Now, Initialize the SDRAM,
- * start with the SDRAM Refresh Rate Control Register
- */
- p0.l = lo(EBIU_SDRRC);
- p0.h = hi(EBIU_SDRRC);
- r0 = mem_SDRRC;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Memory Bank Control Register - bank specific parameters
- */
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16);
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Global Control Register - global programmable parameters
- * Disable self-refresh
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITCLR (R0, 24);
-
- /*
- * Check if SDRAM is already powered up, if it is, enable self-refresh
- */
- p0.h = hi(EBIU_SDSTAT);
- p0.l = lo(EBIU_SDSTAT);
- r2.l = w[p0];
- cc = bittst(r2,3);
- if !cc jump skip;
- NOP;
- BITSET (R0, 23);
-skip:
- [P2] = R0;
- SSYNC;
-
- /* Write in the new value in the register */
- R0.L = lo(mem_SDGCTL);
- R0.H = hi(mem_SDGCTL);
- [P2] = R0;
- SSYNC;
- nop;
-
- (P5:0) = [SP++];
- (R7:0) = [SP++];
- RETS = [SP++];
- ASTAT = [SP++];
- RTS;
diff --git a/cpu/bf537/interrupt.S b/cpu/bf537/interrupt.S
deleted file mode 100644
index fe850bf..0000000
--- a/cpu/bf537/interrupt.S
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * U-boot - interrupt.S Processing of interrupts and exception handling
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on interrupt.S
- *
- * Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com>
- * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- *
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * This file is also based on exception.asm
- * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#define ASSEMBLY
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/entry.h>
-
-.global _blackfin_irq_panic;
-
-.text
-.align 2
-
-#ifndef CONFIG_KGDB
-.global _evt_emulation
-_evt_emulation:
- SAVE_CONTEXT
- r0 = 0;
- r1 = seqstat;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
- rte;
-#endif
-
-.global _evt_nmi
-_evt_nmi:
- SAVE_CONTEXT
- r0 = 2;
- r1 = RETN;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
-
-_evt_nmi_exit:
- rtn;
-
-.global _trap
-_trap:
- SAVE_ALL_SYS
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- sp += -12;
- call _trap_c
- sp += 12;
- RESTORE_ALL_SYS
- rtx;
-
-.global _evt_rst
-_evt_rst:
- SAVE_CONTEXT
- r0 = 1;
- r1 = RETN;
- sp += -12;
- call _do_reset;
- sp += 12;
-
-_evt_rst_exit:
- rtn;
-
-irq_panic:
- r0 = 3;
- r1 = sp;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
-
-.global _evt_ivhw
-_evt_ivhw:
- SAVE_CONTEXT
- RAISE 14;
-
-_evt_ivhw_exit:
- rti;
-
-.global _evt_timer
-_evt_timer:
- SAVE_CONTEXT
- r0 = 6;
- sp += -12;
- /* Polling method used now. */
- /* call timer_int; */
- sp += 12;
- RESTORE_CONTEXT
- rti;
- nop;
-
-.global _evt_evt7
-_evt_evt7:
- SAVE_CONTEXT
- r0 = 7;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt7_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt8
-_evt_evt8:
- SAVE_CONTEXT
- r0 = 8;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt8_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt9
-_evt_evt9:
- SAVE_CONTEXT
- r0 = 9;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt9_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt10
-_evt_evt10:
- SAVE_CONTEXT
- r0 = 10;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt10_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt11
-_evt_evt11:
- SAVE_CONTEXT
- r0 = 11;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt11_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt12
-_evt_evt12:
- SAVE_CONTEXT
- r0 = 12;
- sp += -12;
- call _process_int;
- sp += 12;
-evt_evt12_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt13
-_evt_evt13:
- SAVE_CONTEXT
- r0 = 13;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt13_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_system_call
-_evt_system_call:
- [--sp] = r0;
- [--SP] = RETI;
- r0 = [sp++];
- r0 += 2;
- [--sp] = r0;
- RETI = [SP++];
- r0 = [SP++];
- SAVE_CONTEXT
- sp += -12;
- call _exception_handle;
- sp += 12;
- RESTORE_CONTEXT
- RTI;
-
-evt_system_call_exit:
- rti;
-
-.global _evt_soft_int1
-_evt_soft_int1:
- [--sp] = r0;
- [--SP] = RETI;
- r0 = [sp++];
- r0 += 2;
- [--sp] = r0;
- RETI = [SP++];
- r0 = [SP++];
- SAVE_CONTEXT
- sp += -12;
- call _exception_handle;
- sp += 12;
- RESTORE_CONTEXT
- RTI;
-
-evt_soft_int1_exit:
- rti;
diff --git a/cpu/bf537/interrupts.c b/cpu/bf537/interrupts.c
deleted file mode 100644
index 853fa49..0000000
--- a/cpu/bf537/interrupts.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * U-boot - interrupts.c Interrupt related routines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on interrupts.c
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-static ulong timestamp;
-static ulong last_time;
-static int int_flag;
-
-int irq_flags; /* needed by asm-blackfin/system.h */
-
-/* Functions just to satisfy the linker */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On BF533 it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On BF533 it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- ulong tbclk;
-
- tbclk = CFG_HZ;
- return tbclk;
-}
-
-void enable_interrupts(void)
-{
-}
-
-int disable_interrupts(void)
-{
- return 1;
-}
-
-int interrupt_init(void)
-{
- return (0);
-}
-
-void udelay(unsigned long usec)
-{
- unsigned long delay, start, stop;
- unsigned long cclk;
- cclk = (CONFIG_CCLK_HZ);
-
- while (usec > 1) {
- /*
- * how many clock ticks to delay?
- * - request(in useconds) * clock_ticks(Hz) / useconds/second
- */
- if (usec < 1000) {
- delay = (usec * (cclk / 244)) >> 12;
- usec = 0;
- } else {
- delay = (1000 * (cclk / 244)) >> 12;
- usec -= 1000;
- }
-
- asm volatile (" %0 = CYCLES;":"=r" (start));
- do {
- asm volatile (" %0 = CYCLES; ":"=r" (stop));
- } while (stop - start < delay);
- }
-
- return;
-}
-
-void timer_init(void)
-{
- *pTCNTL = 0x1;
- *pTSCALE = 0x0;
- *pTCOUNT = MAX_TIM_LOAD;
- *pTPERIOD = MAX_TIM_LOAD;
- *pTCNTL = 0x7;
- asm("CSYNC;");
-
- timestamp = 0;
- last_time = 0;
-}
-
-/* Any network command or flash
- * command is started get_timer shall
- * be called before TCOUNT gets reset,
- * to implement the accurate timeouts.
- *
- * How ever milliconds doesn't return
- * the number that has been elapsed from
- * the last reset.
- *
- * As get_timer is used in the u-boot
- * only for timeouts this should be
- * sufficient
- */
-ulong get_timer(ulong base)
-{
- ulong milisec;
-
- /* Number of clocks elapsed */
- ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
-
- /**
- * Find if the TCOUNT is reset
- * timestamp gives the number of times
- * TCOUNT got reset
- */
- if (clocks < last_time)
- timestamp++;
- last_time = clocks;
-
- /* Get the number of milliseconds */
- milisec = clocks / (CONFIG_CCLK_HZ / 1000);
-
- /**
- * Find the number of millisonds
- * that got elapsed before this TCOUNT cycle
- */
- milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
-
- return (milisec - base);
-}
-
-void reset_timer (void)
-{
- timestamp = 0;
-}
diff --git a/cpu/bf537/ints.c b/cpu/bf537/ints.c
deleted file mode 100644
index 05d9a1b..0000000
--- a/cpu/bf537/ints.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * U-boot - ints.c Interrupt related routines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on ints.c
- *
- * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
- * drivers
- *
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <linux/stddef.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-void blackfin_irq_panic(int reason, struct pt_regs *regs)
-{
- printf("\n\nException: IRQ 0x%x entered\n", reason);
- printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
- printf("stack frame=0x%x, ", (unsigned int)regs);
- printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
- dump(regs);
- printf("Unhandled IRQ or exceptions!\n");
- printf("Please reset the board \n");
-}
-
-void blackfin_init_IRQ(void)
-{
- *(unsigned volatile long *)(SIC_IMASK) = 0;
-#ifndef CONFIG_KGDB
- *(unsigned volatile long *)(EVT1) = 0x0;
-#endif
- *(unsigned volatile long *)(EVT2) =
- (unsigned volatile long)evt_nmi;
- *(unsigned volatile long *)(EVT3) =
- (unsigned volatile long)trap;
- *(unsigned volatile long *)(EVT5) =
- (unsigned volatile long)evt_ivhw;
- *(unsigned volatile long *)(EVT0) =
- (unsigned volatile long)evt_rst;
- *(unsigned volatile long *)(EVT6) =
- (unsigned volatile long)evt_timer;
- *(unsigned volatile long *)(EVT7) =
- (unsigned volatile long)evt_evt7;
- *(unsigned volatile long *)(EVT8) =
- (unsigned volatile long)evt_evt8;
- *(unsigned volatile long *)(EVT9) =
- (unsigned volatile long)evt_evt9;
- *(unsigned volatile long *)(EVT10) =
- (unsigned volatile long)evt_evt10;
- *(unsigned volatile long *)(EVT11) =
- (unsigned volatile long)evt_evt11;
- *(unsigned volatile long *)(EVT12) =
- (unsigned volatile long)evt_evt12;
- *(unsigned volatile long *)(EVT13) =
- (unsigned volatile long)evt_evt13;
- *(unsigned volatile long *)(EVT14) =
- (unsigned volatile long)evt_system_call;
- *(unsigned volatile long *)(EVT15) =
- (unsigned volatile long)evt_soft_int1;
- *(volatile unsigned long *)ILAT = 0;
- asm("csync;");
- *(volatile unsigned long *)IMASK = 0xffbf;
- asm("csync;");
-}
-
-void exception_handle(void)
-{
-#if defined (CONFIG_PANIC_HANG)
- display_excp();
-#else
- udelay(100000); /* allow messages to go out */
- do_reset(NULL, 0, 0, NULL);
-#endif
-}
-
-void display_excp(void)
-{
- printf("Exception!\n");
-}
diff --git a/cpu/bf537/serial.c b/cpu/bf537/serial.c
deleted file mode 100644
index 3c6a370..0000000
--- a/cpu/bf537/serial.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * U-boot - serial.c Serial driver for BF537
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * bf537_serial.c: Serial driver for BlackFin BF537 internal UART.
- * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on blkfinserial.c
- * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
- * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
- * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
- * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328 version serial driver imlpementation which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/bitops.h>
-#include <asm/delay.h>
-#include <asm/io.h>
-#include "serial.h"
-#include <asm/mach-common/bits/uart.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long pll_div_fact;
-
-void calc_baud(void)
-{
- unsigned char i;
- int temp;
- u_long sclk = get_sclk();
-
- for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
- temp = sclk / (baud_table[i] * 8);
- if ((temp & 0x1) == 1) {
- temp++;
- }
- temp = temp / 2;
- hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
- hw_baud_table[i].dl_low = (temp) & 0xFF;
- }
-}
-
-void serial_setbrg(void)
-{
- int i;
-
- calc_baud();
-
- for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
- if (gd->baudrate == baud_table[i])
- break;
- }
-
- /* Enable UART */
- *pUART0_GCTL |= UCEN;
- SSYNC();
-
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH;
- SSYNC();
-
- *pUART0_DLL = hw_baud_table[i].dl_low;
- SSYNC();
- *pUART0_DLH = hw_baud_table[i].dl_high;
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER;
- SSYNC();
-
- /* Enable ERBFI and ELSI interrupts
- * to poll SIC_ISR register*/
- *pUART0_IER = ELSI | ERBFI | ETBEI;
- SSYNC();
-
- /* Set LCR to Word Lengh 8-bit word select */
- *pUART0_LCR = WLS_8;
- SSYNC();
-
- return;
-}
-
-int serial_init(void)
-{
- serial_setbrg();
- return (0);
-}
-
-void serial_putc(const char c)
-{
- if ((*pUART0_LSR) & TEMT) {
- if (c == '\n')
- serial_putc('\r');
-
- local_put_char(c);
- }
-
- while (!((*pUART0_LSR) & TEMT))
- SYNC_ALL;
-
- return;
-}
-
-int serial_tstc(void)
-{
- if (*pUART0_LSR & DR)
- return 1;
- else
- return 0;
-}
-
-int serial_getc(void)
-{
- unsigned short uart_lsr_val, uart_rbr_val;
- unsigned long isr_val;
- int ret;
-
- /* Poll for RX Interrupt */
- while (!serial_tstc())
- continue;
- asm("csync;");
-
- uart_lsr_val = *pUART0_LSR; /* Clear status bit */
- uart_rbr_val = *pUART0_RBR; /* getc() */
-
- if (uart_lsr_val & (OE|PE|FE|BI)) {
- ret = -1;
- } else {
- ret = uart_rbr_val & 0xff;
- }
-
- return ret;
-}
-
-void serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
-static void local_put_char(char ch)
-{
- int flags = 0;
- unsigned long isr_val;
-
- /* Poll for TX Interruput */
- while (!(*pUART0_LSR & THRE))
- continue;
- asm("csync;");
-
- *pUART0_THR = ch; /* putc() */
-
- return;
-}
diff --git a/cpu/bf537/serial.h b/cpu/bf537/serial.h
deleted file mode 100644
index e4e0b9a..0000000
--- a/cpu/bf537/serial.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * U-boot - bf537_serial.h Serial Driver defines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
- * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl>
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on:
- * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
- *
- * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com
- * Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328serial.c which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _Bf537_SERIAL_H
-#define _Bf537_SERIAL_H
-
-#include <linux/config.h>
-#include <asm/blackfin.h>
-
-#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
-#define ACCESS_LATCH *pUART0_LCR |= DLAB;
-#define ACCESS_PORT_IER *pUART0_LCR &= (~DLAB);
-
-void serial_setbrg(void);
-static void local_put_char(char ch);
-void calc_baud(void);
-void serial_setbrg(void);
-int serial_init(void);
-void serial_putc(const char c);
-int serial_tstc(void);
-int serial_getc(void);
-void serial_puts(const char *s);
-static void local_put_char(char ch);
-
-int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
-
-struct {
- unsigned char dl_high;
- unsigned char dl_low;
-} hw_baud_table[5];
-
-#ifdef CONFIG_STAMP
-extern unsigned long pll_div_fact;
-#endif
-
-#endif
diff --git a/cpu/bf537/start.S b/cpu/bf537/start.S
deleted file mode 100644
index a48f3c6..0000000
--- a/cpu/bf537/start.S
+++ /dev/null
@@ -1,576 +0,0 @@
-/*
- * U-boot - start.S Startup file of u-boot for BF537
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on head.S
- * Copyright (c) 2003 Metrowerks/Motorola
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * Note: A change in this file subsequently requires a change in
- * board/$(board_name)/config.mk for a valid u-boot.bin
- */
-
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/dma.h>
-#include <asm/mach-common/bits/pll.h>
-
-.global _stext;
-.global __bss_start;
-.global start;
-.global _start;
-.global edata;
-.global _exit;
-.global init_sdram;
-.global _icache_enable;
-.global _dcache_enable;
-#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
-.global _memory_post_test;
-.global _post_flag;
-#endif
-
-#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-#endif
-
-.text
-_start:
-start:
-_stext:
-
- R0 = 0x32;
- SYSCFG = R0;
- SSYNC;
-
- /* As per HW reference manual DAG registers,
- * DATA and Address resgister shall be zero'd
- * in initialization, after a reset state
- */
- r1 = 0; /* Data registers zero'd */
- r2 = 0;
- r3 = 0;
- r4 = 0;
- r5 = 0;
- r6 = 0;
- r7 = 0;
-
- p0 = 0; /* Address registers zero'd */
- p1 = 0;
- p2 = 0;
- p3 = 0;
- p4 = 0;
- p5 = 0;
-
- i0 = 0; /* DAG Registers zero'd */
- i1 = 0;
- i2 = 0;
- i3 = 0;
- m0 = 0;
- m1 = 0;
- m3 = 0;
- m3 = 0;
- l0 = 0;
- l1 = 0;
- l2 = 0;
- l3 = 0;
- b0 = 0;
- b1 = 0;
- b2 = 0;
- b3 = 0;
-
- /* Set loop counters to zero, to make sure that
- * hw loops are disabled.
- */
- r0 = 0;
- lc0 = r0;
- lc1 = r0;
-
- SSYNC;
-
- /* Check soft reset status */
- p0.h = SWRST >> 16;
- p0.l = SWRST & 0xFFFF;
- r0.l = w[p0];
-
- cc = bittst(r0, 15);
- if !cc jump no_soft_reset;
-
- /* Clear Soft reset */
- r0 = 0x0000;
- w[p0] = r0;
- ssync;
-
-no_soft_reset:
- nop;
-
- /* Clear EVT registers */
- p0.h = (EVT0 >> 16);
- p0.l = (EVT0 & 0xFFFF);
- p0 += 8;
- p1 = 14;
- r1 = 0;
- LSETUP(4,4) lc0 = p1;
- [ p0 ++ ] = r1;
-
-#if (BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT)
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-#endif
-
-#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
-
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over, */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-#endif
-
- /*
- * We now are running at speed, time to set the Async mem bank wait states
- * This will speed up execution, since we are normally running from FLASH.
- * we need to read MAC address from FLASH
- */
- p2.h = (EBIU_AMBCTL1 >> 16);
- p2.l = (EBIU_AMBCTL1 & 0xFFFF);
- r0.h = (AMBCTL1VAL >> 16);
- r0.l = (AMBCTL1VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMBCTL0 >> 16);
- p2.l = (EBIU_AMBCTL0 & 0xFFFF);
- r0.h = (AMBCTL0VAL >> 16);
- r0.l = (AMBCTL0VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMGCTL >> 16);
- p2.l = (EBIU_AMGCTL & 0xffff);
- r0 = AMGCTLVAL;
- w[p2] = r0;
- ssync;
-
-#if ((BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT) && (BFIN_BOOT_MODE != BF537_UART_BOOT))
- sp.l = (0xffb01000 & 0xFFFF);
- sp.h = (0xffb01000 >> 16);
-
- call init_sdram;
-#endif
-
-
-#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
- /* DMA POST code to Hi of L1 SRAM */
-postcopy:
- /* P1 Points to the beginning of SYSTEM MMR Space */
- P1.H = hi(SYSMMR_BASE);
- P1.L = lo(SYSMMR_BASE);
-
- R0.H = _text_l1;
- R0.L = _text_l1;
- R1.H = _etext_l1;
- R1.L = _etext_l1;
- R2 = R1 - R0; /* Count */
- R0.H = _etext;
- R0.L = _etext;
- R1.H = (CFG_MONITOR_BASE >> 16);
- R1.L = (CFG_MONITOR_BASE & 0xFFFF);
- R0 = R0 - R1;
- R1.H = (CFG_FLASH_BASE >> 16);
- R1.L = (CFG_FLASH_BASE & 0xFFFF);
- R0 = R0 + R1; /* Source Address */
- R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
- R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
- R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
- /* Destination DMAConfig Value (8-bit words) */
- R4.L = (DI_EN | WNR | DMAEN);
-
- R6 = 0x1 (Z);
- W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
- W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
-
- [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
- W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
- /* Set Source DMAConfig = DMA Enable,
- Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
- W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
-
- [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
- W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
- /* Set Destination DMAConfig = DMA Enable,
- Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
- W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-
-POST_DMA_DONE:
- p0.h = hi(MDMA_D0_IRQ_STATUS);
- p0.l = lo(MDMA_D0_IRQ_STATUS);
- R0 = W[P0](Z);
- CC = BITTST(R0, 0);
- if ! CC jump POST_DMA_DONE
-
- R0 = 0x1;
- W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
-
- /* DMA POST data to Hi of L1 SRAM */
- R0.H = _rodata_l1;
- R0.L = _rodata_l1;
- R1.H = _erodata_l1;
- R1.L = _erodata_l1;
- R2 = R1 - R0; /* Count */
- R0.H = _erodata;
- R0.L = _erodata;
- R1.H = (CFG_MONITOR_BASE >> 16);
- R1.L = (CFG_MONITOR_BASE & 0xFFFF);
- R0 = R0 - R1;
- R1.H = (CFG_FLASH_BASE >> 16);
- R1.L = (CFG_FLASH_BASE & 0xFFFF);
- R0 = R0 + R1; /* Source Address */
- R1.H = hi(DATA_BANKB_SRAM); /* Destination Address (high) */
- R1.L = lo(DATA_BANKB_SRAM); /* Destination Address (low) */
- R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
- R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
-
- R6 = 0x1 (Z);
- W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
- W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
-
- [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
- W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
- /* Set Source DMAConfig = DMA Enable,
- Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
- W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
-
- [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
- W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
- /* Set Destination DMAConfig = DMA Enable,
- Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
- W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-
-POST_DATA_DMA_DONE:
- p0.h = hi(MDMA_D0_IRQ_STATUS);
- p0.l = lo(MDMA_D0_IRQ_STATUS);
- R0 = W[P0](Z);
- CC = BITTST(R0, 0);
- if ! CC jump POST_DATA_DMA_DONE
-
- R0 = 0x1;
- W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
-
- p0.l = _memory_post_test;
- p0.h = _memory_post_test;
- r0 = 0x0;
- call (p0);
- r7 = r0; /* save return value */
-
- call init_sdram;
-#endif
-
- /* relocate into to RAM */
- call get_pc;
-offset:
- r2.l = offset;
- r2.h = offset;
- r3.l = start;
- r3.h = start;
- r1 = r2 - r3;
-
- r0 = r0 - r1;
- p1 = r0;
-
- p2.l = (CFG_MONITOR_BASE & 0xffff);
- p2.h = (CFG_MONITOR_BASE >> 16);
-
- p3 = 0x04;
- p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
- p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
-loop1:
- r1 = [p1 ++ p3];
- [p2 ++ p3] = r1;
- cc=p2==p4;
- if !cc jump loop1;
- /*
- * configure STACK
- */
- r0.h = (CONFIG_STACKBASE >> 16);
- r0.l = (CONFIG_STACKBASE & 0xFFFF);
- sp = r0;
- fp = sp;
-
- /*
- * This next section keeps the processor in supervisor mode
- * during kernel boot. Switches to user mode at end of boot.
- * See page 3-9 of Hardware Reference manual for documentation.
- */
-
- /* To keep ourselves in the supervisor mode */
- p0.l = (EVT15 & 0xFFFF);
- p0.h = (EVT15 >> 16);
-
- p1.l = _real_start;
- p1.h = _real_start;
- [p0] = p1;
-
- p0.l = (IMASK & 0xFFFF);
- p0.h = (IMASK >> 16);
- r0.l = LO(EVT_IVG15);
- r0.h = HI(EVT_IVG15);
- [p0] = r0;
- raise 15;
- p0.l = WAIT_HERE;
- p0.h = WAIT_HERE;
- reti = p0;
- rti;
-
-WAIT_HERE:
- jump WAIT_HERE;
-
-.global _real_start;
-_real_start:
- [ -- sp ] = reti;
-
-#ifdef CONFIG_BF537
-/* Initialise General-Purpose I/O Modules on BF537
- * Rev 0.0 Anomaly 05000212 - PORTx_FER,
- * PORT_MUX Registers Do Not accept "writes" correctly
- */
- p0.h = hi(PORTF_FER);
- p0.l = lo(PORTF_FER);
- R0.L = W[P0]; /* Read */
- nop;
- nop;
- nop;
- ssync;
- R0 = 0x000F(Z);
- W[P0] = R0.L; /* Write */
- nop;
- nop;
- nop;
- ssync;
- W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */
- nop;
- nop;
- nop;
- ssync;
-
- p0.h = hi(PORTH_FER);
- p0.l = lo(PORTH_FER);
- R0.L = W[P0]; /* Read */
- nop;
- nop;
- nop;
- ssync;
- R0 = 0xFFFF(Z);
- W[P0] = R0.L; /* Write */
- nop;
- nop;
- nop;
- ssync;
- W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */
- nop;
- nop;
- nop;
- ssync;
-
-#endif
-
- /* DMA reset code to Hi of L1 SRAM */
-copy:
- P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
- P1.L = lo(SYSMMR_BASE);
-
- R0.H = reset_start; /* Source Address (high) */
- R0.L = reset_start; /* Source Address (low) */
- R1.H = reset_end;
- R1.L = reset_end;
- R2 = R1 - R0; /* Count */
- R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
- R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
- R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
- R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
-
-DMA:
- R6 = 0x1 (Z);
- W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
- W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
-
- [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
- W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
- /* Set Source DMAConfig = DMA Enable,
- Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
- W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
-
- [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
- W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
- /* Set Destination DMAConfig = DMA Enable,
- Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
- W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-
-WAIT_DMA_DONE:
- p0.h = hi(MDMA_D0_IRQ_STATUS);
- p0.l = lo(MDMA_D0_IRQ_STATUS);
- R0 = W[P0](Z);
- CC = BITTST(R0, 0);
- if ! CC jump WAIT_DMA_DONE
-
- R0 = 0x1;
- W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
-
- /* Initialize BSS Section with 0 s */
- p1.l = __bss_start;
- p1.h = __bss_start;
- p2.l = _end;
- p2.h = _end;
- r1 = p1;
- r2 = p2;
- r3 = r2 - r1;
- r3 = r3 >> 2;
- p3 = r3;
- lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
- CC = p2<=p1;
- if CC jump _clear_bss_skip;
- r0 = 0;
-_clear_bss:
-_clear_bss_end:
- [p1++] = r0;
-_clear_bss_skip:
-
-#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
- p0.l = _post_flag;
- p0.h = _post_flag;
- r0 = r7;
- [p0] = r0;
-#endif
-
- p0.l = _start1;
- p0.h = _start1;
- jump (p0);
-
-reset_start:
- p0.h = WDOG_CNT >> 16;
- p0.l = WDOG_CNT & 0xffff;
- r0 = 0x0010;
- w[p0] = r0;
- p0.h = WDOG_CTL >> 16;
- p0.l = WDOG_CTL & 0xffff;
- r0 = 0x0000;
- w[p0] = r0;
-reset_wait:
- jump reset_wait;
-
-reset_end:
- nop;
-
-_exit:
- jump.s _exit;
-get_pc:
- r0 = rets;
- rts;
diff --git a/cpu/bf537/start1.S b/cpu/bf537/start1.S
deleted file mode 100644
index 6d4731b..0000000
--- a/cpu/bf537/start1.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * U-boot - start1.S Code running out of RAM after relocation
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#define ASSEMBLY
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-.global start1;
-.global _start1;
-
-.text
-_start1:
-start1:
- sp += -12;
- call _board_init_f;
- sp += 12;
diff --git a/cpu/bf537/traps.c b/cpu/bf537/traps.c
deleted file mode 100644
index 51de322..0000000
--- a/cpu/bf537/traps.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * U-boot - traps.c Routines related to interrupts and exceptions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * No original Copyright holder listed,
- * Probabily original (C) Roman Zippel (assigned DJD, 1999)
- *
- * Copyright 2003 Metrowerks - for Blackfin
- * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
- * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <asm/errno.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include "cpu.h"
-#include <asm/cplb.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
-
-void init_IRQ(void)
-{
- blackfin_init_IRQ();
- return;
-}
-
-void process_int(unsigned long vec, struct pt_regs *fp)
-{
- printf("interrupt\n");
- return;
-}
-
-extern unsigned int icplb_table[page_descriptor_table_size][2];
-extern unsigned int dcplb_table[page_descriptor_table_size][2];
-
-unsigned long last_cplb_fault_retx;
-
-static unsigned int cplb_sizes[4] =
- { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
-
-void trap_c(struct pt_regs *regs)
-{
- unsigned int addr;
- unsigned long trapnr = (regs->seqstat) & EXCAUSE;
- unsigned int i, j, size, *I0, *I1;
- unsigned short data = 0;
-
- switch (trapnr) {
- /* 0x26 - Data CPLB Miss */
- case VEC_CPLB_M:
-
-#if ANOMALY_05000261
- /*
- * Work around an anomaly: if we see a new DCPLB fault,
- * return without doing anything. Then,
- * if we get the same fault again, handle it.
- */
- addr = last_cplb_fault_retx;
- last_cplb_fault_retx = regs->retx;
- printf("this time, curr = 0x%08x last = 0x%08x\n",
- addr, last_cplb_fault_retx);
- if (addr != last_cplb_fault_retx)
- goto trap_c_return;
-#endif
- data = 1;
-
- case VEC_CPLB_I_M:
-
- if (data) {
- addr = *pDCPLB_FAULT_ADDR;
- } else {
- addr = *pICPLB_FAULT_ADDR;
- }
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (data) {
- size = cplb_sizes[dcplb_table[i][1] >> 16];
- j = dcplb_table[i][0];
- } else {
- size = cplb_sizes[icplb_table[i][1] >> 16];
- j = icplb_table[i][0];
- }
- if ((j <= addr) && ((j + size) > addr)) {
- debug("found %i 0x%08x\n", i, j);
- break;
- }
- }
- if (i == page_descriptor_table_size) {
- printf("something is really wrong\n");
- do_reset(NULL, 0, 0, NULL);
- }
-
- /* Turn the cache off */
- if (data) {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL &=
- ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
- } else {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
- SSYNC();
- }
-
- if (data) {
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
- } else {
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
- }
-
- j = 0;
- while (*I1 & CPLB_LOCK) {
- debug("skipping %i %08p - %08x\n", j, I1, *I1);
- *I0++;
- *I1++;
- j++;
- }
-
- debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
-
- for (; j < 15; j++) {
- debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
- *I0++ = *(I0 + 1);
- *I1++ = *(I1 + 1);
- }
-
- if (data) {
- *I0 = dcplb_table[i][0];
- *I1 = dcplb_table[i][1];
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
- } else {
- *I0 = icplb_table[i][0];
- *I1 = icplb_table[i][1];
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
- }
-
- for (j = 0; j < 16; j++) {
- debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
- }
-
- /* Turn the cache back on */
- if (data) {
- j = *(unsigned int *)DMEM_CONTROL;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL =
- ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
- SSYNC();
- } else {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
- SSYNC();
- }
-
- break;
- default:
- /* All traps come here */
- printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
- printf("stack frame=0x%x, ", (unsigned int)regs);
- printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
- dump(regs);
- printf("\n\n");
-
- printf("Unhandled IRQ or exceptions!\n");
- printf("Please reset the board \n");
- do_reset(NULL, 0, 0, NULL);
- }
-
-trap_c_return:
- return;
-
-}
-
-void dump(struct pt_regs *fp)
-{
- debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n",
- fp->rete, fp->retn, fp->retx, fp->rets);
- debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
- debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
- debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
- fp->r0, fp->r1, fp->r2, fp->r3);
- debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
- fp->r4, fp->r5, fp->r6, fp->r7);
- debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
- fp->p0, fp->p1, fp->p2, fp->p3);
- debug("P4: %08lx P5: %08lx FP: %08lx\n",
- fp->p4, fp->p5, fp->fp);
- debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
- fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
- debug("LB0: %08lx LT0: %08lx LC0: %08lx\n",
- fp->lb0, fp->lt0, fp->lc0);
- debug("LB1: %08lx LT1: %08lx LC1: %08lx\n",
- fp->lb1, fp->lt1, fp->lc1);
- debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n",
- fp->b0, fp->l0, fp->m0, fp->i0);
- debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n",
- fp->b1, fp->l1, fp->m1, fp->i1);
- debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n",
- fp->b2, fp->l2, fp->m2, fp->i2);
- debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n",
- fp->b3, fp->l3, fp->m3, fp->i3);
-
- debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
- debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
-
-}
diff --git a/cpu/bf537/video.c b/cpu/bf537/video.c
deleted file mode 100644
index 3ff0151..0000000
--- a/cpu/bf537/video.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
- * (C) Copyright 2002
- * Wolfgang Denk, wd@denx.de
- * (C) Copyright 2006
- * Aubrey Li, aubrey.li@analog.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <devices.h>
-
-#ifdef CONFIG_VIDEO
-#define NTSC_FRAME_ADDR 0x06000000
-#include "video.h"
-
-/* NTSC OUTPUT SIZE 720 * 240 */
-#define VERTICAL 2
-#define HORIZONTAL 4
-
-int is_vblank_line(const int line)
-{
- /*
- * This array contains a single bit for each line in
- * an NTSC frame.
- */
- if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
- return true;
-
- return false;
-}
-
-int NTSC_framebuffer_init(char *base_address)
-{
- const int NTSC_frames = 1;
- const int NTSC_lines = 525;
- char *dest = base_address;
- int frame_num, line_num;
-
- for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
- for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
- unsigned int code;
- int offset = 0;
- int i;
-
- if (is_vblank_line(line_num))
- offset++;
-
- if (line_num > 266 || line_num < 3)
- offset += 2;
-
- /* Output EAV code */
- code = SystemCodeMap[offset].EAV;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output horizontal blanking */
- for (i = 0; i < 67 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
-
- /* Output SAV */
- code = SystemCodeMap[offset].SAV;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output empty horizontal data */
- for (i = 0; i < 360 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
- }
- }
-
- return dest - base_address;
-}
-
-void fill_frame(char *Frame, int Value)
-{
- int *OddPtr32;
- int OddLine;
- int *EvenPtr32;
- int EvenLine;
- int i;
- int *data;
- int m, n;
-
- /* fill odd and even frames */
- for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
- OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
- EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
- for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
- *OddPtr32 = Value;
- *EvenPtr32 = Value;
- }
- }
-
- for (m = 0; m < VERTICAL; m++) {
- data = (int *)u_boot_logo.data;
- for (OddLine = (22 + m), EvenLine = (285 + m);
- OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
- OddLine += VERTICAL, EvenLine += VERTICAL) {
- OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
- EvenPtr32 =
- (int *)((Frame + ((EvenLine) * 1716)) + 276);
- for (i = 0; i < u_boot_logo.width / 2; i++) {
- /* enlarge one pixel to m x n */
- for (n = 0; n < HORIZONTAL; n++) {
- *OddPtr32++ = *data;
- *EvenPtr32++ = *data;
- }
- data++;
- }
- }
- }
-}
-
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
-static int video_init(void)
-{
- char *NTSCFrame;
- NTSCFrame = (char *)NTSC_FRAME_ADDR;
- NTSC_framebuffer_init(NTSCFrame);
- fill_frame(NTSCFrame, BLUE);
-
- *pPPI_CONTROL = 0x0082;
- *pPPI_FRAME = 0x020D;
-
- *pDMA0_START_ADDR = NTSCFrame;
- *pDMA0_X_COUNT = 0x035A;
- *pDMA0_X_MODIFY = 0x0002;
- *pDMA0_Y_COUNT = 0x020D;
- *pDMA0_Y_MODIFY = 0x0002;
- *pDMA0_CONFIG = 0x1015;
- *pPPI_CONTROL = 0x0083;
- return 0;
-}
-
-int drv_video_init(void)
-{
- int error, devices = 1;
-
- device_t videodev;
-
- video_init(); /* Video initialization */
-
- memset(&videodev, 0, sizeof(videodev));
-
- strcpy(videodev.name, "video");
- videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
- videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */
- videodev.putc = video_putc; /* 'putc' function */
- videodev.puts = video_puts; /* 'puts' function */
-
- error = device_register(&videodev);
-
- return (error == 0) ? devices : error;
-}
-#endif
diff --git a/cpu/bf537/video.h b/cpu/bf537/video.h
deleted file mode 100644
index a43553f..0000000
--- a/cpu/bf537/video.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#include <video_logo.h>
-#define write_dest_byte(val) {*dest++=val;}
-#define BLACK (0x01800180) /* black pixel pattern */
-#define BLUE (0x296E29F0) /* blue pixel pattern */
-#define RED (0x51F0515A) /* red pixel pattern */
-#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern*/
-#define GREEN (0x91229136) /* green pixel pattern */
-#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
-#define YELLOW (0xD292D210) /* yellow pixel pattern */
-#define WHITE (0xFE80FE80) /* white pixel pattern */
-
-#define true 1
-#define false 0
-
-typedef struct {
- unsigned int SAV;
- unsigned int EAV;
-} SystemCodeType;
-
-const SystemCodeType SystemCodeMap[4] = {
- {0xFF000080, 0xFF00009D},
- {0xFF0000AB, 0xFF0000B6},
- {0xFF0000C7, 0xFF0000DA},
- {0xFF0000EC, 0xFF0000F1}
-};
diff --git a/cpu/bf561/cache.S b/cpu/bf561/cache.S
deleted file mode 100644
index d9015c6..0000000
--- a/cpu/bf561/cache.S
+++ /dev/null
@@ -1,129 +0,0 @@
-#define ASSEMBLY
-#include <asm/linkage.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/mpu.h>
-
-.text
-.align 2
-ENTRY(_blackfin_icache_flush_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
- 1:
- IFLUSH[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
- IFLUSH[P0];
- SSYNC;
- RTS;
-
-ENTRY(_blackfin_dcache_flush_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
-1:
- FLUSH[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
- FLUSH[P0];
- SSYNC;
- RTS;
-
-ENTRY(_icache_invalidate)
-ENTRY(_invalidate_entire_icache)
- [--SP] = (R7:5);
-
- P0.L = (IMEM_CONTROL & 0xFFFF);
- P0.H = (IMEM_CONTROL >> 16);
- R7 =[P0];
-
- /*
- * Clear the IMC bit , All valid bits in the instruction
- * cache are set to the invalid state
- */
- BITCLR(R7, IMC_P);
- CLI R6;
- /* SSYNC required before invalidating cache. */
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- /* Configures the instruction cache agian */
- R6 = (IMC | ENICPLB);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- (R7:5) =[SP++];
- RTS;
-
-/*
- * Invalidate the Entire Data cache by
- * clearing DMC[1:0] bits
- */
-ENTRY(_invalidate_entire_dcache)
-ENTRY(_dcache_invalidate)
- [--SP] = (R7:6);
-
- P0.L = (DMEM_CONTROL & 0xFFFF);
- P0.H = (DMEM_CONTROL >> 16);
- R7 =[P0];
-
- /*
- * Clear the DMC[1:0] bits, All valid bits in the data
- * cache are set to the invalid state
- */
- BITCLR(R7, DMC0_P);
- BITCLR(R7, DMC1_P);
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
- /* Configures the data cache again */
-
- R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC;
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- (R7:6) =[SP++];
- RTS;
-
-ENTRY(_blackfin_dcache_invalidate_range)
- R2 = -32;
- R2 = R0 & R2;
- P0 = R2;
- P1 = R1;
- CSYNC;
-1:
- FLUSHINV[P0++];
- CC = P0 < P1(iu);
- IF CC JUMP 1b(bp);
-
- /*
- * If the data crosses a cache line, then we'll be pointing to
- * the last cache line, but won't have flushed/invalidated it yet, so do
- * one more.
- */
- FLUSHINV[P0];
- SSYNC;
- RTS;
diff --git a/cpu/bf561/config.mk b/cpu/bf561/config.mk
deleted file mode 100644
index 3628a02..0000000
--- a/cpu/bf561/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-# U-boot - config.mk
-#
-# Copyright (c) 2005-2007 Analog Devices Inc.
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-PLATFORM_RELFLAGS += -mcpu=bf561
diff --git a/cpu/bf561/cpu.c b/cpu/bf561/cpu.c
deleted file mode 100644
index e0dd2f5..0000000
--- a/cpu/bf561/cpu.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * U-boot - cpu.c CPU specific functions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <command.h>
-#include <asm/entry.h>
-#include <asm/cplb.h>
-#include <asm/io.h>
-
-#define CACHE_ON 1
-#define CACHE_OFF 0
-
-extern unsigned int icplb_table[page_descriptor_table_size][2];
-extern unsigned int dcplb_table[page_descriptor_table_size][2];
-
-int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
- __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
- );
-
- return 0;
-}
-
-/* These functions are just used to satisfy the linker */
-int cpu_init(void)
-{
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- return 0;
-}
-
-void icache_enable(void)
-{
- unsigned int *I0, *I1;
- int i, j = 0;
-
- /* Before enable icache, disable it first */
- icache_disable();
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
-
- /* make sure the locked ones go in first */
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (CPLB_LOCK & icplb_table[i][1]) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- icplb_table[i][0], icplb_table[i][1]);
- *I0++ = icplb_table[i][0];
- *I1++ = icplb_table[i][1];
- j++;
- }
- }
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (!(CPLB_LOCK & icplb_table[i][1])) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- icplb_table[i][0], icplb_table[i][1]);
- *I0++ = icplb_table[i][0];
- *I1++ = icplb_table[i][1];
- j++;
- if (j == 16) {
- break;
- }
- }
- }
-
- /* Fill the rest with invalid entry */
- if (j <= 15) {
- for (; j < 16; j++) {
- debug("filling %i with 0", j);
- *I1++ = 0x0;
- }
-
- }
-
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
- SSYNC();
-}
-
-void icache_disable(void)
-{
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
- SSYNC();
-}
-
-int icache_status(void)
-{
- unsigned int value;
- value = *(unsigned int *)IMEM_CONTROL;
-
- if (value & (IMC | ENICPLB))
- return CACHE_ON;
- else
- return CACHE_OFF;
-}
-
-void dcache_enable(void)
-{
- unsigned int *I0, *I1;
- unsigned int temp;
- int i, j = 0;
-
- /* Before enable dcache, disable it first */
- dcache_disable();
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
-
- /* make sure the locked ones go in first */
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (CPLB_LOCK & dcplb_table[i][1]) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- *I0++ = dcplb_table[i][0];
- *I1++ = dcplb_table[i][1];
- j++;
- } else {
- debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- }
- }
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (!(CPLB_LOCK & dcplb_table[i][1])) {
- debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
- dcplb_table[i][0], dcplb_table[i][1]);
- *I0++ = dcplb_table[i][0];
- *I1++ = dcplb_table[i][1];
- j++;
- if (j == 16) {
- break;
- }
- }
- }
-
- /* Fill the rest with invalid entry */
- if (j <= 15) {
- for (; j < 16; j++) {
- debug("filling %i with 0", j);
- *I1++ = 0x0;
- }
- }
-
- temp = *(unsigned int *)DMEM_CONTROL;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL =
- ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
- SSYNC();
-}
-
-void dcache_disable(void)
-{
-
- unsigned int *I0, *I1;
- int i;
-
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL &=
- ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
-
- /* after disable dcache, clear it so we don't confuse the next application */
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
-
- for (i = 0; i < 16; i++) {
- *I0++ = 0x0;
- *I1++ = 0x0;
- }
-}
-
-int dcache_status(void)
-{
- unsigned int value;
- value = *(unsigned int *)DMEM_CONTROL;
- if (value & (ENDCPLB))
- return CACHE_ON;
- else
- return CACHE_OFF;
-}
diff --git a/cpu/bf561/cpu.h b/cpu/bf561/cpu.h
deleted file mode 100644
index b6b73b1..0000000
--- a/cpu/bf561/cpu.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * U-boot - cpu.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _CPU_H_
-#define _CPU_H_
-
-#include <command.h>
-
-#define INTERNAL_IRQS (32)
-#define NUM_IRQ_NODES 16
-#define DEF_INTERRUPT_FLAGS 1
-#define MAX_TIM_LOAD 0xFFFFFFFF
-
-void blackfin_irq_panic(int reason, struct pt_regs *reg);
-extern void dump(struct pt_regs *regs);
-void display_excp(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_exception(void);
-asmlinkage void trap(void);
-asmlinkage void evt_ivhw(void);
-asmlinkage void evt_rst(void);
-asmlinkage void evt_timer(void);
-asmlinkage void evt_evt7(void);
-asmlinkage void evt_evt8(void);
-asmlinkage void evt_evt9(void);
-asmlinkage void evt_evt10(void);
-asmlinkage void evt_evt11(void);
-asmlinkage void evt_evt12(void);
-asmlinkage void evt_evt13(void);
-asmlinkage void evt_soft_int1(void);
-asmlinkage void evt_system_call(void);
-void blackfin_irq_panic(int reason, struct pt_regs *regs);
-void blackfin_free_irq(unsigned int irq, void *dev_id);
-void call_isr(int irq, struct pt_regs *fp);
-void blackfin_do_irq(int vec, struct pt_regs *fp);
-void blackfin_init_IRQ(void);
-void blackfin_enable_irq(unsigned int irq);
-void blackfin_disable_irq(unsigned int irq);
-extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
-int blackfin_request_irq(unsigned int irq,
- void (*handler) (int, void *, struct pt_regs *),
- unsigned long flags, const char *devname,
- void *dev_id);
-void timer_init(void);
-#endif
diff --git a/cpu/bf561/flush.S b/cpu/bf561/flush.S
deleted file mode 100644
index 0140a60..0000000
--- a/cpu/bf561/flush.S
+++ /dev/null
@@ -1,402 +0,0 @@
-/* Copyright (C) 2003-2007 Analog Devices Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.
- */
-
-#define ASSEMBLY
-
-#include <asm/linkage.h>
-#include <asm/cplb.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-.text
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the instruction cache.
- */
-
-ENTRY(_flush_instruction_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = (ICPLB_ADDR0 >> 16);
- P5.L = (ICPLB_ADDR0 & 0xFFFF);
- P4.H = (ICPLB_DATA0 >> 16);
- P4.L = (ICPLB_DATA0 & 0xFFFF);
- R7 = CPLB_VALID | CPLB_L1_CHBL;
- R6 = 16;
-inext: R0 = [P5++];
- R1 = [P4++];
- [--SP] = RETS;
- CALL _icplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-iskip: R6 += -1;
- CC = R6;
- IF CC JUMP inext;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular ICPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_icplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP iflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /*Anamoly 05000209*/
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
- R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/
-
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = (ITEST_COMMAND & 0xFFFF);
- P5.H = (ITEST_COMMAND >> 16);
- P4.L = (ITEST_DATA0 & 0xFFFF);
- P4.H = (ITEST_DATA0 >> 16);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 4;
- LSETUP (ifs1, ife1) LC1 = P2;
-ifs1: P0 = 32; /* iterate over all sets*/
- LSETUP (ifs0, ife0) LC0 = P0;
-ifs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- [P5] = R6; /* Issue Command*/
- SSYNC; /* CSYNC will not work here :(*/
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP ifskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- IFLUSH [P3]; /* And flush the entry*/
-ifskip:
-ife0: R5 += 1; /* Advance to next Set*/
-ife1: NOP;
-
-ifinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-iflush_whole_page:
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- IFLUSH [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (isall, ieall) LC0 = P1;
-isall:IFLUSH [P0++];
-ieall: NOP;
- SSYNC;
- JUMP ifinished;
-
-/* This is an external function being called by the user
- * application through __flush_cache_all. Currently this function
- * serves the purpose of flushing all the pending writes in
- * in the data cache.
- */
-
-ENTRY(_flush_data_cache)
- [--SP] = ( R7:6, P5:4 );
- LINK 12;
- SP += -12;
- P5.H = (DCPLB_ADDR0 >> 16);
- P5.L = (DCPLB_ADDR0 & 0xFFFF);
- P4.H = (DCPLB_DATA0 >> 16);
- P4.L = (DCPLB_DATA0 & 0xFFFF);
- R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
- R6 = 16;
-next: R0 = [P5++];
- R1 = [P4++];
- CC = BITTST(R1, 14); /* Is it write-through?*/
- IF CC JUMP skip; /* If so, ignore it.*/
- R2 = R1 & R7; /* Is it a dirty, cached page?*/
- CC = R2;
- IF !CC JUMP skip; /* If not, ignore it.*/
- [--SP] = RETS;
- CALL _dcplb_flush; /* R0 = page, R1 = data*/
- RETS = [SP++];
-skip: R6 += -1;
- CC = R6;
- IF CC JUMP next;
- SSYNC;
- SP += 12;
- UNLINK;
- ( R7:6, P5:4 ) = [SP++];
- RTS;
-
-/* This is an internal function to flush all pending
- * writes in the cache associated with a particular DCPLB.
- *
- * R0 - page's start address
- * R1 - CPLB's data field.
- */
-
-.align 2
-ENTRY(_dcplb_flush)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = LC0;
- [--SP] = LT0;
- [--SP] = LB0;
- [--SP] = LC1;
- [--SP] = LT1;
- [--SP] = LB1;
-
- /* If it's a 1K or 4K page, then it's quickest to
- * just systematically flush all the addresses in
- * the page, regardless of whether they're in the
- * cache, or dirty. If it's a 1M or 4M page, there
- * are too many addresses, and we have to search the
- * cache for lines corresponding to the page.
- */
-
- CC = BITTST(R1, 17); /* 1MB or 4MB */
- IF !CC JUMP dflush_whole_page;
-
- /* We're only interested in the page's size, so extract
- * this from the CPLB (bits 17:16), and scale to give an
- * offset into the page_size and page_prefix tables.
- */
-
- R1 <<= 14;
- R1 >>= 30;
- R1 <<= 2;
-
- /* The page could be mapped into Bank A or Bank B, depending
- * on (a) whether both banks are configured as cache, and
- * (b) on whether address bit A[x] is set. x is determined
- * by DCBS in DMEM_CONTROL
- */
-
- R2 = 0; /* Default to Bank A (Bank B would be 1)*/
-
- P0.L = (DMEM_CONTROL & 0xFFFF);
- P0.H = (DMEM_CONTROL >> 16);
-
- R3 = [P0]; /* If Bank B is not enabled as cache*/
- CC = BITTST(R3, 2); /* then Bank A is our only option.*/
- IF CC JUMP bank_chosen;
-
- R4 = 1<<14; /* If DCBS==0, use A[14].*/
- R5 = R4 << 7; /* If DCBS==1, use A[23];*/
- CC = BITTST(R3, 4);
- IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
- R5 = R0 & R4; /* Use it to test the Page address*/
- CC = R5; /* and if that bit is set, we use Bank B,*/
- R2 = CC; /* else we use Bank A.*/
- R2 <<= 23; /* The Bank selection's at posn 23.*/
-
-bank_chosen:
-
- /* We can also determine the sub-bank used, because this is
- * taken from bits 13:12 of the address.
- */
-
- R3 = ((12<<8)|2); /* Extraction pattern */
- nop; /*Anamoly 05000209*/
- R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
- /* Save in extraction pattern for later deposit.*/
- R3.H = R4.L << 0;
-
- /* So:
- * R0 = Page start
- * R1 = Page length (actually, offset into size/prefix tables)
- * R2 = Bank select mask
- * R3 = sub-bank deposit values
- *
- * The cache has 2 Ways, and 64 sets, so we iterate through
- * the sets, accessing the tag for each Way, for our Bank and
- * sub-bank, looking for dirty, valid tags that match our
- * address prefix.
- */
-
- P5.L = (DTEST_COMMAND & 0xFFFF);
- P5.H = (DTEST_COMMAND >> 16);
- P4.L = (DTEST_DATA0 & 0xFFFF);
- P4.H = (DTEST_DATA0 >> 16);
-
- P0.L = page_prefix_table;
- P0.H = page_prefix_table;
- P1 = R1;
- R5 = 0; /* Set counter*/
- P0 = P1 + P0;
- R4 = [P0]; /* This is the address prefix*/
-
-
- /* We're reading (bit 1==0) the tag (bit 2==0), and we
- * don't care about which double-word, since we're only
- * fetching tags, so we only have to set Set, Bank,
- * Sub-bank and Way.
- */
-
- P2 = 2;
- LSETUP (fs1, fe1) LC1 = P2;
-fs1: P0 = 64; /* iterate over all sets*/
- LSETUP (fs0, fe0) LC0 = P0;
-fs0: R6 = R5 << 5; /* Combine set*/
- R6.H = R3.H << 0 ; /* and sub-bank*/
- R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
- BITSET(R6,14);
- [P5] = R6; /* Issue Command*/
- SSYNC;
- R7 = [P4]; /* and read Tag.*/
- CC = BITTST(R7, 0); /* Check if valid*/
- IF !CC JUMP fskip; /* and skip if not.*/
- CC = BITTST(R7, 1); /* Check if dirty*/
- IF !CC JUMP fskip; /* and skip if not.*/
-
- /* Compare against the page address. First, plant bits 13:12
- * into the tag, since those aren't part of the returned data.
- */
-
- R7 = DEPOSIT(R7, R3); /* set 13:12*/
- R1 = R7 & R4; /* Mask off lower bits*/
- CC = R1 == R0; /* Compare against page start.*/
- IF !CC JUMP fskip; /* Skip it if it doesn't match.*/
-
- /* Tag address matches against page, so this is an entry
- * we must flush.
- */
-
- R7 >>= 10; /* Mask off the non-address bits*/
- R7 <<= 10;
- P3 = R7;
- SSYNC;
- FLUSHINV [P3]; /* And flush the entry*/
-fskip:
-fe0: R5 += 1; /* Advance to next Set*/
-fe1: BITSET(R2, 26); /* Go to next Way.*/
-
-dfinished:
- SSYNC; /* Ensure the data gets out to mem.*/
-
- /*Finished. Restore context.*/
- LB1 = [SP++];
- LT1 = [SP++];
- LC1 = [SP++];
- LB0 = [SP++];
- LT0 = [SP++];
- LC0 = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
-
-dflush_whole_page:
-
- /* It's a 1K or 4K page, so quicker to just flush the
- * entire page.
- */
-
- P1 = 32; /* For 1K pages*/
- P2 = P1 << 2; /* For 4K pages*/
- P0 = R0; /* Start of page*/
- CC = BITTST(R1, 16); /* Whether 1K or 4K*/
- IF CC P1 = P2;
- P1 += -1; /* Unroll one iteration*/
- SSYNC;
- FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
- LSETUP (eall, eall) LC0 = P1;
-eall: FLUSHINV [P0++];
- SSYNC;
- JUMP dfinished;
-
-.align 4;
-page_prefix_table:
-.byte4 0xFFFFFC00; /* 1K */
-.byte4 0xFFFFF000; /* 4K */
-.byte4 0xFFF00000; /* 1M */
-.byte4 0xFFC00000; /* 4M */
-.page_prefix_table.end:
diff --git a/cpu/bf561/init_sdram.S b/cpu/bf561/init_sdram.S
deleted file mode 100644
index f5ccf30..0000000
--- a/cpu/bf561/init_sdram.S
+++ /dev/null
@@ -1,175 +0,0 @@
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
-.global init_sdram;
-
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-
-init_sdram:
- [--SP] = ASTAT;
- [--SP] = RETS;
- [--SP] = (R7:0);
- [--SP] = (P5:0);
-
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over, */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-
- /*
- * We now are running at speed, time to set the Async mem bank wait states
- * This will speed up execution, since we are normally running from FLASH.
- */
-
- p2.h = (EBIU_AMBCTL1 >> 16);
- p2.l = (EBIU_AMBCTL1 & 0xFFFF);
- r0.h = (AMBCTL1VAL >> 16);
- r0.l = (AMBCTL1VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMBCTL0 >> 16);
- p2.l = (EBIU_AMBCTL0 & 0xFFFF);
- r0.h = (AMBCTL0VAL >> 16);
- r0.l = (AMBCTL0VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMGCTL >> 16);
- p2.l = (EBIU_AMGCTL & 0xffff);
- r0 = AMGCTLVAL;
- w[p2] = r0;
- ssync;
-
- /*
- * Now, Initialize the SDRAM,
- * start with the SDRAM Refresh Rate Control Register
- */
- p0.l = lo(EBIU_SDRRC);
- p0.h = hi(EBIU_SDRRC);
- r0 = mem_SDRRC;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Memory Bank Control Register - bank specific parameters
- */
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16);
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Global Control Register - global programmable parameters
- * Disable self-refresh
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITCLR (R0, 24);
-
- /*
- * Check if SDRAM is already powered up, if it is, enable self-refresh
- */
- p0.h = hi(EBIU_SDSTAT);
- p0.l = lo(EBIU_SDSTAT);
- r2.l = w[p0];
- cc = bittst(r2,3);
- if !cc jump skip;
- NOP;
- BITSET (R0, 23);
-skip:
- [P2] = R0;
- SSYNC;
-
- /* Write in the new value in the register */
- R0.L = lo(mem_SDGCTL);
- R0.H = hi(mem_SDGCTL);
- [P2] = R0;
- SSYNC;
- nop;
-
- (P5:0) = [SP++];
- (R7:0) = [SP++];
- RETS = [SP++];
- ASTAT = [SP++];
- RTS;
diff --git a/cpu/bf561/init_sdram_bootrom_initblock.S b/cpu/bf561/init_sdram_bootrom_initblock.S
deleted file mode 100644
index 9cc5e78..0000000
--- a/cpu/bf561/init_sdram_bootrom_initblock.S
+++ /dev/null
@@ -1,189 +0,0 @@
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
-.global init_sdram;
-
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-#endif
-
-init_sdram:
- [--SP] = ASTAT;
- [--SP] = RETS;
- [--SP] = (R7:0);
- [--SP] = (P5:0);
-
-
- p0.h = hi(SICA_IWR0);
- p0.l = lo(SICA_IWR0);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-
- p0.h = hi(SPI_BAUD);
- p0.l = lo(SPI_BAUD);
- r0.l = CONFIG_SPI_BAUD_INITBLOCK;
- w[p0] = r0.l;
- SSYNC;
-
- /*
- * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
- */
- p0.h = hi(PLL_LOCKCNT);
- p0.l = lo(PLL_LOCKCNT);
- r0 = 0x300(Z);
- w[p0] = r0.l;
- ssync;
-
- /*
- * Put SDRAM in self-refresh, incase anything is running
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITSET (R0, 24);
- [P2] = R0;
- SSYNC;
-
- /*
- * Set PLL_CTL with the value that we calculate in R0
- * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
- * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
- * - [7] = output delay (add 200ps of delay to mem signals)
- * - [6] = input delay (add 200ps of input delay to mem signals)
- * - [5] = PDWN : 1=All Clocks off
- * - [3] = STOPCK : 1=Core Clock off
- * - [1] = PLL_OFF : 1=Disable Power to PLL
- * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
- * all other bits set to zero
- */
-
- r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
- r0 = r0 << 9; /* Shift it over, */
- r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */
- r0 = r1 | r0;
- r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
- r1 = r1 << 8; /* Shift it over */
- r0 = r1 | r0; /* add them all together */
-
- p0.h = hi(PLL_CTL);
- p0.l = lo(PLL_CTL); /* Load the address */
- cli r2; /* Disable interrupts */
- ssync;
- w[p0] = r0.l; /* Set the value */
- idle; /* Wait for the PLL to stablize */
- sti r2; /* Enable interrupts */
-
-check_again:
- p0.h = hi(PLL_STAT);
- p0.l = lo(PLL_STAT);
- R0 = W[P0](Z);
- CC = BITTST(R0,5);
- if ! CC jump check_again;
-
- /* Configure SCLK & CCLK Dividers */
- r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
- p0.h = hi(PLL_DIV);
- p0.l = lo(PLL_DIV);
- w[p0] = r0.l;
- ssync;
-
- /*
- * We now are running at speed, time to set the Async mem bank wait states
- * This will speed up execution, since we are normally running from FLASH.
- */
-
- p2.h = (EBIU_AMBCTL1 >> 16);
- p2.l = (EBIU_AMBCTL1 & 0xFFFF);
- r0.h = (AMBCTL1VAL >> 16);
- r0.l = (AMBCTL1VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMBCTL0 >> 16);
- p2.l = (EBIU_AMBCTL0 & 0xFFFF);
- r0.h = (AMBCTL0VAL >> 16);
- r0.l = (AMBCTL0VAL & 0xFFFF);
- [p2] = r0;
- ssync;
-
- p2.h = (EBIU_AMGCTL >> 16);
- p2.l = (EBIU_AMGCTL & 0xffff);
- r0 = AMGCTLVAL;
- w[p2] = r0;
- ssync;
-
- /*
- * Now, Initialize the SDRAM,
- * start with the SDRAM Refresh Rate Control Register
- */
- p0.l = lo(EBIU_SDRRC);
- p0.h = hi(EBIU_SDRRC);
- r0 = mem_SDRRC;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Memory Bank Control Register - bank specific parameters
- */
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16);
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
- /*
- * SDRAM Global Control Register - global programmable parameters
- * Disable self-refresh
- */
- P2.H = hi(EBIU_SDGCTL);
- P2.L = lo(EBIU_SDGCTL);
- R0 = [P2];
- BITCLR (R0, 24);
-
- /*
- * Check if SDRAM is already powered up, if it is, enable self-refresh
- */
- p0.h = hi(EBIU_SDSTAT);
- p0.l = lo(EBIU_SDSTAT);
- r2.l = w[p0];
- cc = bittst(r2,3);
- if !cc jump skip;
- NOP;
- BITSET (R0, 23);
-skip:
- [P2] = R0;
- SSYNC;
-
- /* Write in the new value in the register */
- R0.L = lo(mem_SDGCTL);
- R0.H = hi(mem_SDGCTL);
- [P2] = R0;
- SSYNC;
- nop;
-
-
- (P5:0) = [SP++];
- (R7:0) = [SP++];
- RETS = [SP++];
- ASTAT = [SP++];
- RTS;
diff --git a/cpu/bf561/interrupt.S b/cpu/bf561/interrupt.S
deleted file mode 100644
index a10eaab..0000000
--- a/cpu/bf561/interrupt.S
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * U-boot - interrupt.S Processing of interrupts and exception handling
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file is based on interrupt.S
- *
- * Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com>
- * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- *
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * This file is also based on exception.asm
- * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#define ASSEMBLY
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/entry.h>
-
-.global _blackfin_irq_panic;
-
-.text
-.align 2
-
-#ifndef CONFIG_KGDB
-.global _evt_emulation
-_evt_emulation:
- SAVE_CONTEXT
- r0 = 0;
- r1 = seqstat;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
- rte;
-#endif
-
-.global _evt_nmi
-_evt_nmi:
- SAVE_CONTEXT
- r0 = 2;
- r1 = RETN;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
-
-_evt_nmi_exit:
- rtn;
-
-.global _trap
-_trap:
- SAVE_ALL_SYS
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- sp += -12;
- call _trap_c
- sp += 12;
- RESTORE_ALL_SYS
- rtx;
-
-.global _evt_rst
-_evt_rst:
- SAVE_CONTEXT
- r0 = 1;
- r1 = RETN;
- sp += -12;
- call _do_reset;
- sp += 12;
-
-_evt_rst_exit:
- rtn;
-
-irq_panic:
- r0 = 3;
- r1 = sp;
- sp += -12;
- call _blackfin_irq_panic;
- sp += 12;
-
-.global _evt_ivhw
-_evt_ivhw:
- SAVE_CONTEXT
- RAISE 14;
-
-_evt_ivhw_exit:
- rti;
-
-.global _evt_timer
-_evt_timer:
- SAVE_CONTEXT
- r0 = 6;
- sp += -12;
- /* Polling method used now. */
- /* call timer_int; */
- sp += 12;
- RESTORE_CONTEXT
- rti;
- nop;
-
-.global _evt_evt7
-_evt_evt7:
- SAVE_CONTEXT
- r0 = 7;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt7_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt8
-_evt_evt8:
- SAVE_CONTEXT
- r0 = 8;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt8_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt9
-_evt_evt9:
- SAVE_CONTEXT
- r0 = 9;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt9_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt10
-_evt_evt10:
- SAVE_CONTEXT
- r0 = 10;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt10_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt11
-_evt_evt11:
- SAVE_CONTEXT
- r0 = 11;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt11_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt12
-_evt_evt12:
- SAVE_CONTEXT
- r0 = 12;
- sp += -12;
- call _process_int;
- sp += 12;
-evt_evt12_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_evt13
-_evt_evt13:
- SAVE_CONTEXT
- r0 = 13;
- sp += -12;
- call _process_int;
- sp += 12;
-
-evt_evt13_exit:
- RESTORE_CONTEXT
- rti;
-
-.global _evt_system_call
-_evt_system_call:
- [--sp] = r0;
- [--SP] = RETI;
- r0 = [sp++];
- r0 += 2;
- [--sp] = r0;
- RETI = [SP++];
- r0 = [SP++];
- SAVE_CONTEXT
- sp += -12;
- call _exception_handle;
- sp += 12;
- RESTORE_CONTEXT
- RTI;
-
-evt_system_call_exit:
- rti;
-
-.global _evt_soft_int1
-_evt_soft_int1:
- [--sp] = r0;
- [--SP] = RETI;
- r0 = [sp++];
- r0 += 2;
- [--sp] = r0;
- RETI = [SP++];
- r0 = [SP++];
- SAVE_CONTEXT
- sp += -12;
- call _exception_handle;
- sp += 12;
- RESTORE_CONTEXT
- RTI;
-
-evt_soft_int1_exit:
- rti;
diff --git a/cpu/bf561/ints.c b/cpu/bf561/ints.c
deleted file mode 100644
index d6aa393..0000000
--- a/cpu/bf561/ints.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * U-boot - ints.c Interrupt related routines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on ints.c
- *
- * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
- * drivers
- *
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <linux/stddef.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-void blackfin_irq_panic(int reason, struct pt_regs *regs)
-{
- printf("\n\nException: IRQ 0x%x entered\n", reason);
- printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
- printf("stack frame=0x%x, ", (unsigned int)regs);
- printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
- dump(regs);
- printf("Unhandled IRQ or exceptions!\n");
- printf("Please reset the board \n");
-}
-
-void blackfin_init_IRQ(void)
-{
- *(unsigned volatile long *)(SICA_IMASK0) = 0;
-#ifndef CONFIG_KGDB
- *(unsigned volatile long *)(EVT1) = 0x0;
-#endif
- *(unsigned volatile long *)(EVT2) =
- (unsigned volatile long)evt_nmi;
- *(unsigned volatile long *)(EVT3) =
- (unsigned volatile long)trap;
- *(unsigned volatile long *)(EVT5) =
- (unsigned volatile long)evt_ivhw;
- *(unsigned volatile long *)(EVT0) =
- (unsigned volatile long)evt_rst;
- *(unsigned volatile long *)(EVT6) =
- (unsigned volatile long)evt_timer;
- *(unsigned volatile long *)(EVT7) =
- (unsigned volatile long)evt_evt7;
- *(unsigned volatile long *)(EVT8) =
- (unsigned volatile long)evt_evt8;
- *(unsigned volatile long *)(EVT9) =
- (unsigned volatile long)evt_evt9;
- *(unsigned volatile long *)(EVT10) =
- (unsigned volatile long)evt_evt10;
- *(unsigned volatile long *)(EVT11) =
- (unsigned volatile long)evt_evt11;
- *(unsigned volatile long *)(EVT12) =
- (unsigned volatile long)evt_evt12;
- *(unsigned volatile long *)(EVT13) =
- (unsigned volatile long)evt_evt13;
- *(unsigned volatile long *)(EVT14) =
- (unsigned volatile long)evt_system_call;
- *(unsigned volatile long *)(EVT15) =
- (unsigned volatile long)evt_soft_int1;
- *(volatile unsigned long *)ILAT = 0;
- asm("csync;");
- *(volatile unsigned long *)IMASK = 0xffbf;
- asm("csync;");
-}
-
-void exception_handle(void)
-{
-#if defined (CONFIG_PANIC_HANG)
- display_excp();
-#else
- udelay(100000); /* allow messages to go out */
- do_reset(NULL, 0, 0, NULL);
-#endif
-}
-
-void display_excp(void)
-{
- printf("Exception!\n");
-}
diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c
deleted file mode 100644
index a398fd5..0000000
--- a/cpu/bf561/serial.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * U-boot - serial.c Serial driver for BF561
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART.
- * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on blkfinserial.c
- * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
- * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
- * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
- * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328 version serial driver imlpementation which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/bitops.h>
-#include <asm/delay.h>
-#include "serial.h"
-#include <asm/io.h>
-#include <asm/mach-common/bits/uart.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long pll_div_fact;
-
-void calc_baud(void)
-{
- unsigned char i;
- int temp;
- u_long sclk = get_sclk();
-
- for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
- temp = sclk / (baud_table[i] * 8);
- if ((temp & 0x1) == 1) {
- temp++;
- }
- temp = temp / 2;
- hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
- hw_baud_table[i].dl_low = (temp) & 0xFF;
- }
-}
-
-void serial_setbrg(void)
-{
- int i;
-
- calc_baud();
-
- for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
- if (gd->baudrate == baud_table[i])
- break;
- }
-
- /* Enable UART */
- *pUART_GCTL |= UCEN;
- SSYNC();
-
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH;
- SSYNC();
-
- *pUART_DLL = hw_baud_table[i].dl_low;
- SSYNC();
- *pUART_DLH = hw_baud_table[i].dl_high;
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER;
- SSYNC();
-
- /*
- * Enable ERBFI and ELSI interrupts
- * to poll SIC_ISR register
- */
- *pUART_IER = ELSI | ERBFI | ETBEI;
- SSYNC();
-
- /* Set LCR to Word Lengh 8-bit word select */
- *pUART_LCR = WLS_8;
- SSYNC();
-
- return;
-}
-
-int serial_init(void)
-{
- serial_setbrg();
- return (0);
-}
-
-void serial_putc(const char c)
-{
- if ((*pUART_LSR) & TEMT) {
- if (c == '\n')
- serial_putc('\r');
-
- local_put_char(c);
- }
-
- while (!((*pUART_LSR) & TEMT))
- SYNC_ALL;
-
- return;
-}
-
-int serial_tstc(void)
-{
- if (*pUART_LSR & DR)
- return 1;
- else
- return 0;
-}
-
-int serial_getc(void)
-{
- unsigned short uart_lsr_val, uart_rbr_val;
- unsigned long isr_val;
- int ret;
-
- /* Poll for RX Interrupt */
- while (!serial_tstc())
- continue;
- asm("csync;");
-
- uart_lsr_val = *pUART_LSR; /* Clear status bit */
- uart_rbr_val = *pUART_RBR; /* getc() */
-
- if (uart_lsr_val & (OE|PE|FE|BI)) {
- ret = -1;
- } else {
- ret = uart_rbr_val & 0xff;
- }
-
- return ret;
-}
-
-void serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
-static void local_put_char(char ch)
-{
- int flags = 0;
- unsigned long isr_val;
-
- /* Poll for TX Interruput */
- while (!(*pUART_LSR & THRE))
- continue;
- asm("csync;");
-
- *pUART_THR = ch; /* putc() */
-
- return;
-}
diff --git a/cpu/bf561/serial.h b/cpu/bf561/serial.h
deleted file mode 100644
index 647560c..0000000
--- a/cpu/bf561/serial.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * U-boot - bf561_serial.h Serial Driver defines
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
- * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl>
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on:
- * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
- *
- * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com
- * Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328serial.c which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _Bf561_SERIAL_H
-#define _Bf561_SERIAL_H
-
-#include <linux/config.h>
-#include <asm/blackfin.h>
-
-#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
-#define ACCESS_LATCH *pUART_LCR |= DLAB;
-#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB);
-
-void serial_setbrg(void);
-static void local_put_char(char ch);
-void calc_baud(void);
-void serial_setbrg(void);
-int serial_init(void);
-void serial_putc(const char c);
-int serial_tstc(void);
-int serial_getc(void);
-void serial_puts(const char *s);
-static void local_put_char(char ch);
-
-int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
-
-struct {
- unsigned char dl_high;
- unsigned char dl_low;
-} hw_baud_table[5];
-
-#ifdef CONFIG_STAMP
-extern unsigned long pll_div_fact;
-#endif
-
-#endif
diff --git a/cpu/bf561/start.S b/cpu/bf561/start.S
deleted file mode 100644
index 6565de8..0000000
--- a/cpu/bf561/start.S
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * U-boot - start.S Startup file of u-boot for BF533/BF561
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on head.S
- * Copyright (c) 2003 Metrowerks/Motorola
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * Note: A change in this file subsequently requires a change in
- * board/$(board_name)/config.mk for a valid u-boot.bin
- */
-
-#define ASSEMBLY
-
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/dma.h>
-#include <asm/mach-common/bits/pll.h>
-
-.global _stext;
-.global __bss_start;
-.global start;
-.global _start;
-.global edata;
-.global _exit;
-.global init_sdram;
-
-.text
-_start:
-start:
-_stext:
-
- R0 = 0x32;
- SYSCFG = R0;
- SSYNC;
-
- /*
- * As per HW reference manual DAG registers,
- * DATA and Address resgister shall be zero'd
- * in initialization, after a reset state
- */
- r1 = 0; /* Data registers zero'd */
- r2 = 0;
- r3 = 0;
- r4 = 0;
- r5 = 0;
- r6 = 0;
- r7 = 0;
-
- p0 = 0; /* Address registers zero'd */
- p1 = 0;
- p2 = 0;
- p3 = 0;
- p4 = 0;
- p5 = 0;
-
- i0 = 0; /* DAG Registers zero'd */
- i1 = 0;
- i2 = 0;
- i3 = 0;
- m0 = 0;
- m1 = 0;
- m3 = 0;
- m3 = 0;
- l0 = 0;
- l1 = 0;
- l2 = 0;
- l3 = 0;
- b0 = 0;
- b1 = 0;
- b2 = 0;
- b3 = 0;
-
- /*
- * Set loop counters to zero, to make sure that
- * hw loops are disabled.
- */
- r0 = 0;
- lc0 = r0;
- lc1 = r0;
-
- SSYNC;
-
- /* Check soft reset status */
- p0.h = SWRST >> 16;
- p0.l = SWRST & 0xFFFF;
- r0.l = w[p0];
-
- cc = bittst(r0, 15);
- if !cc jump no_soft_reset;
-
- /* Clear Soft reset */
- r0 = 0x0000;
- w[p0] = r0;
- ssync;
-
-no_soft_reset:
- nop;
-
- /* Clear EVT registers */
- p0.h = (EVT0 >> 16);
- p0.l = (EVT0 & 0xFFFF);
- p0 += 8;
- p1 = 14;
- r1 = 0;
- LSETUP(4,4) lc0 = p1;
- [ p0 ++ ] = r1;
-
- p0.h = hi(SICA_IWR0);
- p0.l = lo(SICA_IWR0);
- r0.l = 0x1;
- w[p0] = r0.l;
- SSYNC;
-
- sp.l = (0xffb01000 & 0xFFFF);
- sp.h = (0xffb01000 >> 16);
-
- /*
- * Check if the code is in SDRAM
- * If the code is in SDRAM, skip SDRAM initializaiton
- */
- call get_pc;
- r3.l = 0x0;
- r3.h = 0x2000;
- cc = r0 < r3 (iu);
- if cc jump sdram_initialized;
- call init_sdram;
- /* relocate into to RAM */
-sdram_initialized:
- call get_pc;
-offset:
- r2.l = offset;
- r2.h = offset;
- r3.l = start;
- r3.h = start;
- r1 = r2 - r3;
-
- r0 = r0 - r1;
- p1 = r0;
-
- p2.l = (CFG_MONITOR_BASE & 0xffff);
- p2.h = (CFG_MONITOR_BASE >> 16);
-
- p3 = 0x04;
- p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
- p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
-loop1:
- r1 = [p1 ++ p3];
- [p2 ++ p3] = r1;
- cc=p2==p4;
- if !cc jump loop1;
- /*
- * configure STACK
- */
- r0.h = (CONFIG_STACKBASE >> 16);
- r0.l = (CONFIG_STACKBASE & 0xFFFF);
- sp = r0;
- fp = sp;
-
- /*
- * This next section keeps the processor in supervisor mode
- * during kernel boot. Switches to user mode at end of boot.
- * See page 3-9 of Hardware Reference manual for documentation.
- */
-
- /* To keep ourselves in the supervisor mode */
- p0.l = (EVT15 & 0xFFFF);
- p0.h = (EVT15 >> 16);
-
- p1.l = _real_start;
- p1.h = _real_start;
- [p0] = p1;
-
- p0.l = (IMASK & 0xFFFF);
- p0.h = (IMASK >> 16);
- r0.l = LO(EVT_IVG15);
- r0.h = HI(EVT_IVG15);
- [p0] = r0;
- raise 15;
- p0.l = WAIT_HERE;
- p0.h = WAIT_HERE;
- reti = p0;
- rti;
-
-WAIT_HERE:
- jump WAIT_HERE;
-
-.global _real_start;
-_real_start:
- [ -- sp ] = reti;
-
- /* DMA reset code to Hi of L1 SRAM */
-copy:
- P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
- P1.L = lo(SYSMMR_BASE);
-
- R0.H = reset_start; /* Source Address (high) */
- R0.L = reset_start; /* Source Address (low) */
- R1.H = reset_end;
- R1.L = reset_end;
- R2 = R1 - R0; /* Count */
- R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
- R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
- R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
- R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
-
-DMA:
- R6 = 0x1 (Z);
- W[P1+OFFSET_(IMDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
- W[P1+OFFSET_(IMDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
-
- [P1+OFFSET_(IMDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
- W[P1+OFFSET_(IMDMA_S0_X_COUNT)] = R2; /* Set Source Count */
- /* Set Source DMAConfig = DMA Enable,
- Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
- W[P1+OFFSET_(IMDMA_S0_CONFIG)] = R3;
-
- [P1+OFFSET_(IMDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
- W[P1+OFFSET_(IMDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
- /* Set Destination DMAConfig = DMA Enable,
- Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
- W[P1+OFFSET_(IMDMA_D0_CONFIG)] = R4;
-
-WAIT_DMA_DONE:
- p0.h = hi(IMDMA_D0_IRQ_STATUS);
- p0.l = lo(IMDMA_D0_IRQ_STATUS);
- R0 = W[P0](Z);
- CC = BITTST(R0, 0);
- if ! CC jump WAIT_DMA_DONE
-
- R0 = 0x1;
- W[P1+OFFSET_(IMDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
-
- /* Initialize BSS Section with 0 s */
- p1.l = __bss_start;
- p1.h = __bss_start;
- p2.l = _end;
- p2.h = _end;
- r1 = p1;
- r2 = p2;
- r3 = r2 - r1;
- r3 = r3 >> 2;
- p3 = r3;
- lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
- CC = p2<=p1;
- if CC jump _clear_bss_skip;
- r0 = 0;
-_clear_bss:
-_clear_bss_end:
- [p1++] = r0;
-_clear_bss_skip:
-
- p0.l = _start1;
- p0.h = _start1;
- jump (p0);
-
-reset_start:
- p0.h = WDOG_CNT >> 16;
- p0.l = WDOG_CNT & 0xffff;
- r0 = 0x0010;
- w[p0] = r0;
- p0.h = WDOG_CTL >> 16;
- p0.l = WDOG_CTL & 0xffff;
- r0 = 0x0000;
- w[p0] = r0;
-reset_wait:
- jump reset_wait;
-
-reset_end: nop;
-
-_exit:
- jump.s _exit;
-get_pc:
- r0 = rets;
- rts;
diff --git a/cpu/bf561/traps.c b/cpu/bf561/traps.c
deleted file mode 100644
index e35620c..0000000
--- a/cpu/bf561/traps.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * U-boot - traps.c Routines related to interrupts and exceptions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * No original Copyright holder listed,
- * Probabily original (C) Roman Zippel (assigned DJD, 1999)
- *
- * Copyright 2003 Metrowerks - for Blackfin
- * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
- * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <asm/errno.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include "cpu.h"
-#include <asm/cplb.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
-
-void init_IRQ(void)
-{
- blackfin_init_IRQ();
- return;
-}
-
-void process_int(unsigned long vec, struct pt_regs *fp)
-{
- printf("interrupt\n");
- return;
-}
-
-extern unsigned int icplb_table[page_descriptor_table_size][2];
-extern unsigned int dcplb_table[page_descriptor_table_size][2];
-
-unsigned long last_cplb_fault_retx;
-
-static unsigned int cplb_sizes[4] =
- { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
-
-void trap_c(struct pt_regs *regs)
-{
- unsigned int addr;
- unsigned long trapnr = (regs->seqstat) & EXCAUSE;
- unsigned int i, j, size, *I0, *I1;
- unsigned short data = 0;
-
- switch (trapnr) {
- /* 0x26 - Data CPLB Miss */
- case VEC_CPLB_M:
-
-#if ANOMALY_05000261
- /*
- * Work around an anomaly: if we see a new DCPLB fault, return
- * without doing anything. Then, if we get the same fault again,
- * handle it.
- */
- addr = last_cplb_fault_retx;
- last_cplb_fault_retx = regs->retx;
- printf("this time, curr = 0x%08x last = 0x%08x\n", addr,
- last_cplb_fault_retx);
- if (addr != last_cplb_fault_retx)
- goto trap_c_return;
-#endif
- data = 1;
-
- case VEC_CPLB_I_M:
-
- if (data)
- addr = *pDCPLB_FAULT_ADDR;
- else
- addr = *pICPLB_FAULT_ADDR;
-
- for (i = 0; i < page_descriptor_table_size; i++) {
- if (data) {
- size = cplb_sizes[dcplb_table[i][1] >> 16];
- j = dcplb_table[i][0];
- } else {
- size = cplb_sizes[icplb_table[i][1] >> 16];
- j = icplb_table[i][0];
- }
- if ((j <= addr) && ((j + size) > addr)) {
- debug("found %i 0x%08x\n", i, j);
- break;
- }
- }
- if (i == page_descriptor_table_size) {
- printf("something is really wrong\n");
- do_reset(NULL, 0, 0, NULL);
- }
-
- /* Turn the cache off */
- if (data) {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL &=
- ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
- } else {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
- SSYNC();
- }
-
- if (data) {
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
- } else {
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
- }
-
- j = 0;
- while (*I1 & CPLB_LOCK) {
- debug("skipping %i %08p - %08x\n", j, I1, *I1);
- *I0++;
- *I1++;
- j++;
- }
-
- debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
-
- for (; j < 15; j++) {
- debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
- *I0++ = *(I0 + 1);
- *I1++ = *(I1 + 1);
- }
-
- if (data) {
- *I0 = dcplb_table[i][0];
- *I1 = dcplb_table[i][1];
- I0 = (unsigned int *)DCPLB_ADDR0;
- I1 = (unsigned int *)DCPLB_DATA0;
- } else {
- *I0 = icplb_table[i][0];
- *I1 = icplb_table[i][1];
- I0 = (unsigned int *)ICPLB_ADDR0;
- I1 = (unsigned int *)ICPLB_DATA0;
- }
-
- for (j = 0; j < 16; j++) {
- debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
- }
-
- /* Turn the cache back on */
- if (data) {
- j = *(unsigned int *)DMEM_CONTROL;
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)DMEM_CONTROL =
- ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
- SSYNC();
- } else {
- SSYNC();
- asm(" .align 8; ");
- *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
- SSYNC();
- }
-
- break;
- default:
- /* All traps come here */
- printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
- printf("stack frame=0x%x, ", (unsigned int)regs);
- printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
- dump(regs);
- printf("\n\n");
-
- printf("Unhandled IRQ or exceptions!\n");
- printf("Please reset the board \n");
- do_reset(NULL, 0, 0, NULL);
- }
-
-trap_c_return:
- return;
-
-}
-
-void dump(struct pt_regs *fp)
-{
- debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n", fp->rete,
- fp->retn, fp->retx, fp->rets);
- debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
- debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
- debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n", fp->r0,
- fp->r1, fp->r2, fp->r3);
- debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", fp->r4,
- fp->r5, fp->r6, fp->r7);
- debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n", fp->p0,
- fp->p1, fp->p2, fp->p3);
- debug("P4: %08lx P5: %08lx FP: %08lx\n", fp->p4, fp->p5, fp->fp);
- debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
- fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
- debug("LB0: %08lx LT0: %08lx LC0: %08lx\n", fp->lb0, fp->lt0,
- fp->lc0);
- debug("LB1: %08lx LT1: %08lx LC1: %08lx\n", fp->lb1, fp->lt1,
- fp->lc1);
- debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n", fp->b0, fp->l0,
- fp->m0, fp->i0);
- debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n", fp->b1, fp->l1,
- fp->m1, fp->i1);
- debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n", fp->b2, fp->l2,
- fp->m2, fp->i2);
- debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n", fp->b3, fp->l3,
- fp->m3, fp->i3);
-
- debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
- debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
-
-}
diff --git a/cpu/bf561/video.c b/cpu/bf561/video.c
deleted file mode 100644
index 3ff0151..0000000
--- a/cpu/bf561/video.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
- * (C) Copyright 2002
- * Wolfgang Denk, wd@denx.de
- * (C) Copyright 2006
- * Aubrey Li, aubrey.li@analog.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <devices.h>
-
-#ifdef CONFIG_VIDEO
-#define NTSC_FRAME_ADDR 0x06000000
-#include "video.h"
-
-/* NTSC OUTPUT SIZE 720 * 240 */
-#define VERTICAL 2
-#define HORIZONTAL 4
-
-int is_vblank_line(const int line)
-{
- /*
- * This array contains a single bit for each line in
- * an NTSC frame.
- */
- if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
- return true;
-
- return false;
-}
-
-int NTSC_framebuffer_init(char *base_address)
-{
- const int NTSC_frames = 1;
- const int NTSC_lines = 525;
- char *dest = base_address;
- int frame_num, line_num;
-
- for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
- for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
- unsigned int code;
- int offset = 0;
- int i;
-
- if (is_vblank_line(line_num))
- offset++;
-
- if (line_num > 266 || line_num < 3)
- offset += 2;
-
- /* Output EAV code */
- code = SystemCodeMap[offset].EAV;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output horizontal blanking */
- for (i = 0; i < 67 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
-
- /* Output SAV */
- code = SystemCodeMap[offset].SAV;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output empty horizontal data */
- for (i = 0; i < 360 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
- }
- }
-
- return dest - base_address;
-}
-
-void fill_frame(char *Frame, int Value)
-{
- int *OddPtr32;
- int OddLine;
- int *EvenPtr32;
- int EvenLine;
- int i;
- int *data;
- int m, n;
-
- /* fill odd and even frames */
- for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
- OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
- EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
- for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
- *OddPtr32 = Value;
- *EvenPtr32 = Value;
- }
- }
-
- for (m = 0; m < VERTICAL; m++) {
- data = (int *)u_boot_logo.data;
- for (OddLine = (22 + m), EvenLine = (285 + m);
- OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
- OddLine += VERTICAL, EvenLine += VERTICAL) {
- OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
- EvenPtr32 =
- (int *)((Frame + ((EvenLine) * 1716)) + 276);
- for (i = 0; i < u_boot_logo.width / 2; i++) {
- /* enlarge one pixel to m x n */
- for (n = 0; n < HORIZONTAL; n++) {
- *OddPtr32++ = *data;
- *EvenPtr32++ = *data;
- }
- data++;
- }
- }
- }
-}
-
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
-static int video_init(void)
-{
- char *NTSCFrame;
- NTSCFrame = (char *)NTSC_FRAME_ADDR;
- NTSC_framebuffer_init(NTSCFrame);
- fill_frame(NTSCFrame, BLUE);
-
- *pPPI_CONTROL = 0x0082;
- *pPPI_FRAME = 0x020D;
-
- *pDMA0_START_ADDR = NTSCFrame;
- *pDMA0_X_COUNT = 0x035A;
- *pDMA0_X_MODIFY = 0x0002;
- *pDMA0_Y_COUNT = 0x020D;
- *pDMA0_Y_MODIFY = 0x0002;
- *pDMA0_CONFIG = 0x1015;
- *pPPI_CONTROL = 0x0083;
- return 0;
-}
-
-int drv_video_init(void)
-{
- int error, devices = 1;
-
- device_t videodev;
-
- video_init(); /* Video initialization */
-
- memset(&videodev, 0, sizeof(videodev));
-
- strcpy(videodev.name, "video");
- videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
- videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */
- videodev.putc = video_putc; /* 'putc' function */
- videodev.puts = video_puts; /* 'puts' function */
-
- error = device_register(&videodev);
-
- return (error == 0) ? devices : error;
-}
-#endif
diff --git a/cpu/bf561/video.h b/cpu/bf561/video.h
deleted file mode 100644
index d237f6a..0000000
--- a/cpu/bf561/video.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#include <video_logo.h>
-#define write_dest_byte(val) {*dest++=val;}
-#define BLACK (0x01800180) /* black pixel pattern */
-#define BLUE (0x296E29F0) /* blue pixel pattern */
-#define RED (0x51F0515A) /* red pixel pattern */
-#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
-#define GREEN (0x91229136) /* green pixel pattern */
-#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
-#define YELLOW (0xD292D210) /* yellow pixel pattern */
-#define WHITE (0xFE80FE80) /* white pixel pattern */
-
-#define true 1
-#define false 0
-
-typedef struct {
- unsigned int SAV;
- unsigned int EAV;
-} SystemCodeType;
-
-const SystemCodeType SystemCodeMap[4] = {
- {0xFF000080, 0xFF00009D},
- {0xFF0000AB, 0xFF0000B6},
- {0xFF0000C7, 0xFF0000DA},
- {0xFF0000EC, 0xFF0000F1}
-};
diff --git a/cpu/blackfin/.gitignore b/cpu/blackfin/.gitignore
new file mode 100644
index 0000000..0ec9d56
--- /dev/null
+++ b/cpu/blackfin/.gitignore
@@ -0,0 +1 @@
+bootrom-asm-offsets.[chs]
diff --git a/cpu/blackfin/Makefile b/cpu/blackfin/Makefile
new file mode 100644
index 0000000..f194a38
--- /dev/null
+++ b/cpu/blackfin/Makefile
@@ -0,0 +1,65 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Licensed under the GPL-2 or later.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).a
+
+EXTRA :=
+CEXTRA := initcode.o
+SEXTRA := start.o
+SOBJS := interrupt.o cache.o flush.o
+COBJS := cpu.o traps.o interrupts.o reset.o serial.o i2c.o watchdog.o
+
+ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
+COBJS += initcode.o
+endif
+
+SRCS := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+EXTRA := $(addprefix $(obj),$(EXTRA))
+CEXTRA := $(addprefix $(obj),$(CEXTRA))
+SEXTRA := $(addprefix $(obj),$(SEXTRA))
+
+all: $(obj).depend $(LIB) $(obj).depend $(EXTRA) $(CEXTRA) $(SEXTRA) check_initcode
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+$(OBJS): $(obj)bootrom-asm-offsets.h
+$(obj)bootrom-asm-offsets.c: bootrom-asm-offsets.c.in bootrom-asm-offsets.awk
+ echo '#include <asm/mach-common/bits/bootrom.h>' | $(CPP) $(CPPFLAGS) - | gawk -f ./bootrom-asm-offsets.awk > $@.tmp
+ mv $@.tmp $@
+$(obj)bootrom-asm-offsets.s: $(obj)bootrom-asm-offsets.c
+ $(CC) $(CFLAGS) -S $^ -o $@.tmp
+ mv $@.tmp $@
+$(obj)bootrom-asm-offsets.h: $(obj)bootrom-asm-offsets.s
+ sed -ne "/^->/{s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; s:->::; p;}" $^ > $@
+
+# make sure our initcode (which goes into LDR) does not
+# have relocs or external references
+READINIT = env LC_ALL=C $(CROSS_COMPILE)readelf -s $<
+check_initcode: $(obj)initcode.o
+ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
+ @if $(READINIT) | grep '\<GLOBAL\>.*\<UND\>' ; then \
+ echo "$< contains external references!" 1>&2 ; \
+ exit 1 ; \
+ fi
+endif
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/blackfin/bootrom-asm-offsets.awk b/cpu/blackfin/bootrom-asm-offsets.awk
new file mode 100755
index 0000000..1d61824
--- /dev/null
+++ b/cpu/blackfin/bootrom-asm-offsets.awk
@@ -0,0 +1,41 @@
+#!/usr/bin/gawk -f
+BEGIN {
+ print "/* DO NOT EDIT: AUTOMATICALLY GENERATED"
+ print " * Input files: bootrom-asm-offsets.awk bootrom-asm-offsets.c.in"
+ print " * DO NOT EDIT: AUTOMATICALLY GENERATED"
+ print " */"
+ print ""
+ system("cat bootrom-asm-offsets.c.in")
+ print "{"
+}
+
+{
+ /* find a structure definition */
+ if ($0 ~ /typedef struct .* {/) {
+ delete members;
+ i = 0;
+
+ /* extract each member of the structure */
+ while (1) {
+ getline
+ if ($1 == "}")
+ break;
+ gsub(/[*;]/, "");
+ members[i++] = $NF;
+ }
+
+ /* grab the structure's name */
+ struct = $NF;
+ sub(/;$/, "", struct);
+
+ /* output the DEFINE() macros */
+ while (i-- > 0)
+ print "\tDEFINE(" struct ", " members[i] ");"
+ print ""
+ }
+}
+
+END {
+ print "\treturn 0;"
+ print "}"
+}
diff --git a/cpu/blackfin/bootrom-asm-offsets.c.in b/cpu/blackfin/bootrom-asm-offsets.c.in
new file mode 100644
index 0000000..3146e46
--- /dev/null
+++ b/cpu/blackfin/bootrom-asm-offsets.c.in
@@ -0,0 +1,12 @@
+/* A little trick taken from the kernel asm-offsets.h where we convert
+ * the C structures automatically into a bunch of defines for use in
+ * the assembly files.
+ */
+
+#include <linux/stddef.h>
+#include <asm/mach-common/bits/bootrom.h>
+
+#define _DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val))
+#define DEFINE(s, m) _DEFINE(offset_##s##_##m, offsetof(s, m))
+
+int main(int argc, char *argv[])
diff --git a/cpu/blackfin/cache.S b/cpu/blackfin/cache.S
new file mode 100644
index 0000000..51bdb30
--- /dev/null
+++ b/cpu/blackfin/cache.S
@@ -0,0 +1,61 @@
+/* cache.S - low level cache handling routines
+ * Copyright (C) 2003-2007 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <asm/linkage.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.text
+.align 2
+ENTRY(_blackfin_icache_flush_range)
+ R2 = -32;
+ R2 = R0 & R2;
+ P0 = R2;
+ P1 = R1;
+ CSYNC;
+1:
+ IFLUSH[P0++];
+ CC = P0 < P1(iu);
+ IF CC JUMP 1b(bp);
+ IFLUSH[P0];
+ SSYNC;
+ RTS;
+ENDPROC(_blackfin_icache_flush_range)
+
+ENTRY(_blackfin_dcache_flush_range)
+ R2 = -32;
+ R2 = R0 & R2;
+ P0 = R2;
+ P1 = R1;
+ CSYNC;
+1:
+ FLUSH[P0++];
+ CC = P0 < P1(iu);
+ IF CC JUMP 1b(bp);
+ FLUSH[P0];
+ SSYNC;
+ RTS;
+ENDPROC(_blackfin_dcache_flush_range)
+
+ENTRY(_blackfin_dcache_invalidate_range)
+ R2 = -32;
+ R2 = R0 & R2;
+ P0 = R2;
+ P1 = R1;
+ CSYNC;
+1:
+ FLUSHINV[P0++];
+ CC = P0 < P1(iu);
+ IF CC JUMP 1b(bp);
+
+ /*
+ * If the data crosses a cache line, then we'll be pointing to
+ * the last cache line, but won't have flushed/invalidated it yet, so do
+ * one more.
+ */
+ FLUSHINV[P0];
+ SSYNC;
+ RTS;
+ENDPROC(_blackfin_dcache_invalidate_range)
diff --git a/cpu/blackfin/cpu.c b/cpu/blackfin/cpu.c
new file mode 100644
index 0000000..53de5ab
--- /dev/null
+++ b/cpu/blackfin/cpu.c
@@ -0,0 +1,141 @@
+/*
+ * U-boot - cpu.c CPU specific functions
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/cplb.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/mpu.h>
+#include <asm/mach-common/bits/trace.h>
+
+#include "cpu.h"
+#include "serial.h"
+
+void icache_enable(void)
+{
+ bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() | (IMC | ENICPLB));
+ SSYNC();
+}
+
+void icache_disable(void)
+{
+ bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() & ~(IMC | ENICPLB));
+ SSYNC();
+}
+
+int icache_status(void)
+{
+ return bfin_read_IMEM_CONTROL() & ENICPLB;
+}
+
+void dcache_enable(void)
+{
+ bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() | (ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
+ SSYNC();
+}
+
+void dcache_disable(void)
+{
+ bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
+ SSYNC();
+}
+
+int dcache_status(void)
+{
+ return bfin_read_DMEM_CONTROL() & ENDCPLB;
+}
+
+__attribute__ ((__noreturn__))
+void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
+{
+ /* Build a NOP slide over the LDR jump block. Whee! */
+ serial_early_puts("NOP Slide\n");
+ char nops[0xC];
+ memset(nops, 0x00, sizeof(nops));
+ extern char _stext_l1;
+ memcpy(&_stext_l1 - sizeof(nops), nops, sizeof(nops));
+
+ if (!loaded_from_ldr) {
+ /* Relocate sections into L1 if the LDR didn't do it -- don't
+ * check length because the linker script does the size
+ * checking at build time.
+ */
+ serial_early_puts("L1 Relocate\n");
+ extern char _stext_l1, _etext_l1, _stext_l1_lma;
+ memcpy(&_stext_l1, &_stext_l1_lma, (&_etext_l1 - &_stext_l1));
+ extern char _sdata_l1, _edata_l1, _sdata_l1_lma;
+ memcpy(&_sdata_l1, &_sdata_l1_lma, (&_edata_l1 - &_sdata_l1));
+ }
+#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+ /* The BF537 bootrom will reset the EBIU_AMGCTL register on us
+ * after it has finished loading the LDR. So configure it again.
+ */
+ else
+ bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+#endif
+
+#ifdef CONFIG_DEBUG_DUMP
+ /* Turn on hardware trace buffer */
+ bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
+#endif
+
+#ifndef CONFIG_PANIC_HANG
+ /* Reset upon a double exception rather than just hanging.
+ * Do not do bfin_read on SWRST as that will reset status bits.
+ */
+ bfin_write_SWRST(DOUBLE_FAULT);
+#endif
+
+ serial_early_puts("Board init flash\n");
+ board_init_f(bootflag);
+}
+
+int exception_init(void)
+{
+ bfin_write_EVT3(trap);
+ return 0;
+}
+
+int irq_init(void)
+{
+#ifdef SIC_IMASK0
+ bfin_write_SIC_IMASK0(0);
+ bfin_write_SIC_IMASK1(0);
+# ifdef SIC_IMASK2
+ bfin_write_SIC_IMASK2(0);
+# endif
+#elif defined(SICA_IMASK0)
+ bfin_write_SICA_IMASK0(0);
+ bfin_write_SICA_IMASK1(0);
+#else
+ bfin_write_SIC_IMASK(0);
+#endif
+ bfin_write_EVT2(evt_default); /* NMI */
+ bfin_write_EVT5(evt_default); /* hardware error */
+ bfin_write_EVT6(evt_default); /* core timer */
+ bfin_write_EVT7(evt_default);
+ bfin_write_EVT8(evt_default);
+ bfin_write_EVT9(evt_default);
+ bfin_write_EVT10(evt_default);
+ bfin_write_EVT11(evt_default);
+ bfin_write_EVT12(evt_default);
+ bfin_write_EVT13(evt_default);
+ bfin_write_EVT14(evt_default);
+ bfin_write_EVT15(evt_default);
+ bfin_write_ILAT(0);
+ CSYNC();
+ /* enable all interrupts except for core timer */
+ irq_flags = 0xffffffbf;
+ local_irq_enable();
+ CSYNC();
+ return 0;
+}
diff --git a/cpu/bf561/start1.S b/cpu/blackfin/cpu.h
index 6d4731b..0a13c28 100644
--- a/cpu/bf561/start1.S
+++ b/cpu/blackfin/cpu.h
@@ -1,7 +1,7 @@
/*
- * U-boot - start1.S Code running out of RAM after relocation
+ * U-boot - cpu.h
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -22,17 +22,17 @@
* MA 02110-1301 USA
*/
-#define ASSEMBLY
-#include <linux/config.h>
-#include <config.h>
-#include <asm/blackfin.h>
+#ifndef _CPU_H_
+#define _CPU_H_
-.global start1;
-.global _start1;
+#include <command.h>
-.text
-_start1:
-start1:
- sp += -12;
- call _board_init_f;
- sp += 12;
+void board_reset(void) __attribute__((__weak__));
+void bfin_reset_or_hang(void) __attribute__((__noreturn__));
+void bfin_panic(struct pt_regs *reg);
+void dump(struct pt_regs *regs);
+
+asmlinkage void trap(void);
+asmlinkage void evt_default(void);
+
+#endif
diff --git a/cpu/blackfin/flush.S b/cpu/blackfin/flush.S
new file mode 100644
index 0000000..8072b86
--- /dev/null
+++ b/cpu/blackfin/flush.S
@@ -0,0 +1,230 @@
+/* flush.S - low level cache flushing routines
+ * Copyright (C) 2003-2007 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/cplb.h>
+#include <asm/mach-common/bits/mpu.h>
+
+.text
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the data cache.
+ */
+
+ENTRY(_flush_data_cache)
+ [--SP] = ( R7:6, P5:4 );
+ LINK 12;
+ SP += -12;
+ P5.H = HI(DCPLB_ADDR0);
+ P5.L = LO(DCPLB_ADDR0);
+ P4.H = HI(DCPLB_DATA0);
+ P4.L = LO(DCPLB_DATA0);
+ R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
+ R6 = 16;
+.Lnext: R0 = [P5++];
+ R1 = [P4++];
+ CC = BITTST(R1, 14); /* Is it write-through?*/
+ IF CC JUMP .Lskip; /* If so, ignore it.*/
+ R2 = R1 & R7; /* Is it a dirty, cached page?*/
+ CC = R2;
+ IF !CC JUMP .Lskip; /* If not, ignore it.*/
+ [--SP] = RETS;
+ CALL _dcplb_flush; /* R0 = page, R1 = data*/
+ RETS = [SP++];
+.Lskip: R6 += -1;
+ CC = R6;
+ IF CC JUMP .Lnext;
+ SSYNC;
+ SP += 12;
+ UNLINK;
+ ( R7:6, P5:4 ) = [SP++];
+ RTS;
+ENDPROC(_flush_data_cache)
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular DCPLB.
+ *
+ * R0 - page's start address
+ * R1 - CPLB's data field.
+ */
+
+.align 2
+ENTRY(_dcplb_flush)
+ [--SP] = ( R7:0, P5:0 );
+ [--SP] = LC0;
+ [--SP] = LT0;
+ [--SP] = LB0;
+ [--SP] = LC1;
+ [--SP] = LT1;
+ [--SP] = LB1;
+
+ /* If it's a 1K or 4K page, then it's quickest to
+ * just systematically flush all the addresses in
+ * the page, regardless of whether they're in the
+ * cache, or dirty. If it's a 1M or 4M page, there
+ * are too many addresses, and we have to search the
+ * cache for lines corresponding to the page.
+ */
+
+ CC = BITTST(R1, 17); /* 1MB or 4MB */
+ IF !CC JUMP .Ldflush_whole_page;
+
+ /* We're only interested in the page's size, so extract
+ * this from the CPLB (bits 17:16), and scale to give an
+ * offset into the page_size and page_prefix tables.
+ */
+
+ R1 <<= 14;
+ R1 >>= 30;
+ R1 <<= 2;
+
+ /* The page could be mapped into Bank A or Bank B, depending
+ * on (a) whether both banks are configured as cache, and
+ * (b) on whether address bit A[x] is set. x is determined
+ * by DCBS in DMEM_CONTROL
+ */
+
+ R2 = 0; /* Default to Bank A (Bank B would be 1)*/
+
+ P0.L = LO(DMEM_CONTROL);
+ P0.H = HI(DMEM_CONTROL);
+
+ R3 = [P0]; /* If Bank B is not enabled as cache*/
+ CC = BITTST(R3, 2); /* then Bank A is our only option.*/
+ IF CC JUMP .Lbank_chosen;
+
+ R4 = 1<<14; /* If DCBS==0, use A[14].*/
+ R5 = R4 << 7; /* If DCBS==1, use A[23];*/
+ CC = BITTST(R3, 4);
+ IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
+ R5 = R0 & R4; /* Use it to test the Page address*/
+ CC = R5; /* and if that bit is set, we use Bank B,*/
+ R2 = CC; /* else we use Bank A.*/
+ R2 <<= 23; /* The Bank selection's at posn 23.*/
+
+.Lbank_chosen:
+
+ /* We can also determine the sub-bank used, because this is
+ * taken from bits 13:12 of the address.
+ */
+
+ R3 = ((12<<8)|2); /* Extraction pattern */
+ nop; /*Anamoly 05000209*/
+ R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
+ /* Save in extraction pattern for later deposit.*/
+ R3.H = R4.L << 0;
+
+ /* So:
+ * R0 = Page start
+ * R1 = Page length (actually, offset into size/prefix tables)
+ * R2 = Bank select mask
+ * R3 = sub-bank deposit values
+ *
+ * The cache has 2 Ways, and 64 sets, so we iterate through
+ * the sets, accessing the tag for each Way, for our Bank and
+ * sub-bank, looking for dirty, valid tags that match our
+ * address prefix.
+ */
+
+ P5.L = LO(DTEST_COMMAND);
+ P5.H = HI(DTEST_COMMAND);
+ P4.L = LO(DTEST_DATA0);
+ P4.H = HI(DTEST_DATA0);
+
+ P0.L = page_prefix_table;
+ P0.H = page_prefix_table;
+ P1 = R1;
+ R5 = 0; /* Set counter*/
+ P0 = P1 + P0;
+ R4 = [P0]; /* This is the address prefix*/
+
+
+ /* We're reading (bit 1==0) the tag (bit 2==0), and we
+ * don't care about which double-word, since we're only
+ * fetching tags, so we only have to set Set, Bank,
+ * Sub-bank and Way.
+ */
+
+ P2 = 2;
+ LSETUP (.Lfs1, .Lfe1) LC1 = P2;
+.Lfs1: P0 = 64; /* iterate over all sets*/
+ LSETUP (.Lfs0, .Lfe0) LC0 = P0;
+.Lfs0: R6 = R5 << 5; /* Combine set*/
+ R6.H = R3.H << 0 ; /* and sub-bank*/
+ R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
+ BITSET(R6,14);
+ [P5] = R6; /* Issue Command*/
+ SSYNC;
+ R7 = [P4]; /* and read Tag.*/
+ CC = BITTST(R7, 0); /* Check if valid*/
+ IF !CC JUMP .Lfskip; /* and skip if not.*/
+ CC = BITTST(R7, 1); /* Check if dirty*/
+ IF !CC JUMP .Lfskip; /* and skip if not.*/
+
+ /* Compare against the page address. First, plant bits 13:12
+ * into the tag, since those aren't part of the returned data.
+ */
+
+ R7 = DEPOSIT(R7, R3); /* set 13:12*/
+ R1 = R7 & R4; /* Mask off lower bits*/
+ CC = R1 == R0; /* Compare against page start.*/
+ IF !CC JUMP .Lfskip; /* Skip it if it doesn't match.*/
+
+ /* Tag address matches against page, so this is an entry
+ * we must flush.
+ */
+
+ R7 >>= 10; /* Mask off the non-address bits*/
+ R7 <<= 10;
+ P3 = R7;
+ SSYNC;
+ FLUSHINV [P3]; /* And flush the entry*/
+.Lfskip:
+.Lfe0: R5 += 1; /* Advance to next Set*/
+.Lfe1: BITSET(R2, 26); /* Go to next Way.*/
+
+.Ldfinished:
+ SSYNC; /* Ensure the data gets out to mem.*/
+
+ /*Finished. Restore context.*/
+ LB1 = [SP++];
+ LT1 = [SP++];
+ LC1 = [SP++];
+ LB0 = [SP++];
+ LT0 = [SP++];
+ LC0 = [SP++];
+ ( R7:0, P5:0 ) = [SP++];
+ RTS;
+
+.Ldflush_whole_page:
+
+ /* It's a 1K or 4K page, so quicker to just flush the
+ * entire page.
+ */
+
+ P1 = 32; /* For 1K pages*/
+ P2 = P1 << 2; /* For 4K pages*/
+ P0 = R0; /* Start of page*/
+ CC = BITTST(R1, 16); /* Whether 1K or 4K*/
+ IF CC P1 = P2;
+ P1 += -1; /* Unroll one iteration*/
+ SSYNC;
+ FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
+ LSETUP (.Leall, .Leall) LC0 = P1;
+.Leall: FLUSHINV [P0++];
+ SSYNC;
+ JUMP .Ldfinished;
+ENDPROC(_dcplb_flush)
+
+.align 4;
+page_prefix_table:
+.byte4 0xFFFFFC00; /* 1K */
+.byte4 0xFFFFF000; /* 4K */
+.byte4 0xFFF00000; /* 1M */
+.byte4 0xFFC00000; /* 4M */
+.page_prefix_table.end:
diff --git a/cpu/bf537/i2c.c b/cpu/blackfin/i2c.c
index ab7dd38..47be258 100644
--- a/cpu/bf537/i2c.c
+++ b/cpu/blackfin/i2c.c
@@ -1,18 +1,10 @@
-/****************************************************************
- * $ID: i2c.c 24 Oct 2006 12:00:00 +0800 $ *
- * *
- * Description: *
- * *
- * Maintainer: sonicz <sonic.zhang@analog.com> *
- * *
- * CopyRight (c) 2006 Analog Device *
- * All rights reserved. *
- * *
- * This file is free software; *
- * you are free to modify and/or redistribute it *
- * under the terms of the GNU General Public Licence (GPL).*
- * *
- ****************************************************************/
+/*
+ * i2c.c - driver for Blackfin on-chip TWI/I2C
+ *
+ * Copyright (c) 2006-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
#include <common.h>
@@ -23,10 +15,45 @@
#include <asm/io.h>
#include <asm/mach-common/bits/twi.h>
-DECLARE_GLOBAL_DATA_PTR;
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
+#ifdef TWI0_CLKDIV
+#define bfin_read_TWI_CLKDIV() bfin_read_TWI0_CLKDIV()
+#define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val)
+#define bfin_read_TWI_CONTROL() bfin_read_TWI0_CONTROL()
+#define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val)
+#define bfin_read_TWI_SLAVE_CTL() bfin_read_TWI0_SLAVE_CTL()
+#define bfin_write_TWI_SLAVE_CTL(val) bfin_write_TWI0_SLAVE_CTL(val)
+#define bfin_read_TWI_SLAVE_STAT() bfin_read_TWI0_SLAVE_STAT()
+#define bfin_write_TWI_SLAVE_STAT(val) bfin_write_TWI0_SLAVE_STAT(val)
+#define bfin_read_TWI_SLAVE_ADDR() bfin_read_TWI0_SLAVE_ADDR()
+#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write_TWI0_SLAVE_ADDR(val)
+#define bfin_read_TWI_MASTER_CTL() bfin_read_TWI0_MASTER_CTL()
+#define bfin_write_TWI_MASTER_CTL(val) bfin_write_TWI0_MASTER_CTL(val)
+#define bfin_read_TWI_MASTER_STAT() bfin_read_TWI0_MASTER_STAT()
+#define bfin_write_TWI_MASTER_STAT(val) bfin_write_TWI0_MASTER_STAT(val)
+#define bfin_read_TWI_MASTER_ADDR() bfin_read_TWI0_MASTER_ADDR()
+#define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val)
+#define bfin_read_TWI_INT_STAT() bfin_read_TWI0_INT_STAT()
+#define bfin_write_TWI_INT_STAT(val) bfin_write_TWI0_INT_STAT(val)
+#define bfin_read_TWI_INT_MASK() bfin_read_TWI0_INT_MASK()
+#define bfin_write_TWI_INT_MASK(val) bfin_write_TWI0_INT_MASK(val)
+#define bfin_read_TWI_FIFO_CTL() bfin_read_TWI0_FIFO_CTL()
+#define bfin_write_TWI_FIFO_CTL(val) bfin_write_TWI0_FIFO_CTL(val)
+#define bfin_read_TWI_FIFO_STAT() bfin_read_TWI0_FIFO_STAT()
+#define bfin_write_TWI_FIFO_STAT(val) bfin_write_TWI0_FIFO_STAT(val)
+#define bfin_read_TWI_XMT_DATA8() bfin_read_TWI0_XMT_DATA8()
+#define bfin_write_TWI_XMT_DATA8(val) bfin_write_TWI0_XMT_DATA8(val)
+#define bfin_read_TWI_XMT_DATA_16() bfin_read_TWI0_XMT_DATA16()
+#define bfin_write_TWI_XMT_DATA16(val) bfin_write_TWI0_XMT_DATA16(val)
+#define bfin_read_TWI_RCV_DATA8() bfin_read_TWI0_RCV_DATA8()
+#define bfin_write_TWI_RCV_DATA8(val) bfin_write_TWI0_RCV_DATA8(val)
+#define bfin_read_TWI_RCV_DATA16() bfin_read_TWI0_RCV_DATA16()
+#define bfin_write_TWI_RCV_DATA16(val) bfin_write_TWI0_RCV_DATA16(val)
+#endif
#ifdef DEBUG_I2C
#define PRINTD(fmt,args...) do { \
+ DECLARE_GLOBAL_DATA_PTR; \
if (gd->have_console) \
printf(fmt ,##args); \
} while (0)
@@ -50,14 +77,12 @@ struct i2c_msg {
/**
* i2c_reset: - reset the host controller
- *
*/
-
static void i2c_reset(void)
{
/* Disable TWI */
bfin_write_TWI_CONTROL(0);
- sync();
+ SSYNC();
/* Set TWI internal clock as 10MHz */
bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
@@ -74,7 +99,7 @@ static void i2c_reset(void)
/* Enable TWI */
bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
- sync();
+ SSYNC();
}
int wait_for_completion(struct i2c_msg *msg, int timeout_count)
@@ -95,10 +120,10 @@ int wait_for_completion(struct i2c_msg *msg, int timeout_count)
} else if (msg->flags & I2C_M_STOP)
bfin_write_TWI_MASTER_CTL
(bfin_read_TWI_MASTER_CTL() | STOP);
- sync();
+ SSYNC();
/* Clear status */
bfin_write_TWI_INT_STAT(XMTSERV);
- sync();
+ SSYNC();
i = 0;
}
if (RCVSERV & twi_int_stat) {
@@ -109,11 +134,11 @@ int wait_for_completion(struct i2c_msg *msg, int timeout_count)
} else if (msg->flags & I2C_M_STOP) {
bfin_write_TWI_MASTER_CTL
(bfin_read_TWI_MASTER_CTL() | STOP);
- sync();
+ SSYNC();
}
/* Clear interrupt source */
bfin_write_TWI_INT_STAT(RCVSERV);
- sync();
+ SSYNC();
i = 0;
}
if (MERR & twi_int_stat) {
@@ -121,7 +146,7 @@ int wait_for_completion(struct i2c_msg *msg, int timeout_count)
bfin_write_TWI_INT_MASK(0);
bfin_write_TWI_MASTER_STAT(0x3e);
bfin_write_TWI_MASTER_CTL(0);
- sync();
+ SSYNC();
/*
* if both err and complete int stats are set,
* return proper results.
@@ -130,7 +155,7 @@ int wait_for_completion(struct i2c_msg *msg, int timeout_count)
bfin_write_TWI_INT_STAT(MCOMP);
bfin_write_TWI_INT_MASK(0);
bfin_write_TWI_MASTER_CTL(0);
- sync();
+ SSYNC();
/*
* If it is a quick transfer,
* only address bug no data, not an err.
@@ -150,10 +175,10 @@ int wait_for_completion(struct i2c_msg *msg, int timeout_count)
}
if (MCOMP & twi_int_stat) {
bfin_write_TWI_INT_STAT(MCOMP);
- sync();
+ SSYNC();
bfin_write_TWI_INT_MASK(0);
bfin_write_TWI_MASTER_CTL(0);
- sync();
+ SSYNC();
return 0;
}
}
@@ -187,7 +212,8 @@ int i2c_transfer(struct i2c_msg *msg)
goto transfer_error;
}
- while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) ;
+ while (bfin_read_TWI_MASTER_STAT() & BUSBUSY)
+ continue;
/* Set Transmit device address */
bfin_write_TWI_MASTER_ADDR(msg->addr);
@@ -197,9 +223,9 @@ int i2c_transfer(struct i2c_msg *msg)
* Data in FIFO should be discarded before start a new operation.
*/
bfin_write_TWI_FIFO_CTL(0x3);
- sync();
+ SSYNC();
bfin_write_TWI_FIFO_CTL(0);
- sync();
+ SSYNC();
if (!(msg->flags & I2C_M_RD)) {
/* Transmit first data */
@@ -208,7 +234,7 @@ int i2c_transfer(struct i2c_msg *msg)
len);
bfin_write_TWI_XMT_DATA8(*(msg->buf++));
msg->len--;
- sync();
+ SSYNC();
}
}
@@ -218,7 +244,7 @@ int i2c_transfer(struct i2c_msg *msg)
/* Interrupt mask . Enable XMT, RCV interrupt */
bfin_write_TWI_INT_MASK(MCOMP | MERR |
((msg->flags & I2C_M_RD) ? RCVSERV : XMTSERV));
- sync();
+ SSYNC();
if (len > 0 && len <= 255)
bfin_write_TWI_MASTER_CTL((len << 6));
@@ -233,12 +259,12 @@ int i2c_transfer(struct i2c_msg *msg)
((msg->flags & I2C_M_RD)
? MDIR : 0) | ((CONFIG_TWICLK_KHZ >
100) ? FAST : 0));
- sync();
+ SSYNC();
ret = wait_for_completion(msg, timeout_count);
PRINTD("3 in i2c_transfer: ret=%d\n", ret);
-transfer_error:
+ transfer_error:
switch (ret) {
case 1:
PRINTD(("i2c_transfer: error: transfer fail\n"));
@@ -415,4 +441,4 @@ void i2c_reg_write(uchar chip, uchar reg, uchar val)
i2c_write(chip, reg, 0, &val, 1);
}
-#endif /* CONFIG_HARD_I2C */
+#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
new file mode 100644
index 0000000..ffc8420
--- /dev/null
+++ b/cpu/blackfin/initcode.c
@@ -0,0 +1,353 @@
+/*
+ * initcode.c - Initialize the processor. This is usually entails things
+ * like external memory, voltage regulators, etc... Note that this file
+ * cannot make any function calls as it may be executed all by itself by
+ * the Blackfin's bootrom in LDR format.
+ *
+ * Copyright (c) 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#include <asm/mach-common/bits/uart.h>
+
+#define BFIN_IN_INITCODE
+#include "serial.h"
+
+__attribute__((always_inline))
+static inline uint32_t serial_init(void)
+{
+#ifdef __ADSPBF54x__
+# ifdef BFIN_BOOT_UART_USE_RTS
+# define BFIN_UART_USE_RTS 1
+# else
+# define BFIN_UART_USE_RTS 0
+# endif
+ if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+ size_t i;
+
+ /* force RTS rather than relying on auto RTS */
+ bfin_write_UART1_MCR(bfin_read_UART1_MCR() | FCPOL);
+
+ /* Wait for the line to clear up. We cannot rely on UART
+ * registers as none of them reflect the status of the RSR.
+ * Instead, we'll sleep for ~10 bit times at 9600 baud.
+ * We can precalc things here by assuming boot values for
+ * PLL rather than loading registers and calculating.
+ * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
+ * EDB0 = 0
+ * Divisor = (SCLK / baud) / 16
+ * SCLK = baud * 16 * Divisor
+ * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
+ * CCLK = (16 * Divisor * 5) * (9600 / 10)
+ * In reality, this will probably be just about 1 second delay,
+ * so assuming 9600 baud is OK (both as a very low and too high
+ * speed as this will buffer things enough).
+ */
+#define _NUMBITS (10) /* how many bits to delay */
+#define _LOWBAUD (9600) /* low baud rate */
+#define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
+#define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
+#define _NUMINS (3) /* how many instructions in loop */
+#define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
+ i = _CCLK;
+ while (i--)
+ asm volatile("" : : : "memory");
+ }
+#endif
+
+ uint32_t old_baud = serial_early_get_baud();
+
+ if (BFIN_DEBUG_EARLY_SERIAL) {
+ serial_early_init();
+
+ /* If the UART is off, that means we need to program
+ * the baud rate ourselves initially.
+ */
+ if (!old_baud) {
+ old_baud = CONFIG_BAUDRATE;
+ serial_early_set_baud(CONFIG_BAUDRATE);
+ }
+ }
+
+ return old_baud;
+}
+
+__attribute__((always_inline))
+static inline void serial_deinit(void)
+{
+#ifdef __ADSPBF54x__
+ if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+ /* clear forced RTS rather than relying on auto RTS */
+ bfin_write_UART1_MCR(bfin_read_UART1_MCR() & ~FCPOL);
+ }
+#endif
+}
+
+/* We need to reset the baud rate when we have early debug turned on
+ * or when we are booting over the UART.
+ * XXX: we should fix this to calc the old baud and restore it rather
+ * than hardcoding it via CONFIG_LDR_LOAD_BAUD ... but we have
+ * to figure out how to avoid the division in the baud calc ...
+ */
+__attribute__((always_inline))
+static inline void serial_reset_baud(uint32_t baud)
+{
+ if (!BFIN_DEBUG_EARLY_SERIAL && CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
+ return;
+
+#ifndef CONFIG_LDR_LOAD_BAUD
+# define CONFIG_LDR_LOAD_BAUD 115200
+#endif
+
+ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+ serial_early_set_baud(baud);
+ else if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+ serial_early_set_baud(CONFIG_LDR_LOAD_BAUD);
+ else
+ serial_early_set_baud(CONFIG_BAUDRATE);
+}
+
+__attribute__((always_inline))
+static inline void serial_putc(char c)
+{
+ if (!BFIN_DEBUG_EARLY_SERIAL)
+ return;
+
+ if (c == '\n')
+ *pUART_THR = '\r';
+
+ *pUART_THR = c;
+
+ while (!(*pUART_LSR & TEMT))
+ continue;
+}
+
+
+/* Max SCLK can be 133MHz ... dividing that by 4 gives
+ * us a freq of 33MHz for SPI which should generally be
+ * slow enough for the slow reads the bootrom uses.
+ */
+#ifndef CONFIG_SPI_BAUD_INITBLOCK
+# define CONFIG_SPI_BAUD_INITBLOCK 4
+#endif
+
+/* PLL_DIV defines */
+#ifndef CONFIG_PLL_DIV_VAL
+# if (CONFIG_CCLK_DIV == 1)
+# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
+# elif (CONFIG_CCLK_DIV == 2)
+# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
+# elif (CONFIG_CCLK_DIV == 4)
+# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
+# elif (CONFIG_CCLK_DIV == 8)
+# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
+# else
+# define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
+# endif
+# define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
+#endif
+
+#ifndef CONFIG_PLL_LOCKCNT_VAL
+# define CONFIG_PLL_LOCKCNT_VAL 0x0300
+#endif
+
+#ifndef CONFIG_PLL_CTL_VAL
+# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9))
+#endif
+
+#ifndef CONFIG_EBIU_RSTCTL_VAL
+# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
+#endif
+
+#ifndef CONFIG_EBIU_MBSCTL_VAL
+# define CONFIG_EBIU_MBSCTL_VAL 0
+#endif
+
+/* Make sure our voltage value is sane so we don't blow up! */
+#ifndef CONFIG_VR_CTL_VAL
+# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
+# if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
+# define CCLK_VLEV_120 400000000
+# define CCLK_VLEV_125 533000000
+# elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+# define CCLK_VLEV_120 401000000
+# define CCLK_VLEV_125 401000000
+# elif defined(__ADSPBF561__)
+# define CCLK_VLEV_120 300000000
+# define CCLK_VLEV_125 501000000
+# endif
+# if BFIN_CCLK < CCLK_VLEV_120
+# define CONFIG_VR_CTL_VLEV VLEV_120
+# elif BFIN_CCLK < CCLK_VLEV_125
+# define CONFIG_VR_CTL_VLEV VLEV_125
+# else
+# define CONFIG_VR_CTL_VLEV VLEV_130
+# endif
+# if defined(__ADSPBF52x__) /* TBD; use default */
+# undef CONFIG_VR_CTL_VLEV
+# define CONFIG_VR_CTL_VLEV VLEV_110
+# elif defined(__ADSPBF54x__) /* TBD; use default */
+# undef CONFIG_VR_CTL_VLEV
+# define CONFIG_VR_CTL_VLEV VLEV_120
+# endif
+
+# ifdef CONFIG_BFIN_MAC
+# define CONFIG_VR_CTL_CLKBUF CLKBUFOE
+# else
+# define CONFIG_VR_CTL_CLKBUF 0
+# endif
+
+# if defined(__ADSPBF52x__)
+# define CONFIG_VR_CTL_FREQ FREQ_1000
+# else
+# define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
+# endif
+
+# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
+#endif
+
+__attribute__((saveall))
+void initcode(ADI_BOOT_DATA *bootstruct)
+{
+ uint32_t old_baud = serial_init();
+
+#ifdef CONFIG_HW_WATCHDOG
+# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
+# define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
+# endif
+ /* Program the watchdog with an initial timeout of ~20 seconds.
+ * Hopefully that should be long enough to load the u-boot LDR
+ * (from wherever) and then the common u-boot code can take over.
+ * In bypass mode, the start.S would have already set a much lower
+ * timeout, so don't clobber that.
+ */
+ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
+ bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
+ bfin_write_WDOG_CTL(0);
+ }
+#endif
+
+ serial_putc('S');
+
+ /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
+ * fast read, so we need to slow down the SPI clock a lot more during
+ * boot. Once we switch over to u-boot's SPI flash driver, we'll
+ * increase the speed appropriately.
+ */
+ if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#ifdef SPI0_BAUD
+ bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
+#else
+ bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
+#endif
+
+ serial_putc('B');
+
+ /* Disable all peripheral wakeups except for the PLL event. */
+#ifdef SIC_IWR0
+ bfin_write_SIC_IWR0(1);
+ bfin_write_SIC_IWR1(0);
+# ifdef SIC_IWR2
+ bfin_write_SIC_IWR2(0);
+# endif
+#elif defined(SICA_IWR0)
+ bfin_write_SICA_IWR0(1);
+ bfin_write_SICA_IWR1(0);
+#else
+ bfin_write_SIC_IWR(1);
+#endif
+
+ serial_putc('L');
+
+ bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
+
+ serial_putc('A');
+
+ /* Only reprogram when needed to avoid triggering unnecessary
+ * PLL relock sequences.
+ */
+ if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
+ serial_putc('!');
+ bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
+ asm("idle;");
+ }
+
+ serial_putc('C');
+
+ bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
+
+ serial_putc('K');
+
+ /* Only reprogram when needed to avoid triggering unnecessary
+ * PLL relock sequences.
+ */
+ if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
+ serial_putc('!');
+ bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
+ asm("idle;");
+ }
+
+ /* Since we've changed the SCLK above, we may need to update
+ * the UART divisors (UART baud rates are based on SCLK).
+ */
+ serial_reset_baud(old_baud);
+
+ serial_putc('F');
+
+ /* Program the async banks controller. */
+ bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
+ bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
+ bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+
+#ifdef EBIU_MODE
+ /* Not all parts have these additional MMRs. */
+ bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
+ bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
+ bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
+#endif
+
+ serial_putc('I');
+
+ /* Program the external memory controller. */
+#ifdef EBIU_RSTCTL
+ bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
+ bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
+ bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
+ bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
+# ifdef CONFIG_EBIU_DDRCTL3_VAL
+ /* default is disable, so don't need to force this */
+ bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
+# endif
+#else
+ bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
+ bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
+ bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
+#endif
+
+ serial_putc('N');
+
+ /* Restore all peripheral wakeups. */
+#ifdef SIC_IWR0
+ bfin_write_SIC_IWR0(-1);
+ bfin_write_SIC_IWR1(-1);
+# ifdef SIC_IWR2
+ bfin_write_SIC_IWR2(-1);
+# endif
+#elif defined(SICA_IWR0)
+ bfin_write_SICA_IWR0(-1);
+ bfin_write_SICA_IWR1(-1);
+#else
+ bfin_write_SIC_IWR(-1);
+#endif
+
+ serial_putc('>');
+ serial_putc('\n');
+
+ serial_deinit();
+}
diff --git a/cpu/blackfin/interrupt.S b/cpu/blackfin/interrupt.S
new file mode 100644
index 0000000..dd2cc53
--- /dev/null
+++ b/cpu/blackfin/interrupt.S
@@ -0,0 +1,33 @@
+/*
+ * interrupt.S - trampoline default exceptions/interrupts to C handlers
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <asm/blackfin.h>
+#include <asm/entry.h>
+
+.text
+
+/* default entry point for exceptions */
+ENTRY(_trap)
+ SAVE_ALL_SYS
+ r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
+ sp += -12;
+ call _trap_c;
+ sp += 12;
+ RESTORE_ALL_SYS
+ rtx;
+ENDPROC(_trap)
+
+/* default entry point for interrupts */
+ENTRY(_evt_default)
+ SAVE_ALL_SYS
+ r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
+ sp += -12;
+ call _bfin_panic;
+ sp += 12;
+ RESTORE_ALL_SYS
+ rti;
+ENDPROC(_evt_default)
diff --git a/cpu/bf561/interrupts.c b/cpu/blackfin/interrupts.c
index 7880061..80c5505 100644
--- a/cpu/bf561/interrupts.c
+++ b/cpu/blackfin/interrupts.c
@@ -1,7 +1,7 @@
/*
* U-boot - interrupts.c Interrupt related routines
*
- * Copyright (c) 2005-2007 Analog Devices Inc.
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* This file is based on interrupts.c
* Copyright 1996 Roman Zippel
@@ -14,24 +14,8 @@
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Licensed under the GPL-2 or later.
*/
#include <common.h>
@@ -49,7 +33,7 @@ int irq_flags; /* needed by asm-blackfin/system.h */
/*
* This function is derived from PowerPC code (read timebase as long long).
- * On BF561 it just returns the timer value.
+ * On Blackfin it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
@@ -58,7 +42,7 @@ unsigned long long get_ticks(void)
/*
* This function is derived from PowerPC code (timebase clock frequency).
- * On BF561 it returns the number of timer ticks per second.
+ * On Blackfin it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
@@ -70,18 +54,15 @@ ulong get_tbclk(void)
void enable_interrupts(void)
{
+ local_irq_restore(int_flag);
}
int disable_interrupts(void)
{
+ local_irq_save(int_flag);
return 1;
}
-int interrupt_init(void)
-{
- return (0);
-}
-
void udelay(unsigned long usec)
{
unsigned long delay, start, stop;
@@ -101,16 +82,17 @@ void udelay(unsigned long usec)
usec -= 1000;
}
- asm volatile (" %0 = CYCLES;":"=r" (start));
+ asm volatile (" %0 = CYCLES;" : "=r" (start));
do {
- asm volatile (" %0 = CYCLES; ":"=r" (stop));
+ asm volatile (" %0 = CYCLES; " : "=r" (stop));
} while (stop - start < delay);
}
return;
}
-void timer_init(void)
+#define MAX_TIM_LOAD 0xFFFFFFFF
+int timer_init(void)
{
*pTCNTL = 0x1;
*pTSCALE = 0x0;
@@ -121,6 +103,8 @@ void timer_init(void)
timestamp = 0;
last_time = 0;
+
+ return 0;
}
/*
@@ -157,11 +141,15 @@ ulong get_timer(ulong base)
milisec = clocks / (CONFIG_CCLK_HZ / 1000);
/*
- * Find the number of millisonds
- * that got elapsed before this TCOUNT
- * cycle
+ * Find the number of millisonds that
+ * got elapsed before this TCOUNT cycle
*/
milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
return (milisec - base);
}
+
+void reset_timer(void)
+{
+ timestamp = 0;
+}
diff --git a/cpu/blackfin/reset.c b/cpu/blackfin/reset.c
new file mode 100644
index 0000000..d1e34b3
--- /dev/null
+++ b/cpu/blackfin/reset.c
@@ -0,0 +1,96 @@
+/*
+ * reset.c - logic for resetting the cpu
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+/* A system soft reset makes external memory unusable so force
+ * this function into L1. We use the compiler ssync here rather
+ * than SSYNC() because it's safe (no interrupts and such) and
+ * we save some L1. We do not need to force sanity in the SYSCR
+ * register as the BMODE selection bit is cleared by the soft
+ * reset while the Core B bit (on dual core parts) is cleared by
+ * the core reset.
+ */
+__attribute__ ((__l1_text__, __noreturn__))
+void bfin_reset(void)
+{
+ /* Wait for completion of "system" events such as cache line
+ * line fills so that we avoid infinite stalls later on as
+ * much as possible. This code is in L1, so it won't trigger
+ * any such event after this point in time.
+ */
+ __builtin_bfin_ssync();
+
+ while (1) {
+ /* Initiate System software reset. */
+ bfin_write_SWRST(0x7);
+
+ /* Due to the way reset is handled in the hardware, we need
+ * to delay for 7 SCLKS. The only reliable way to do this is
+ * to calculate the CCLK/SCLK ratio and multiply 7. For now,
+ * we'll assume worse case which is a 1:15 ratio.
+ */
+ asm(
+ "LSETUP (1f, 1f) LC0 = %0\n"
+ "1: nop;"
+ :
+ : "a" (15 * 7)
+ : "LC0", "LB0", "LT0"
+ );
+
+ /* Clear System software reset */
+ bfin_write_SWRST(0);
+
+ /* Wait for the SWRST write to complete. Cannot rely on SSYNC
+ * though as the System state is all reset now.
+ */
+ asm(
+ "LSETUP (1f, 1f) LC1 = %0\n"
+ "1: nop;"
+ :
+ : "a" (15 * 1)
+ : "LC1", "LB1", "LT1"
+ );
+
+ /* Issue core reset */
+ asm("raise 1");
+ }
+}
+
+/* We need to trampoline ourselves up into L1 since our linker
+ * does not have relaxtion support and will only generate a
+ * PC relative call with a 25 bit immediate. This is not enough
+ * to get us from the top of SDRAM into L1.
+ */
+__attribute__ ((__noreturn__))
+static inline void bfin_reset_trampoline(void)
+{
+ if (board_reset)
+ board_reset();
+ while (1)
+ asm("jump (%0);" : : "a" (bfin_reset));
+}
+
+__attribute__ ((__noreturn__))
+void bfin_reset_or_hang(void)
+{
+#ifdef CONFIG_PANIC_HANG
+ hang();
+#else
+ bfin_reset_trampoline();
+#endif
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ bfin_reset_trampoline();
+ return 0;
+}
diff --git a/cpu/blackfin/serial.c b/cpu/blackfin/serial.c
new file mode 100644
index 0000000..0dfee51
--- /dev/null
+++ b/cpu/blackfin/serial.c
@@ -0,0 +1,124 @@
+/*
+ * U-boot - serial.c Blackfin Serial Driver
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
+ * BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on:
+ * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
+ * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
+ * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
+ * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328 version serial driver imlpementation which was:
+ * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/uart.h>
+
+#if defined(UART_LSR) && (CONFIG_UART_CONSOLE != 0)
+# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
+#endif
+
+#include "serial.h"
+
+/* Symbol for our assembly to call. */
+void serial_set_baud(uint32_t baud)
+{
+ serial_early_set_baud(baud);
+}
+
+/* Symbol for common u-boot code to call.
+ * Setup the baudrate (brg: baudrate generator).
+ */
+void serial_setbrg(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ serial_set_baud(gd->baudrate);
+}
+
+/* Symbol for our assembly to call. */
+void serial_initialize(void)
+{
+ serial_early_init();
+}
+
+/* Symbol for common u-boot code to call. */
+int serial_init(void)
+{
+ serial_initialize();
+ serial_setbrg();
+ return 0;
+}
+
+void serial_putc(const char c)
+{
+ /* send a \r for compatibility */
+ if (c == '\n')
+ serial_putc('\r');
+
+ WATCHDOG_RESET();
+
+ /* wait for the hardware fifo to clear up */
+ while (!(*pUART_LSR & THRE))
+ continue;
+
+ /* queue the character for transmission */
+ *pUART_THR = c;
+ SSYNC();
+
+ WATCHDOG_RESET();
+
+ /* wait for the byte to be shifted over the line */
+ while (!(*pUART_LSR & TEMT))
+ continue;
+}
+
+int serial_tstc(void)
+{
+ WATCHDOG_RESET();
+ return (*pUART_LSR & DR) ? 1 : 0;
+}
+
+int serial_getc(void)
+{
+ uint16_t uart_lsr_val, uart_rbr_val;
+
+ /* wait for data ! */
+ while (!serial_tstc())
+ continue;
+
+ /* clear the status and grab the new byte */
+ uart_lsr_val = *pUART_LSR;
+ uart_rbr_val = *pUART_RBR;
+
+ if (uart_lsr_val & (OE|PE|FE|BI)) {
+ /* Some parts are read-to-clear while others are
+ * write-to-clear. Just do the write for everyone
+ * since it cant hurt (other than code size).
+ */
+ *pUART_LSR = (OE|PE|FE|BI);
+ return -1;
+ }
+
+ return uart_rbr_val & 0xFF;
+}
+
+void serial_puts(const char *s)
+{
+ while (*s)
+ serial_putc(*s++);
+}
diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h
new file mode 100644
index 0000000..1f0f4b4
--- /dev/null
+++ b/cpu/blackfin/serial.h
@@ -0,0 +1,275 @@
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ * any functions defined here must be always_inline since
+ * initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2007 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL_H__
+#define __BFIN_CPU_SERIAL_H__
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/uart.h>
+
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+# define BFIN_DEBUG_EARLY_SERIAL 1
+#else
+# define BFIN_DEBUG_EARLY_SERIAL 0
+#endif
+
+#define LOB(x) ((x) & 0xFF)
+#define HIB(x) (((x) >> 8) & 0xFF)
+
+#ifndef UART_LSR
+# if (CONFIG_UART_CONSOLE == 3)
+# define pUART_DLH pUART3_DLH
+# define pUART_DLL pUART3_DLL
+# define pUART_GCTL pUART3_GCTL
+# define pUART_IER pUART3_IER
+# define pUART_IERC pUART3_IER_CLEAR
+# define pUART_LCR pUART3_LCR
+# define pUART_LSR pUART3_LSR
+# define pUART_RBR pUART3_RBR
+# define pUART_THR pUART3_THR
+# define UART_THR UART3_THR
+# define UART_LSR UART3_LSR
+# elif (CONFIG_UART_CONSOLE == 2)
+# define pUART_DLH pUART2_DLH
+# define pUART_DLL pUART2_DLL
+# define pUART_GCTL pUART2_GCTL
+# define pUART_IER pUART2_IER
+# define pUART_IERC pUART2_IER_CLEAR
+# define pUART_LCR pUART2_LCR
+# define pUART_LSR pUART2_LSR
+# define pUART_RBR pUART2_RBR
+# define pUART_THR pUART2_THR
+# define UART_THR UART2_THR
+# define UART_LSR UART2_LSR
+# elif (CONFIG_UART_CONSOLE == 1)
+# define pUART_DLH pUART1_DLH
+# define pUART_DLL pUART1_DLL
+# define pUART_GCTL pUART1_GCTL
+# define pUART_IER pUART1_IER
+# define pUART_IERC pUART1_IER_CLEAR
+# define pUART_LCR pUART1_LCR
+# define pUART_LSR pUART1_LSR
+# define pUART_RBR pUART1_RBR
+# define pUART_THR pUART1_THR
+# define UART_THR UART1_THR
+# define UART_LSR UART1_LSR
+# elif (CONFIG_UART_CONSOLE == 0)
+# define pUART_DLH pUART0_DLH
+# define pUART_DLL pUART0_DLL
+# define pUART_GCTL pUART0_GCTL
+# define pUART_IER pUART0_IER
+# define pUART_IERC pUART0_IER_CLEAR
+# define pUART_LCR pUART0_LCR
+# define pUART_LSR pUART0_LSR
+# define pUART_RBR pUART0_RBR
+# define pUART_THR pUART0_THR
+# define UART_THR UART0_THR
+# define UART_LSR UART0_LSR
+# endif
+#endif
+
+#ifndef __ASSEMBLY__
+
+/* We cannot use get_sclk() in initcode as it is defined elsewhere. */
+#ifdef BFIN_IN_INITCODE
+# define get_sclk() (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV)
+#endif
+
+#ifdef __ADSPBF54x__
+# define ACCESS_LATCH()
+# define ACCESS_PORT_IER()
+# define CLEAR_IER() (*pUART_IERC = 0)
+#else
+# define ACCESS_LATCH() (*pUART_LCR |= DLAB)
+# define ACCESS_PORT_IER() (*pUART_LCR &= ~DLAB)
+# define CLEAR_IER() (*pUART_IER = 0)
+#endif
+
+__attribute__((always_inline))
+static inline void serial_do_portmux(void)
+{
+#ifdef __ADSPBF52x__
+# define DO_MUX(port, mux, tx, rx) \
+ bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \
+ bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
+ switch (CONFIG_UART_CONSOLE) {
+ case 0: DO_MUX(G, 2, 7, 8); break; /* Port G; mux 2; PG2 and PG8 */
+ case 1: DO_MUX(F, 5, 14, 15); break; /* Port F; mux 5; PF14 and PF15 */
+ }
+ SSYNC();
+#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+# define DO_MUX(func, tx, rx) \
+ bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~(func)); \
+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() | PF##tx | PF##rx);
+ switch (CONFIG_UART_CONSOLE) {
+ case 0: DO_MUX(PFDE, 0, 1); break;
+ case 1: DO_MUX(PFTE, 2, 3); break;
+ }
+ SSYNC();
+#elif defined(__ADSPBF54x__)
+# define DO_MUX(port, tx, rx) \
+ bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_1 | PORT_x_MUX_##rx##_FUNC_1); \
+ bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
+ switch (CONFIG_UART_CONSOLE) {
+ case 0: DO_MUX(E, 7, 8); break; /* Port E; PE7 and PE8 */
+ case 1: DO_MUX(H, 0, 1); break; /* Port H; PH0 and PH1 */
+ case 2: DO_MUX(B, 4, 5); break; /* Port B; PB4 and PB5 */
+ case 3: DO_MUX(B, 6, 7); break; /* Port B; PB6 and PB7 */
+ }
+ SSYNC();
+#endif
+}
+
+__attribute__((always_inline))
+static inline void serial_early_init(void)
+{
+ /* handle portmux crap on different Blackfins */
+ serial_do_portmux();
+
+ /* Enable UART */
+ *pUART_GCTL = UCEN;
+
+ /* Set LCR to Word Lengh 8-bit word select */
+ *pUART_LCR = WLS_8;
+
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint32_t serial_early_get_baud(void)
+{
+ /* If the UART isnt enabled, then we are booting an LDR
+ * from a non-UART source (so like flash) which means
+ * the baud rate here is meaningless.
+ */
+ if ((*pUART_GCTL & UCEN) != UCEN)
+ return 0;
+
+#if (0) /* See comment for serial_reset_baud() in initcode.c */
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH();
+ SSYNC();
+
+ uint8_t dll = *pUART_DLL;
+ uint8_t dlh = *pUART_DLH;
+ uint16_t divisor = (dlh << 8) | dll;
+ uint32_t baud = get_sclk() / (divisor * 16);
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER();
+ SSYNC();
+
+ return baud;
+#else
+ return CONFIG_BAUDRATE;
+#endif
+}
+
+__attribute__((always_inline))
+static inline void serial_early_set_baud(uint32_t baud)
+{
+ /* Translate from baud into divisor in terms of SCLK.
+ * The +1 is to make sure we over sample just a little
+ * rather than under sample the incoming signals.
+ */
+ uint16_t divisor = (get_sclk() / (baud * 16)) + 1;
+
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH();
+ SSYNC();
+
+ /* Program the divisor to get the baud rate we want */
+ *pUART_DLL = LOB(divisor);
+ *pUART_DLH = HIB(divisor);
+ SSYNC();
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER();
+ SSYNC();
+}
+
+#ifndef BFIN_IN_INITCODE
+__attribute__((always_inline))
+static inline void serial_early_puts(const char *s)
+{
+ if (BFIN_DEBUG_EARLY_SERIAL) {
+ serial_puts("Early: ");
+ serial_puts(s);
+ }
+}
+#endif
+
+#else
+
+.macro serial_early_init
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+ call _serial_initialize;
+#endif
+.endm
+
+.macro serial_early_set_baud
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+ R0.L = LO(CONFIG_BAUDRATE);
+ R0.H = HI(CONFIG_BAUDRATE);
+ call _serial_set_baud;
+#endif
+.endm
+
+/* Recursively expand calls to _serial_putc for every byte
+ * passed to us. Append a newline when we're all done.
+ */
+.macro _serial_early_putc byte:req morebytes:vararg
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+ R0 = \byte;
+ call _serial_putc;
+.ifnb \morebytes
+ _serial_early_putc \morebytes
+.else
+.if (\byte != '\n')
+ _serial_early_putc '\n'
+.endif
+.endif
+#endif
+.endm
+
+/* Wrapper around recurisve _serial_early_putc macro which
+ * simply prepends the string "Early: "
+ */
+.macro serial_early_putc byte:req morebytes:vararg
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+ _serial_early_putc 'E', 'a', 'r', 'l', 'y', ':', ' ', \byte, \morebytes
+#endif
+.endm
+
+/* Since we embed the string right into our .text section, we need
+ * to find its address. We do this by getting our PC and adding 2
+ * bytes (which is the length of the jump instruction). Then we
+ * pass this address to serial_puts().
+ */
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+# define serial_early_puts(str) \
+ call _get_pc; \
+ jump 1f; \
+ .ascii "Early:"; \
+ .ascii __FILE__; \
+ .ascii ": "; \
+ .ascii str; \
+ .asciz "\n"; \
+ .align 4; \
+1: \
+ R0 += 2; \
+ call _serial_puts;
+#else
+# define serial_early_puts(str)
+#endif
+
+#endif
+
+#endif
diff --git a/cpu/blackfin/start.S b/cpu/blackfin/start.S
new file mode 100644
index 0000000..30212e9
--- /dev/null
+++ b/cpu/blackfin/start.S
@@ -0,0 +1,219 @@
+/*
+ * U-boot - start.S Startup file for Blackfin u-boot
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * This file is based on head.S
+ * Copyright (c) 2003 Metrowerks/Motorola
+ * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ * Kenneth Albanowski <kjahds@kjahds.com>,
+ * The Silver Hammer Group, Ltd.
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/dma.h>
+#include <asm/mach-common/bits/pll.h>
+
+#include "serial.h"
+
+/* It may seem odd that we make calls to functions even though we haven't
+ * relocated ourselves yet out of {flash,ram,wherever}. This is OK because
+ * the "call" instruction in the Blackfin architecture is actually PC
+ * relative. So we can call functions all we want and not worry about them
+ * not being relocated yet.
+ */
+
+.text
+ENTRY(_start)
+
+ /* Set our initial stack to L1 scratch space */
+ sp.l = LO(L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE);
+ sp.h = HI(L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE);
+
+#ifdef CONFIG_HW_WATCHDOG
+# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START
+# define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000
+# endif
+ /* Program the watchdog with an initial timeout of ~5 seconds.
+ * That should be long enough to bootstrap ourselves up and
+ * then the common u-boot code can take over.
+ */
+ P0.L = LO(WDOG_CNT);
+ P0.H = HI(WDOG_CNT);
+ R0.L = 0;
+ R0.H = HI(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_START));
+ [P0] = R0;
+ /* fire up the watchdog - R0.L above needs to be 0x0000 */
+ W[P0 + (WDOG_CTL - WDOG_CNT)] = R0;
+#endif
+
+ /* Turn on the serial for debugging the init process */
+ serial_early_init
+ serial_early_set_baud
+
+ serial_early_puts("Init Registers");
+
+ /* Disable nested interrupts and enable CYCLES for udelay() */
+ R0 = CCEN | 0x30;
+ SYSCFG = R0;
+
+ /* Zero out registers required by Blackfin ABI.
+ * http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
+ */
+ r1 = 0 (x);
+ /* Disable circular buffers */
+ l0 = r1;
+ l1 = r1;
+ l2 = r1;
+ l3 = r1;
+ /* Disable hardware loops in case we were started by 'go' */
+ lc0 = r1;
+ lc1 = r1;
+
+ /* Save RETX so we can pass it while booting Linux */
+ r7 = RETX;
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+ /* In bypass mode, we don't have an LDR with an init block
+ * so we need to explicitly call it ourselves. This will
+ * reprogram our clocks and setup our async banks.
+ */
+ /* XXX: we should DMA this into L1, put external memory into
+ * self refresh, and then jump there ...
+ */
+ call _get_pc;
+ r3 = 0x0;
+ r3.h = 0x2000;
+ cc = r0 < r3 (iu);
+ if cc jump .Lproc_initialized;
+
+ serial_early_puts("Program Clocks");
+
+ call _initcode;
+
+ /* Since we reprogrammed SCLK, we need to update the serial divisor */
+ serial_early_set_baud
+
+.Lproc_initialized:
+#endif
+
+ /* Inform upper layers if we had to do the relocation ourselves.
+ * This allows us to detect whether we were loaded by 'go 0x1000'
+ * or by the bootrom from an LDR. "r6" is "loaded_from_ldr".
+ */
+ r6 = 1 (x);
+
+ /* Relocate from wherever are (FLASH/RAM/etc...) to the
+ * hardcoded monitor location in the end of RAM.
+ */
+ serial_early_puts("Relocate");
+ call _get_pc;
+.Loffset:
+ r2.l = .Loffset;
+ r2.h = .Loffset;
+ r3.l = _start;
+ r3.h = _start;
+ r1 = r2 - r3;
+
+ r0 = r0 - r1;
+
+ cc = r0 == r3;
+ if cc jump .Lnorelocate;
+
+ r6 = 0 (x);
+ p1 = r0;
+
+ p2.l = LO(CFG_MONITOR_BASE);
+ p2.h = HI(CFG_MONITOR_BASE);
+
+ p3 = 0x04;
+ p4.l = LO(CFG_MONITOR_BASE + CFG_MONITOR_LEN);
+ p4.h = HI(CFG_MONITOR_BASE + CFG_MONITOR_LEN);
+.Lloop1:
+ r1 = [p1 ++ p3];
+ [p2 ++ p3] = r1;
+ cc=p2==p4;
+ if !cc jump .Lloop1;
+
+ /* Initialize BSS section ... we know that memset() does not
+ * use the BSS, so it is safe to call here. The bootrom LDR
+ * takes care of clearing things for us.
+ */
+ serial_early_puts("Zero BSS");
+ r0.l = __bss_start;
+ r0.h = __bss_start;
+ r1 = 0 (x);
+ r2.l = __bss_end;
+ r2.h = __bss_end;
+ r2 = r2 - r0;
+ call _memset;
+
+.Lnorelocate:
+
+ /* Setup the actual stack in external memory */
+ r0.h = HI(CONFIG_STACKBASE);
+ r0.l = LO(CONFIG_STACKBASE);
+ sp = r0;
+ fp = sp;
+
+ /* Now lower ourselves from the highest interrupt level to
+ * the lowest. We do this by masking all interrupts but 15,
+ * setting the 15 handler to "board_init_f", raising the 15
+ * interrupt, and then returning from the highest interrupt
+ * level to the dummy "jump" until the interrupt controller
+ * services the pending 15 interrupt.
+ */
+ serial_early_puts("Lower to 15");
+ r0 = r7;
+ r1 = r6;
+ p0.l = LO(EVT15);
+ p0.h = HI(EVT15);
+ p1.l = _cpu_init_f;
+ p1.h = _cpu_init_f;
+ [p0] = p1;
+ p2.l = LO(IMASK);
+ p2.h = HI(IMASK);
+ p3.l = LO(EVT_IVG15);
+ p3.h = HI(EVT_IVG15);
+ [p2] = p3;
+ raise 15;
+ p4.l = .LWAIT_HERE;
+ p4.h = .LWAIT_HERE;
+ reti = p4;
+ rti;
+
+.LWAIT_HERE:
+ jump .LWAIT_HERE;
+ENDPROC(_start)
+
+LENTRY(_get_pc)
+ r0 = rets;
+#if ANOMALY_05000371
+ NOP;
+ NOP;
+ NOP;
+#endif
+ rts;
+ENDPROC(_get_pc)
diff --git a/cpu/blackfin/system_map.S b/cpu/blackfin/system_map.S
new file mode 100644
index 0000000..286d7f3
--- /dev/null
+++ b/cpu/blackfin/system_map.S
@@ -0,0 +1,18 @@
+/*
+ * system_map.S - optional symbol lookup for debugging
+ *
+ * Copyright (c) 2007 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_DEBUG_DUMP_SYMS
+.data
+.global _system_map
+.type _system_map,@object
+_system_map:
+#include SYM_FILE
+.asciz ""
+.size _system_map,.-_system_map
+#endif
diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c
new file mode 100644
index 0000000..4474fe5
--- /dev/null
+++ b/cpu/blackfin/traps.c
@@ -0,0 +1,353 @@
+/*
+ * U-boot - traps.c Routines related to interrupts and exceptions
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * This file is based on
+ * No original Copyright holder listed,
+ * Probabily original (C) Roman Zippel (assigned DJD, 1999)
+ *
+ * Copyright 2003 Metrowerks - for Blackfin
+ * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
+ * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/traps.h>
+#include <asm/cplb.h>
+#include <asm/io.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/mpu.h>
+#include <asm/mach-common/bits/trace.h>
+#include "cpu.h"
+
+#define trace_buffer_save(x) \
+ do { \
+ (x) = bfin_read_TBUFCTL(); \
+ bfin_write_TBUFCTL((x) & ~TBUFEN); \
+ } while (0)
+
+#define trace_buffer_restore(x) \
+ bfin_write_TBUFCTL((x))
+
+/* The purpose of this map is to provide a mapping of address<->cplb settings
+ * rather than an exact map of what is actually addressable on the part. This
+ * map covers all current Blackfin parts. If you try to access an address that
+ * is in this map but not actually on the part, you won't get an exception and
+ * reboot, you'll get an external hardware addressing error and reboot. Since
+ * only the ends matter (you did something wrong and the board reset), the means
+ * are largely irrelevant.
+ */
+struct memory_map {
+ uint32_t start, end;
+ uint32_t data_flags, inst_flags;
+};
+const struct memory_map const bfin_memory_map[] = {
+ { /* external memory */
+ .start = 0x00000000,
+ .end = 0x20000000,
+ .data_flags = SDRAM_DGENERIC,
+ .inst_flags = SDRAM_IGENERIC,
+ },
+ { /* async banks */
+ .start = 0x20000000,
+ .end = 0x30000000,
+ .data_flags = SDRAM_EBIU,
+ .inst_flags = SDRAM_INON_CHBL,
+ },
+ { /* everything on chip */
+ .start = 0xE0000000,
+ .end = 0xFFFFFFFF,
+ .data_flags = L1_DMEMORY,
+ .inst_flags = L1_IMEMORY,
+ }
+};
+
+void trap_c(struct pt_regs *regs)
+{
+ uint32_t trapnr = (regs->seqstat & EXCAUSE);
+ bool data = false;
+
+ switch (trapnr) {
+ /* 0x26 - Data CPLB Miss */
+ case VEC_CPLB_M:
+
+ if (ANOMALY_05000261) {
+ static uint32_t last_cplb_fault_retx;
+ /*
+ * Work around an anomaly: if we see a new DCPLB fault,
+ * return without doing anything. Then,
+ * if we get the same fault again, handle it.
+ */
+ if (last_cplb_fault_retx != regs->retx) {
+ last_cplb_fault_retx = regs->retx;
+ return;
+ }
+ }
+
+ data = true;
+ /* fall through */
+
+ /* 0x27 - Instruction CPLB Miss */
+ case VEC_CPLB_I_M: {
+ volatile uint32_t *CPLB_ADDR_BASE, *CPLB_DATA_BASE, *CPLB_ADDR, *CPLB_DATA;
+ uint32_t new_cplb_addr = 0, new_cplb_data = 0;
+ static size_t last_evicted;
+ size_t i;
+
+ new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
+
+ for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) {
+ /* if the exception is inside this range, lets use it */
+ if (new_cplb_addr >= bfin_memory_map[i].start &&
+ new_cplb_addr < bfin_memory_map[i].end)
+ break;
+ }
+ if (i == ARRAY_SIZE(bfin_memory_map)) {
+ printf("%cCPLB exception outside of memory map at 0x%p\n",
+ (data ? 'D' : 'I'), new_cplb_addr);
+ bfin_panic(regs);
+ } else
+ debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end);
+ new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
+
+ /* Turn the cache off */
+ SSYNC();
+ if (data) {
+ asm(" .align 8; ");
+ *pDMEM_CONTROL &= ~ENDCPLB;
+ } else {
+ asm(" .align 8; ");
+ *pIMEM_CONTROL &= ~ENICPLB;
+ }
+ SSYNC();
+
+ if (data) {
+ CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0;
+ CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0;
+ } else {
+ CPLB_ADDR_BASE = (uint32_t *)ICPLB_ADDR0;
+ CPLB_DATA_BASE = (uint32_t *)ICPLB_DATA0;
+ }
+
+ /* find the next unlocked entry and evict it */
+ i = last_evicted & 0xF;
+ debug("last evicted = %i\n", i);
+ CPLB_DATA = CPLB_DATA_BASE + i;
+ while (*CPLB_DATA & CPLB_LOCK) {
+ debug("skipping %i %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
+ i = (i + 1) & 0xF; /* wrap around */
+ CPLB_DATA = CPLB_DATA_BASE + i;
+ }
+ CPLB_ADDR = CPLB_ADDR_BASE + i;
+
+ debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA);
+ last_evicted = i + 1;
+ *CPLB_ADDR = new_cplb_addr;
+ *CPLB_DATA = new_cplb_data;
+
+ /* dump current table for debugging purposes */
+ CPLB_ADDR = CPLB_ADDR_BASE;
+ CPLB_DATA = CPLB_DATA_BASE;
+ for (i = 0; i < 16; ++i)
+ debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++);
+
+ /* Turn the cache back on */
+ SSYNC();
+ if (data) {
+ asm(" .align 8; ");
+ *pDMEM_CONTROL |= ENDCPLB;
+ } else {
+ asm(" .align 8; ");
+ *pIMEM_CONTROL |= ENICPLB;
+ }
+ SSYNC();
+
+ break;
+ }
+
+ default:
+ /* All traps come here */
+ bfin_panic(regs);
+ }
+}
+
+#ifdef CONFIG_DEBUG_DUMP
+# define ENABLE_DUMP 1
+#else
+# define ENABLE_DUMP 0
+#endif
+
+#ifdef CONFIG_DEBUG_DUMP_SYMS
+# define ENABLE_DUMP_SYMS 1
+#else
+# define ENABLE_DUMP_SYMS 0
+#endif
+
+static const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
+{
+ if (!ENABLE_DUMP_SYMS)
+ return NULL;
+
+ extern const char system_map[] __attribute__((__weak__));
+ const char *sym, *csym;
+ char *esym;
+ unsigned long sym_addr;
+
+ sym = system_map;
+ csym = NULL;
+ *caddr = 0;
+
+ while (*sym) {
+ sym_addr = simple_strtoul(sym, &esym, 16);
+ sym = esym + 1;
+ if (sym_addr > addr)
+ break;
+ *caddr = sym_addr;
+ csym = sym;
+ sym += strlen(sym) + 1;
+ }
+
+ return csym;
+}
+
+static void decode_address(char *buf, unsigned long address)
+{
+ unsigned long sym_addr;
+ const char *sym = symbol_lookup(address, &sym_addr);
+
+ if (sym) {
+ sprintf(buf, "<0x%p> { %s + 0x%x }", address, sym, address - sym_addr);
+ return;
+ }
+
+ if (!address)
+ sprintf(buf, "<0x%p> /* Maybe null pointer? */", address);
+ else if (address >= CFG_MONITOR_BASE &&
+ address < CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+ sprintf(buf, "<0x%p> /* somewhere in u-boot */", address);
+ else
+ sprintf(buf, "<0x%p> /* unknown address */", address);
+}
+
+void dump(struct pt_regs *fp)
+{
+ char buf[150];
+ size_t i;
+
+ if (!ENABLE_DUMP)
+ return;
+
+ printf("SEQUENCER STATUS:\n");
+ printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
+ fp->seqstat, fp->ipend, fp->syscfg);
+ printf(" HWERRCAUSE: 0x%lx\n", (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P);
+ printf(" EXCAUSE : 0x%lx\n", (fp->seqstat & EXCAUSE) >> EXCAUSE_P);
+ for (i = 6; i <= 15; ++i) {
+ if (fp->ipend & (1 << i)) {
+ decode_address(buf, bfin_read32(EVT0 + 4*i));
+ printf(" physical IVG%i asserted : %s\n", i, buf);
+ }
+ }
+ decode_address(buf, fp->rete);
+ printf(" RETE: %s\n", buf);
+ decode_address(buf, fp->retn);
+ printf(" RETN: %s\n", buf);
+ decode_address(buf, fp->retx);
+ printf(" RETX: %s\n", buf);
+ decode_address(buf, fp->rets);
+ printf(" RETS: %s\n", buf);
+ decode_address(buf, fp->pc);
+ printf(" PC : %s\n", buf);
+
+ if (fp->seqstat & EXCAUSE) {
+ decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
+ printf("DCPLB_FAULT_ADDR: %s\n", buf);
+ decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
+ printf("ICPLB_FAULT_ADDR: %s\n", buf);
+ }
+
+ printf("\nPROCESSOR STATE:\n");
+ printf(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
+ fp->r0, fp->r1, fp->r2, fp->r3);
+ printf(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
+ fp->r4, fp->r5, fp->r6, fp->r7);
+ printf(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
+ fp->p0, fp->p1, fp->p2, fp->p3);
+ printf(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
+ fp->p4, fp->p5, fp->fp, fp);
+ printf(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
+ fp->lb0, fp->lt0, fp->lc0);
+ printf(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
+ fp->lb1, fp->lt1, fp->lc1);
+ printf(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
+ fp->b0, fp->l0, fp->m0, fp->i0);
+ printf(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
+ fp->b1, fp->l1, fp->m1, fp->i1);
+ printf(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
+ fp->b2, fp->l2, fp->m2, fp->i2);
+ printf(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
+ fp->b3, fp->l3, fp->m3, fp->i3);
+ printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
+ fp->a0w, fp->a0x, fp->a1w, fp->a1x);
+
+ printf("USP : %08lx ASTAT: %08lx\n",
+ fp->usp, fp->astat);
+
+ printf("\n");
+}
+
+void dump_bfin_trace_buffer(void)
+{
+ char buf[150];
+ unsigned long tflags;
+ size_t i = 0;
+
+ if (!ENABLE_DUMP)
+ return;
+
+ trace_buffer_save(tflags);
+
+ printf("Hardware Trace:\n");
+
+ if (bfin_read_TBUFSTAT() & TBUFCNT) {
+ for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
+ decode_address(buf, bfin_read_TBUF());
+ printf("%4i Target : %s\n", i, buf);
+ decode_address(buf, bfin_read_TBUF());
+ printf(" Source : %s\n", buf);
+ }
+ }
+
+ trace_buffer_restore(tflags);
+}
+
+void bfin_panic(struct pt_regs *regs)
+{
+ if (ENABLE_DUMP) {
+ unsigned long tflags;
+ trace_buffer_save(tflags);
+ }
+
+ puts(
+ "\n"
+ "\n"
+ "\n"
+ "Ack! Something bad happened to the Blackfin!\n"
+ "\n"
+ );
+ dump(regs);
+ dump_bfin_trace_buffer();
+ printf(
+ "\n"
+ "Please reset the board\n"
+ "\n"
+ );
+ bfin_reset_or_hang();
+}
diff --git a/cpu/blackfin/watchdog.c b/cpu/blackfin/watchdog.c
new file mode 100644
index 0000000..b47c6b6
--- /dev/null
+++ b/cpu/blackfin/watchdog.c
@@ -0,0 +1,25 @@
+/*
+ * watchdog.c - driver for Blackfin on-chip watchdog
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/blackfin.h>
+
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ bfin_write_WDOG_STAT(0);
+}
+
+void hw_watchdog_init(void)
+{
+ bfin_write_WDOG_CNT(5 * get_sclk()); /* 5 second timeout */
+ hw_watchdog_reset();
+ bfin_write_WDOG_CTL(0x0);
+}
+#endif
diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S
index 0e2db12..1b47c97 100644
--- a/cpu/mcf5227x/start.S
+++ b/cpu/mcf5227x/start.S
@@ -354,3 +354,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S
index 2bd603d..ad04c09 100644
--- a/cpu/mcf523x/start.S
+++ b/cpu/mcf523x/start.S
@@ -338,3 +338,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk
index c3899c5..650e340 100644
--- a/cpu/mcf52x2/config.mk
+++ b/cpu/mcf52x2/config.mk
@@ -30,6 +30,7 @@ is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
+is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
@@ -47,6 +48,9 @@ endif
ifneq (,$(findstring CONFIG_M5272,$(is5272)))
PLATFORM_CPPFLAGS += -mcpu=5272
endif
+ifneq (,$(findstring CONFIG_M5275,$(is5275)))
+PLATFORM_CPPFLAGS += -mcpu=5275
+endif
ifneq (,$(findstring CONFIG_M5282,$(is5282)))
PLATFORM_CPPFLAGS += -mcpu=5282
endif
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index 71ea408..d5d3d33 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -6,6 +6,9 @@
* (C) Copyright 2005
* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
*
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -180,6 +183,69 @@ int watchdog_init(void)
#endif /* #ifdef CONFIG_M5272 */
+#ifdef CONFIG_M5275
+int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+
+ udelay(1000);
+
+ rcm->rcr = RCM_RCR_SOFTRST;
+
+ /* we don't return! */
+ return 0;
+};
+
+int checkcpu(void)
+{
+ char buf[32];
+
+ printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
+ strmhz(buf, CFG_CLK));
+ return 0;
+};
+
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdt->wsr = 0x5555;
+ wdt->wsr = 0xAAAA;
+}
+
+int watchdog_disable(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+ wdt->wsr = 0x5555; /* reset watchdog counter */
+ wdt->wsr = 0xAAAA;
+ wdt->wcr = 0; /* disable watchdog timer */
+
+ puts("WATCHDOG:disabled\n");
+ return (0);
+}
+
+int watchdog_init(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+ wdt->wcr = 0; /* disable watchdog */
+
+ /* set timeout and enable watchdog */
+ wdt->wmr =
+ ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
+ wdt->wsr = 0x5555; /* reset watchdog counter */
+ wdt->wsr = 0xAAAA;
+
+ puts("WATCHDOG:enabled\n");
+ return (0);
+}
+#endif /* #ifdef CONFIG_WATCHDOG */
+
+#endif /* #ifdef CONFIG_M5275 */
+
#ifdef CONFIG_M5282
int checkcpu(void)
{
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 458b85e..207a37e 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -10,6 +10,9 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -245,6 +248,114 @@ void uart_port_conf(void)
}
#endif /* #if defined(CONFIG_M5272) */
+#if defined(CONFIG_M5275)
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ /* if we come from RAM we assume the CPU is
+ * already initialized.
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+ volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
+ volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+ volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
+
+ /* Kill watchdog so we can initialize the PLL */
+ wdog_reg->wcr = 0;
+
+ /* Memory Controller: */
+ /* Flash */
+ csctrl_reg->ar0 = CFG_AR0_PRELIM;
+ csctrl_reg->cr0 = CFG_CR0_PRELIM;
+ csctrl_reg->mr0 = CFG_MR0_PRELIM;
+
+#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
+ csctrl_reg->ar1 = CFG_AR1_PRELIM;
+ csctrl_reg->cr1 = CFG_CR1_PRELIM;
+ csctrl_reg->mr1 = CFG_MR1_PRELIM;
+#endif
+
+#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
+ csctrl_reg->ar2 = CFG_AR2_PRELIM;
+ csctrl_reg->cr2 = CFG_CR2_PRELIM;
+ csctrl_reg->mr2 = CFG_MR2_PRELIM;
+#endif
+
+#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
+ csctrl_reg->ar3 = CFG_AR3_PRELIM;
+ csctrl_reg->cr3 = CFG_CR3_PRELIM;
+ csctrl_reg->mr3 = CFG_MR3_PRELIM;
+#endif
+
+#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
+ csctrl_reg->ar4 = CFG_AR4_PRELIM;
+ csctrl_reg->cr4 = CFG_CR4_PRELIM;
+ csctrl_reg->mr4 = CFG_MR4_PRELIM;
+#endif
+
+#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
+ csctrl_reg->ar5 = CFG_AR5_PRELIM;
+ csctrl_reg->cr5 = CFG_CR5_PRELIM;
+ csctrl_reg->mr5 = CFG_MR5_PRELIM;
+#endif
+
+#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
+ csctrl_reg->ar6 = CFG_AR6_PRELIM;
+ csctrl_reg->cr6 = CFG_CR6_PRELIM;
+ csctrl_reg->mr6 = CFG_MR6_PRELIM;
+#endif
+
+#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
+ csctrl_reg->ar7 = CFG_AR7_PRELIM;
+ csctrl_reg->cr7 = CFG_CR7_PRELIM;
+ csctrl_reg->mr7 = CFG_MR7_PRELIM;
+#endif
+
+#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
+
+#ifdef CONFIG_FSL_I2C
+ gpio_reg->par_feci2c = 0x000F;
+#endif
+
+ /* enable instruction cache now */
+ icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ gpio->par_uart |= UART0_ENABLE_MASK;
+ break;
+ case 1:
+ gpio->par_uart |= UART1_ENABLE_MASK;
+ break;
+ case 2:
+ gpio->par_uart |= UART2_ENABLE_MASK;
+ break;
+ }
+}
+#endif /* #if defined(CONFIG_M5275) */
+
#if defined(CONFIG_M5282)
/*
* Breath some life into the CPU...
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c
index 9167cec..b8fb7bb 100644
--- a/cpu/mcf52x2/interrupts.c
+++ b/cpu/mcf52x2/interrupts.c
@@ -59,7 +59,7 @@ void dtimer_intr_setup(void)
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
@@ -81,7 +81,7 @@ void dtimer_intr_setup(void)
intp->imrl0 &= ~CFG_TMRINTR_MASK;
}
#endif /* CONFIG_MCFTMR */
-#endif /* CONFIG_M5282 | CONFIG_M5271 */
+#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
int interrupt_init(void)
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index bc1e200..85a5c4d 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -64,8 +64,18 @@ int get_clocks (void)
#endif /* CONFIG_M5249 || CONFIG_M5253 */
+#if defined(CONFIG_M5275)
+ volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+
+ /* Setup PLL */
+ pll->syncr = 0x01080000;
+ while (!(pll->synsr & FMPLL_SYNSR_LOCK));
+ pll->syncr = 0x01000000;
+ while (!(pll->synsr & FMPLL_SYNSR_LOCK));
+#endif
+
gd->cpu_clk = CFG_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
#else
gd->bus_clk = gd->cpu_clk;
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index 260a09a..2bc0df3 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -56,9 +56,7 @@
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_R5200)
-.long 0x400
-#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
.long _start - TEXT_BASE
#else
.long _START
@@ -160,7 +158,7 @@ _copy_flash:
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
- movec %d0, %RAMBAR0
+ movec %d0, %FLASHBAR
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
nop
@@ -168,7 +166,7 @@ _after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
- movec %d0, %RAMBAR0
+ movec %d0, %RAMBAR1
#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
#endif
@@ -185,16 +183,15 @@ _after_flashbar_copy:
movec %d0, %VBR
#endif
-#ifdef CONFIG_R5200
- move.l #(_flash_setup-CFG_FLASH_BASE), %a0
- move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1
- move.l #(CFG_INIT_RAM_ADDR), %a2
-_copy_flash:
- move.l (%a0)+, (%a2)+
- cmp.l %a0, %a1
- bgt.s _copy_flash
- jmp CFG_INIT_RAM_ADDR
-_after_flash_copy:
+#ifdef CONFIG_M5275
+ /* Initialize IPSBAR */
+ move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
+ move.l %d0, 0x40000000
+/* movec %d0, %MBAR */
+
+ /* Initialize RAMBAR: locate SRAM and validate it */
+ move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
+ movec %d0, %RAMBAR1
#endif
#if 0
@@ -219,24 +216,6 @@ _after_flash_copy:
/*------------------------------------------------------------------------------*/
-#ifdef CONFIG_R5200
-_flash_setup:
- /* CSAR0 */
- move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0
- move.w %d0, 0x40000080
-
- /* CSCR0 */
- move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */
- move.w %d0, 0x4000008A
-
- /* CSMR0 */
- move.l #0x001f0001, %d0 /* 2 MB, valid */
- move.l %d0, 0x40000084
-
- jmp _after_flash_copy.L
-_flash_setup_end:
-#endif
-
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
@@ -394,6 +373,25 @@ icache_enable:
rts
#endif
+#if defined(CONFIG_M5275)
+/*
+ * Instruction cache only
+ */
+ .globl icache_enable
+icache_enable:
+ move.l #0x01400000, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #0x0000c000, %d0 /* Setup SDRAM caching */
+ movec %d0, %ACR0 /* Enable cache */
+ move.l #0x00000000, %d0 /* No other caching */
+ movec %d0, %ACR1 /* Enable cache */
+ move.l #0x80400100, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Enable cache */
+ moveq #1, %d0
+ move.l %d0, icache_state
+ rts
+#endif
+
#ifdef CONFIG_M5282
.globl icache_enable
icache_enable:
@@ -478,3 +476,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index 61be2ea..a524f70 100644
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -333,3 +333,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf5445x/Makefile b/cpu/mcf5445x/Makefile
index 26ec298..a549fdd 100644
--- a/cpu/mcf5445x/Makefile
+++ b/cpu/mcf5445x/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
-COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o
+COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c
new file mode 100644
index 0000000..44d8505
--- /dev/null
+++ b/cpu/mcf5445x/dspi.c
@@ -0,0 +1,73 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+
+#if defined(CONFIG_CF_DSPI)
+#include <asm/immap.h>
+void dspi_init(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 |
+ GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 |
+ GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK;
+
+ dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
+ DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
+ DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
+ DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
+
+ dspi->dctar0 = DSPI_DCTAR_TRSZ(7) | DSPI_DCTAR_CPOL | DSPI_DCTAR_CPHA |
+ DSPI_DCTAR_PCSSCK_1CLK | DSPI_DCTAR_PASC(0) |
+ DSPI_DCTAR_PDT(0) | DSPI_DCTAR_CSSCK(0) |
+ DSPI_DCTAR_ASC(0) | DSPI_DCTAR_PBR(0) |
+ DSPI_DCTAR_DT(1) | DSPI_DCTAR_BR(1);
+}
+
+void dspi_tx(int chipsel, u8 attrib, u16 data)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ while ((dspi->dsr & 0x0000F000) >= 4) ;
+
+ dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
+}
+
+u16 dspi_rx(void)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ while ((dspi->dsr & 0x000000F0) == 0) ;
+
+ return (dspi->drfr & 0xFFFF);
+}
+
+#endif /* CONFIG_HARD_SPI */
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index d64c5af..0c5194a 100644
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -379,3 +379,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S
index 442665f..c12d7a0 100644
--- a/cpu/mcf547x_8x/start.S
+++ b/cpu/mcf547x_8x/start.S
@@ -359,3 +359,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index bff3cef..36de78d 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -42,6 +42,30 @@ int checkcpu(void)
u32 pvr = get_pvr();
u32 spridr;
char buf[32];
+ int i;
+
+#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
+ const struct cpu_type {
+ char name[15];
+ u32 partid;
+ } cpu_type_list [] = {
+ CPU_TYPE_ENTRY(8311),
+ CPU_TYPE_ENTRY(8313),
+ CPU_TYPE_ENTRY(8314),
+ CPU_TYPE_ENTRY(8315),
+ CPU_TYPE_ENTRY(8321),
+ CPU_TYPE_ENTRY(8323),
+ CPU_TYPE_ENTRY(8343),
+ CPU_TYPE_ENTRY(8347_TBGA_),
+ CPU_TYPE_ENTRY(8347_PBGA_),
+ CPU_TYPE_ENTRY(8349),
+ CPU_TYPE_ENTRY(8358_TBGA_),
+ CPU_TYPE_ENTRY(8358_PBGA_),
+ CPU_TYPE_ENTRY(8360),
+ CPU_TYPE_ENTRY(8377),
+ CPU_TYPE_ENTRY(8378),
+ CPU_TYPE_ENTRY(8379),
+ };
immr = (immap_t *)CFG_IMMR;
@@ -69,130 +93,26 @@ int checkcpu(void)
}
spridr = immr->sysconf.spridr;
- switch(spridr) {
- case SPR_8349E_REV10:
- case SPR_8349E_REV11:
- case SPR_8349E_REV31:
- puts("MPC8349E, ");
- break;
- case SPR_8349_REV10:
- case SPR_8349_REV11:
- case SPR_8349_REV31:
- puts("MPC8349, ");
- break;
- case SPR_8347E_REV10_TBGA:
- case SPR_8347E_REV11_TBGA:
- case SPR_8347E_REV31_TBGA:
- case SPR_8347E_REV10_PBGA:
- case SPR_8347E_REV11_PBGA:
- case SPR_8347E_REV31_PBGA:
- puts("MPC8347E, ");
- break;
- case SPR_8347_REV10_TBGA:
- case SPR_8347_REV11_TBGA:
- case SPR_8347_REV31_TBGA:
- case SPR_8347_REV10_PBGA:
- case SPR_8347_REV11_PBGA:
- case SPR_8347_REV31_PBGA:
- puts("MPC8347, ");
- break;
- case SPR_8343E_REV10:
- case SPR_8343E_REV11:
- case SPR_8343E_REV31:
- puts("MPC8343E, ");
- break;
- case SPR_8343_REV10:
- case SPR_8343_REV11:
- case SPR_8343_REV31:
- puts("MPC8343, ");
- break;
- case SPR_8360E_REV10:
- case SPR_8360E_REV11:
- case SPR_8360E_REV12:
- case SPR_8360E_REV20:
- case SPR_8360E_REV21:
- puts("MPC8360E, ");
- break;
- case SPR_8360_REV10:
- case SPR_8360_REV11:
- case SPR_8360_REV12:
- case SPR_8360_REV20:
- case SPR_8360_REV21:
- puts("MPC8360, ");
- break;
- case SPR_8323E_REV10:
- case SPR_8323E_REV11:
- puts("MPC8323E, ");
- break;
- case SPR_8323_REV10:
- case SPR_8323_REV11:
- puts("MPC8323, ");
- break;
- case SPR_8321E_REV10:
- case SPR_8321E_REV11:
- puts("MPC8321E, ");
- break;
- case SPR_8321_REV10:
- case SPR_8321_REV11:
- puts("MPC8321, ");
- break;
- case SPR_8311_REV10:
- puts("MPC8311, ");
- break;
- case SPR_8311E_REV10:
- puts("MPC8311E, ");
- break;
- case SPR_8313_REV10:
- puts("MPC8313, ");
- break;
- case SPR_8313E_REV10:
- puts("MPC8313E, ");
- break;
- case SPR_8315E_REV10:
- puts("MPC8315E, ");
- break;
- case SPR_8315_REV10:
- puts("MPC8315, ");
- break;
- case SPR_8314E_REV10:
- puts("MPC8314E, ");
- break;
- case SPR_8314_REV10:
- puts("MPC8314, ");
- break;
- case SPR_8379E_REV10:
- puts("MPC8379E, ");
- break;
- case SPR_8379_REV10:
- puts("MPC8379, ");
- break;
- case SPR_8378E_REV10:
- puts("MPC8378E, ");
- break;
- case SPR_8378_REV10:
- puts("MPC8378, ");
- break;
- case SPR_8377E_REV10:
- puts("MPC8377E, ");
- break;
- case SPR_8377_REV10:
- puts("MPC8377, ");
- break;
- default:
- printf("Rev: Unknown revision number:%08x\n"
- "Warning: Unsupported cpu revision!\n",spridr);
- return 0;
- }
-#if defined(CONFIG_MPC834X)
- /* Multiple revisons of 834x processors may have the same SPRIDR value.
- * So use PVR to identify the revision number.
- */
- printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
-#else
- printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
-#endif
- printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
+ for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
+ if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
+ puts("MPC");
+ puts(cpu_type_list[i].name);
+ if (IS_E_PROCESSOR(spridr))
+ puts("E");
+ if (REVID_MAJOR(spridr) >= 2)
+ puts("A");
+ printf(", Rev: %d.%d", REVID_MAJOR(spridr),
+ REVID_MINOR(spridr));
+ break;
+ }
+
+ if (i == ARRAY_SIZE(cpu_type_list))
+ printf("(SPRIDR %08x unknown), ", spridr);
+
+ printf(" at %s MHz, ", strmhz(buf, clock));
+
+ printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
return 0;
}
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 0acca47..97ac7bb 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -34,10 +34,13 @@
#include <asm/mmu.h>
#include <spd_sdram.h>
+DECLARE_GLOBAL_DATA_PTR;
+
void board_add_ram_info(int use_default)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
+ char buf[32];
printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
>> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
@@ -48,9 +51,11 @@ void board_add_ram_info(int use_default)
puts(", 64-bit");
if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
- puts(", ECC on)");
+ puts(", ECC on");
else
- puts(", ECC off)");
+ puts(", ECC off");
+
+ printf(", %s MHz)", strmhz(buf, gd->mem_clk));
#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
puts("\nSDRAM: ");
@@ -60,8 +65,6 @@ void board_add_ram_info(int use_default)
#ifdef CONFIG_SPD_EEPROM
-DECLARE_GLOBAL_DATA_PTR;
-
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
extern void dma_init(void);
extern uint dma_check(void);
@@ -78,12 +81,12 @@ extern int dma_xfer(void *dest, uint count, void *src);
int
picos_to_clk(int picos)
{
- unsigned int ddr_bus_clk;
+ unsigned int mem_bus_clk;
int clks;
- ddr_bus_clk = gd->ddr_clk >> 1;
- clks = picos / (1000000000 / (ddr_bus_clk / 1000));
- if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
+ mem_bus_clk = gd->mem_clk >> 1;
+ clks = picos / (1000000000 / (mem_bus_clk / 1000));
+ if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
clks++;
return clks;
@@ -313,7 +316,7 @@ long int spd_sdram()
debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
- ddrc_clk = gd->ddr_clk / 1000000;
+ ddrc_clk = gd->mem_clk / 1000000;
effective_data_rate = 0;
if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index f598699..16145dd 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -122,9 +122,9 @@ int get_clocks(void)
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
- u32 ddr_clk;
+ u32 mem_clk;
#if defined(CONFIG_MPC8360)
- u32 ddr_sec_clk;
+ u32 mem_sec_clk;
#endif
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
u32 qepmf;
@@ -400,11 +400,11 @@ int get_clocks(void)
return -12;
}
- ddr_clk = csb_clk *
+ mem_clk = csb_clk *
(1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
#if defined(CONFIG_MPC8360)
- ddr_sec_clk = csb_clk * (1 +
+ mem_sec_clk = csb_clk * (1 +
((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
#endif
@@ -466,9 +466,9 @@ int get_clocks(void)
gd->enc_clk = enc_clk;
gd->lbiu_clk = lbiu_clk;
gd->lclk_clk = lclk_clk;
- gd->ddr_clk = ddr_clk;
+ gd->mem_clk = mem_clk;
#if defined(CONFIG_MPC8360)
- gd->ddr_sec_clk = ddr_sec_clk;
+ gd->mem_sec_clk = mem_sec_clk;
#endif
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
gd->qe_clk = qe_clk;
@@ -508,9 +508,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
#endif
printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
- printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
+ printf(" DDR: %4d MHz\n", gd->mem_clk / 1000000);
#if defined(CONFIG_MPC8360)
- printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
+ printf(" DDR Secondary: %4d MHz\n", gd->mem_sec_clk / 1000000);
#endif
printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index 309eb30..fdf9d35 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -172,8 +172,11 @@ boot_warm: /* time t 5 */
/* there and deflate the flash size back to minimal size */
/*------------------------------------------------------------*/
bl map_flash_by_law1
- lis r4, (CFG_MONITOR_BASE)@h
- ori r4, r4, (CFG_MONITOR_BASE)@l
+
+ GET_GOT /* initialize GOT access */
+ lwz r4, GOT(_start)
+ addi r4, r4, -EXC_OFF_SYS_RESET
+
addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r5
blr
@@ -872,8 +875,8 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lwz r4, GOT(_start)
+ addi r4, r4, -EXC_OFF_SYS_RESET
lwz r5, GOT(__init_end)
sub r5, r5, r4
li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index d990250..007cb4f 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -274,7 +274,7 @@ static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
static void ppc_4xx_eth_halt (struct eth_device *dev)
{
EMAC_4XX_HW_PST hw_p = dev->priv;
- uint32_t failsafe = 10000;
+ u32 val = 10000;
out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
@@ -290,8 +290,8 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
/* wait for reset */
while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
udelay (1000); /* Delay 1 MS so as not to hammer the register */
- failsafe--;
- if (failsafe == 0)
+ val--;
+ if (val == 0)
break;
}
@@ -308,6 +308,13 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
hw_p->print_speed = 1; /* print speed message again next time */
#endif
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
+ mfsdr(SDR0_ETH_CFG, val);
+ val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
+ mtsdr(SDR0_ETH_CFG, val);
+#endif
+
return;
}
@@ -494,11 +501,18 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
u32 zmiifer; /* ZMII0_FER reg. */
u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
+ int mode;
zmiifer = 0;
rmiifer = 0;
rmiifer1 = 0;
+#if defined(CONFIG_460EX)
+ mode = 9;
+#else
+ mode = 10;
+#endif
+
/* TODO:
* NOTE: 460GT has 2 RGMII bridge cores:
* emac0 ------ RGMII0_BASE
@@ -520,7 +534,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
* Right now only 2*RGMII is supported. Please extend when needed.
* sr - 2008-02-19
*/
- switch (9) {
+ switch (mode) {
case 1:
/* 1 MII - 460EX */
/* GMC0 EMAC4_0, ZMII Bridge */
@@ -703,6 +717,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#ifdef CONFIG_4xx_DCACHE
static u32 last_used_ea = 0;
#endif
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_405EX)
+ int rgmii_channel;
+#endif
EMAC_4XX_HW_PST hw_p = dev->priv;
@@ -836,10 +855,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
reg = CONFIG_PHY1_ADDR;
break;
#endif
-#if defined (CONFIG_440GX)
+#if defined (CONFIG_PHY2_ADDR)
case 2:
reg = CONFIG_PHY2_ADDR;
break;
+#endif
+#if defined (CONFIG_PHY3_ADDR)
case 3:
reg = CONFIG_PHY3_ADDR;
break;
@@ -1006,12 +1027,17 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
+ if (devnum >= 2)
+ rgmii_channel = devnum - 2;
+ else
+ rgmii_channel = devnum;
+
if (speed == 1000)
- reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
+ reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
else if (speed == 100)
- reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
+ reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
else if (speed == 10)
- reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
+ reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
else {
printf("Error in RGMII Speed\n");
return -1;
@@ -1131,7 +1157,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
- mtdcr (malrxctp8r, hw_p->rx);
+ mtdcr (malrxctp8r, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
#else
@@ -1160,6 +1186,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
break;
#endif /* CONFIG_440GX */
+#if defined (CONFIG_460GT)
+ case 2:
+ /* setup MAL tx & rx channel pointers */
+ mtdcr (maltxbattr, 0x0);
+ mtdcr (malrxbattr, 0x0);
+ mtdcr (maltxctp2r, hw_p->tx_phys);
+ mtdcr (malrxctp16r, hw_p->rx_phys);
+ /* set RX buffer size */
+ mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
+ break;
+ case 3:
+ /* setup MAL tx & rx channel pointers */
+ mtdcr (maltxbattr, 0x0);
+ mtdcr (malrxbattr, 0x0);
+ mtdcr (maltxctp3r, hw_p->tx_phys);
+ mtdcr (malrxctp24r, hw_p->rx_phys);
+ /* set RX buffer size */
+ mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
+ break;
+#endif /* CONFIG_460GT */
case 0:
default:
/* setup MAL tx & rx channel pointers */
@@ -1866,14 +1912,22 @@ int ppc_4xx_eth_initialize (bd_t * bis)
case 2:
memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
bis->bi_enet2addr, 6);
+#if defined(CONFIG_460GT)
+ hw_addr[eth_num] = 0x300;
+#else
hw_addr[eth_num] = 0x400;
+#endif
break;
#endif
#ifdef CONFIG_HAS_ETH3
case 3:
memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
bis->bi_enet3addr, 6);
+#if defined(CONFIG_460GT)
+ hw_addr[eth_num] = 0x400;
+#else
hw_addr[eth_num] = 0x600;
+#endif
break;
#endif
}
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 5d15e2f..42eabfe 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -99,10 +99,107 @@ DECLARE_GLOBAL_DATA_PTR;
# endif
#endif /* CFG_INIT_DCACHE_CS */
+#ifndef CFG_PLL_RECONFIG
+#define CFG_PLL_RECONFIG 0
+#endif
+
+void reconfigure_pll(u32 new_cpu_freq)
+{
+#if defined(CONFIG_440EPX)
+ int reset_needed = 0;
+ u32 reg, temp;
+ u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
+ fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
+ fbdv, target_fbdv, lfbdv, target_lfbdv,
+ perdv0, target_perdv0, /* CLK_PERD */
+ spcid0, target_spcid0; /* CLK_SPCID */
+
+ /* Reconfigure clocks if necessary.
+ * See PPC440EPx User's Manual, sections 8.2 and 14 */
+ if (new_cpu_freq == 667) {
+ target_prbdv0 = 2;
+ target_fwdva = 2;
+ target_fwdvb = 4;
+ target_fbdv = 20;
+ target_lfbdv = 1;
+ target_perdv0 = 4;
+ target_spcid0 = 4;
+
+ mfcpr(clk_primbd, reg);
+ temp = (reg & PRBDV_MASK) >> 24;
+ prbdv0 = temp ? temp : 8;
+ if (prbdv0 != target_prbdv0) {
+ reg &= ~PRBDV_MASK;
+ reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
+ mtcpr(clk_primbd, reg);
+ reset_needed = 1;
+ }
+
+ mfcpr(clk_plld, reg);
+
+ temp = (reg & PLLD_FWDVA_MASK) >> 16;
+ fwdva = temp ? temp : 16;
+
+ temp = (reg & PLLD_FWDVB_MASK) >> 8;
+ fwdvb = temp ? temp : 8;
+
+ temp = (reg & PLLD_FBDV_MASK) >> 24;
+ fbdv = temp ? temp : 32;
+
+ temp = (reg & PLLD_LFBDV_MASK);
+ lfbdv = temp ? temp : 64;
+
+ if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
+ reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
+ PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
+ reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
+ ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
+ ((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
+ (target_lfbdv == 64 ? 0 : target_lfbdv);
+ mtcpr(clk_plld, reg);
+ reset_needed = 1;
+ }
+
+ mfcpr(clk_perd, reg);
+ perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
+ if (perdv0 != target_perdv0) {
+ reg &= ~CPR0_PERD_PERDV0_MASK;
+ reg |= (target_perdv0 << 24);
+ mtcpr(clk_perd, reg);
+ reset_needed = 1;
+ }
+
+ mfcpr(clk_spcid, reg);
+ temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
+ spcid0 = temp ? temp : 4;
+ if (spcid0 != target_spcid0) {
+ reg &= ~CPR0_SPCID_SPCIDV0_MASK;
+ reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
+ mtcpr(clk_spcid, reg);
+ reset_needed = 1;
+ }
+
+ /* Set reload inhibit so configuration will persist across
+ * processor resets */
+ mfcpr(clk_icfg, reg);
+ reg &= ~CPR0_ICFG_RLI_MASK;
+ reg |= 1 << 31;
+ mtcpr(clk_icfg, reg);
+ }
+
+ /* Reset processor if configuration changed */
+ if (reset_needed) {
+ __asm__ __volatile__ ("sync; isync");
+ mtspr(dbcr0, 0x20000000);
+ }
+#endif
+}
+
/*
* Breath some life into the CPU...
*
- * Set up the memory map,
+ * Reconfigure PLL if necessary,
+ * set up the memory map,
* initialize a bunch of registers
*/
void
@@ -111,6 +208,7 @@ cpu_init_f (void)
#if defined(CONFIG_WATCHDOG)
unsigned long val;
#endif
+ reconfigure_pll(CFG_PLL_RECONFIG);
#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
/*
@@ -135,6 +233,7 @@ cpu_init_f (void)
#if defined (CFG_GPIO0_TCR)
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
#endif
+#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */
#if defined (CONFIG_405EP)
/*
@@ -147,7 +246,6 @@ cpu_init_f (void)
*/
mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
#endif /* CONFIG_405EP */
-#endif /* CONFIG_405EP */
#if defined(CFG_4xx_GPIO_TABLE)
gpio_set_chip_configuration();
diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c
index 60f89c9..e20c9eb 100644
--- a/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/cpu/ppc4xx/denali_spd_ddr2.c
@@ -1093,10 +1093,10 @@ long int initdram(int board_type)
program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
- /*------------------------------------------------------------------
+ /*
* TODO: tFAW not found in SPD. Value of 13 taken from Sequoia
- * board SDRAM, but may be overly concervate.
- *-----------------------------------------------------------------*/
+ * board SDRAM, but may be overly conservative.
+ */
mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
DDR0_07_TFAW_ENCODE(13) |
DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
@@ -1181,26 +1181,29 @@ long int initdram(int board_type)
denali_wait_for_dlllock();
#if defined(CONFIG_DDR_DATA_EYE)
- /* -----------------------------------------------------------+
- * Perform data eye search if requested.
- * ----------------------------------------------------------*/
- program_tlb(0, CFG_SDRAM_BASE, dram_size, TLB_WORD2_I_ENABLE);
+ /*
+ * Map the first 1 MiB of memory in the TLB, and perform the data eye
+ * search.
+ */
+ program_tlb(0, CFG_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
denali_core_search_data_eye();
denali_sdram_register_dump();
- remove_tlb(CFG_SDRAM_BASE, dram_size);
+ remove_tlb(CFG_SDRAM_BASE, TLB_1MB_SIZE);
#endif
#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
program_tlb(0, CFG_SDRAM_BASE, dram_size, 0);
sync();
- eieio();
/* Zero the memory */
debug("Zeroing SDRAM...");
- dcbz_area(CFG_SDRAM_BASE, dram_size);
+#if defined(CFG_MEM_TOP_HIDE)
+ dcbz_area(CFG_SDRAM_BASE, dram_size - CFG_MEM_TOP_HIDE);
+#else
+#error Please define CFG_MEM_TOP_HIDE (see README) in your board config file
+#endif
dflush();
debug("Completed\n");
sync();
- eieio();
remove_tlb(CFG_SDRAM_BASE, dram_size);
#if defined(CONFIG_DDR_ECC)
@@ -1211,7 +1214,6 @@ long int initdram(int board_type)
u32 val;
sync();
- eieio();
/* Clear error status */
mfsdram(DDR0_00, val);
mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
@@ -1229,7 +1231,6 @@ long int initdram(int board_type)
print_mcsr();
#endif
sync();
- eieio();
}
#endif /* defined(CONFIG_DDR_ECC) */
#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 698bcb5..8620e2b 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -218,15 +218,16 @@ static void uic_interrupt(u32 uic_base, int vec_base)
} else {
set_dcr(uic_base + UIC_ER,
get_dcr(uic_base + UIC_ER) &
- ~(0x80000000 >> vec));
+ ~(0x80000000 >> (vec & 0x1f)));
printf("Masking bogus interrupt vector %d"
" (UIC_BASE=0x%x)\n", vec, uic_base);
}
/*
- * After servicing the interrupt, we have to remove the status indicator.
+ * After servicing the interrupt, we have to remove the
+ * status indicator
*/
- set_dcr(uic_base + UIC_SR, (0x80000000 >> vec));
+ set_dcr(uic_base + UIC_SR, (0x80000000 >> (vec & 0x1f)));
}
/*
diff --git a/cpu/sh4/cpu.c b/cpu/sh4/cpu.c
index 0ebf951..d94e139 100644
--- a/cpu/sh4/cpu.c
+++ b/cpu/sh4/cpu.c
@@ -24,6 +24,7 @@
#include <common.h>
#include <command.h>
#include <asm/processor.h>
+#include <asm/cache.h>
int checkcpu(void)
{
@@ -51,7 +52,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
void flush_cache (unsigned long addr, unsigned long size)
{
-
+ dcache_invalid_range( addr , addr + size );
}
void icache_enable (void)