diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm926ejs/at91/Makefile | 3 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 175 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91/clock.c | 12 | ||||
| -rw-r--r-- | cpu/mpc512x/Makefile | 10 | ||||
| -rw-r--r-- | cpu/mpc512x/fixed_sdram.c | 113 | ||||
| -rw-r--r-- | cpu/mpc5xxx/ide.c | 3 | ||||
| -rw-r--r-- | cpu/mpc83xx/cpu_init.c | 4 | ||||
| -rw-r--r-- | cpu/ppc4xx/44x_spd_ddr2.c | 42 | ||||
| -rw-r--r-- | cpu/ppc4xx/4xx_pci.c | 44 | ||||
| -rw-r--r-- | cpu/ppc4xx/cpu.c | 2 | ||||
| -rw-r--r-- | cpu/ppc4xx/cpu_init.c | 5 | ||||
| -rw-r--r-- | cpu/ppc4xx/start.S | 1 | ||||
| -rw-r--r-- | cpu/ppc4xx/uic.c | 2 | ||||
| -rw-r--r-- | cpu/sh2/u-boot.lds | 95 | ||||
| -rw-r--r-- | cpu/sh3/u-boot.lds | 102 | ||||
| -rw-r--r-- | cpu/sh4/u-boot.lds | 99 |
16 files changed, 679 insertions, 33 deletions
diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile index 3da89f4..4f467be 100644 --- a/cpu/arm926ejs/at91/Makefile +++ b/cpu/arm926ejs/at91/Makefile @@ -29,8 +29,11 @@ COBJS-$(CONFIG_AT91CAP9) += at91cap9_devices.o COBJS-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o COBJS-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o COBJS-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o +COBJS-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o +COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o +COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o COBJS-$(CONFIG_AT91_LED) += led.o COBJS-y += clock.o COBJS-y += cpu.o diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c new file mode 100644 index 0000000..98d90f2 --- /dev/null +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> + +void at91_serial0_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0); +} + +void at91_serial1_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1); +} + +void at91_serial2_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PD6, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PD7, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2); +} + +void at91_serial3_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);; +} + +void at91_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_serial0_hw_init(); +#endif + +#ifdef CONFIG_USART1 + at91_serial1_hw_init(); +#endif + +#ifdef CONFIG_USART2 + at91_serial2_hw_init(); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_serial3_hw_init(); +#endif +} + +#ifdef CONFIG_ATMEL_SPI +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0); + + if (cs_mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PB3, 0); + } + if (cs_mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PB18, 0); + } + if (cs_mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PB19, 0); + } + if (cs_mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PD27, 0); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PB3, 0); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PB18, 0); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PB19, 0); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PD27, 0); + } +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */ + at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI1); + + if (cs_mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PB17, 0); + } + if (cs_mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PD28, 0); + } + if (cs_mask & (1 << 2)) { + at91_set_A_periph(AT91_PIN_PD18, 0); + } + if (cs_mask & (1 << 3)) { + at91_set_A_periph(AT91_PIN_PD19, 0); + } + if (cs_mask & (1 << 4)) { + at91_set_gpio_output(AT91_PIN_PB17, 0); + } + if (cs_mask & (1 << 5)) { + at91_set_gpio_output(AT91_PIN_PD28, 0); + } + if (cs_mask & (1 << 6)) { + at91_set_gpio_output(AT91_PIN_PD18, 0); + } + if (cs_mask & (1 << 7)) { + at91_set_gpio_output(AT91_PIN_PD19, 0); + } + +} +#endif + +#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */ + at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */ +#ifndef CONFIG_RMII + at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */ + at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */ + at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */ + at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */ +#endif +} +#endif diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c index 9f03468..574f488 100644 --- a/cpu/arm926ejs/at91/clock.c +++ b/cpu/arm926ejs/at91/clock.c @@ -183,15 +183,23 @@ int at91_clock_init(unsigned long main_clock) * For now, assume this parentage won't change. */ mckr = at91_sys_read(AT91_PMC_MCKR); +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) + /* plla divisor by 2 */ + plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); +#endif freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS); + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ #if defined(CONFIG_AT91RM9200) mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ #elif defined(CONFIG_AT91SAM9G20) mck_rate_hz = (mckr & AT91_PMC_MDIV) ? - freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ + freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ if (mckr & AT91_PMC_PDIV) - freq /= 2; /* processor clock division */ + freq /= 2; /* processor clock division */ +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) + mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? + freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ #else mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ #endif diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile index 022c676..427db7a 100644 --- a/cpu/mpc512x/Makefile +++ b/cpu/mpc512x/Makefile @@ -27,7 +27,15 @@ $(shell mkdir -p $(OBJTREE)/board/freescale/common) LIB = $(obj)lib$(CPU).a START = start.o -COBJS-y := traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o +COBJS-y := cpu.o +COBJS-y += traps.o +COBJS-y += cpu_init.o +COBJS-y += fixed_sdram.o +COBJS-y += i2c.o +COBJS-y += interrupts.o +COBJS-y += iopin.o +COBJS-y += serial.o +COBJS-y += speed.o COBJS-${CONFIG_FSL_DIU_FB} += diu.o COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_diu_fb.o COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_logo_bmp.o diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c new file mode 100644 index 0000000..d906903 --- /dev/null +++ b/cpu/mpc512x/fixed_sdram.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2007-2009 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/mpc512x.h> + +/* + * fixed sdram init: + * The board doesn't use memory modules that have serial presence + * detect or similar mechanism for discovery of the DRAM settings + */ +long int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + u32 i; + + /* Initialize IO Control */ + out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); + + /* Initialize DDR Local Window */ + out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000); + out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1); + sync_law(&im->sysconf.ddrlaw.ar); + + /* Enable DDR */ + out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN); + + /* Initialize DDR Priority Manager */ + out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); + out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2); + out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG); + out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU); + out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML); + out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU); + out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML); + out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU); + out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML); + out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU); + out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML); + out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU); + out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML); + out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU); + out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL); + out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU); + out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL); + out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU); + out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL); + out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU); + out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL); + out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU); + out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL); + + /* Initialize MDDRC */ + out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG); + out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0); + out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1); + out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2); + + /* Initialize DDR */ + for (i = 0; i < 10; i++) + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + + /* Start MDDRC */ + out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN); + out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN); + + return msize; +} diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c index 9e8f29b..d337abb 100644 --- a/cpu/mpc5xxx/ide.c +++ b/cpu/mpc5xxx/ide.c @@ -45,6 +45,9 @@ int ide_preinit (void) #if defined(CONFIG_SYS_ATA_CS_ON_I2C2) /* ATA cs0/1 on i2c2 clk/io */ reg = (reg & ~0x03000000ul) | 0x02000000ul; +#elif defined(CONFIG_SYS_ATA_CS_ON_TIMER01) + /* ATA cs0/1 on Timer 0/1 */ + reg = (reg & ~0x03000000ul) | 0x03000000ul; #else /* ATA cs0/1 on Local Plus cs4/5 */ reg = (reg & ~0x03000000ul) | 0x01000000ul; diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 414565c..03b6c86 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -303,11 +303,11 @@ void cpu_init_f (volatile immap_t * im) struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR; /* Configure interface. */ - setbits_be32((void *)ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); + setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); /* Wait for clock to stabilize */ do { - temp = in_be32((void *)ehci->control); + temp = in_be32(&ehci->control); udelay(1000); } while (!(temp & PHY_CLK_VALID)); #endif diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 33788cc..2ab2336 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -60,6 +60,14 @@ "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ } while (0) +#define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic) \ + do { \ + u32 data; \ + data = mfdcr(SDRAM_##mnemonic); \ + printf("%20s[%02x] = 0x%08X\n", \ + "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ + } while (0) + #if defined(CONFIG_440) /* * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 @@ -714,11 +722,11 @@ static void check_mem_type(unsigned long *dimm_populated, spd_ddr_init_hang (); break; case 7: - debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num); + debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num); dimm_populated[dimm_num] = SDRAM_DDR1; break; case 8: - debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num); + debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num); dimm_populated[dimm_num] = SDRAM_DDR2; break; default: @@ -796,7 +804,7 @@ static void check_frequency(unsigned long *dimm_populated, else cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + ((tcyc_reg & 0x0F)*10); - debug("cycle_time=%d [10 picoseconds]\n", cycle_time); + debug("cycle_time=%lu [10 picoseconds]\n", cycle_time); if (cycle_time > (calc_cycle_time + 10)) { /* @@ -1407,7 +1415,7 @@ static void program_mode(unsigned long *dimm_populated, mfsdr(SDR0_DDR0, sdr_ddrpll); sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1); - debug("sdram_freq=%d\n", sdram_freq); + debug("sdram_freq=%lu\n", sdram_freq); /*------------------------------------------------------------------ * Handle the timing. We need to find the worst case timing of all @@ -1437,7 +1445,7 @@ static void program_mode(unsigned long *dimm_populated, /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */ cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); - debug("cas_bit[SPD byte 18]=%02x\n", cas_bit); + debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit); /* For a particular DIMM, grab the three CAS values it supports */ for (cas_index = 0; cas_index < 3; cas_index++) { @@ -1469,7 +1477,7 @@ static void program_mode(unsigned long *dimm_populated, (((tcyc_reg & 0xF0) >> 4) * 100) + ((tcyc_reg & 0x0F)*10); } - debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index, + debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index, cycle_time_ns_x_100[cas_index]); } @@ -1580,9 +1588,9 @@ static void program_mode(unsigned long *dimm_populated, cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10; cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10; cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10; - debug("cycle_3_0_clk=%d\n", cycle_3_0_clk); - debug("cycle_4_0_clk=%d\n", cycle_4_0_clk); - debug("cycle_5_0_clk=%d\n", cycle_5_0_clk); + debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk); + debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk); + debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk); if (sdram_ddr1 == TRUE) { /* DDR1 */ if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) { @@ -2797,13 +2805,13 @@ calibration_loop: } mfsdram(SDRAM_DLCR, val); - debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val); + debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val); mfsdram(SDRAM_RQDC, val); - debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val); + debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val); mfsdram(SDRAM_RFDC, val); - debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val); + debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val); mfsdram(SDRAM_RDCC, val); - debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val); + debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val); } #else /* calibration test with hardvalues */ /*-----------------------------------------------------------------------------+ @@ -3196,10 +3204,10 @@ inline void ppc4xx_ibm_ddr2_register_dump(void) #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT)) - PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS); - PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS); - PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS); - PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS); + PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS); + PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS); + PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS); + PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS); #endif /* (defined(CONFIG_440SP) || ... */ #if defined(CONFIG_405EX) PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR); diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index 99b8e2f..4b5d636 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -87,6 +87,20 @@ DECLARE_GLOBAL_DATA_PTR; */ int __pci_pre_init(struct pci_controller *hose) { +#if defined (CONFIG_405EP) + /* + * Enable the internal PCI arbiter by default. + * + * On 405EP CPUs the internal arbiter can be controlled + * by the I2C strapping EEPROM. If you want to do so + * or if you want to disable the arbiter pci_pre_init() + * must be reimplemented without enabling the arbiter. + * The arbiter is enabled in this place because of + * compatibility reasons. + */ + mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_ARBIT_EN); +#endif /* CONFIG_405EP */ + return 1; } int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init"))); @@ -99,6 +113,19 @@ ushort pmc405_pci_subsys_deviceid(void); /*#define DEBUG*/ +int __is_pci_host(struct pci_controller *hose) +{ +#if defined(CONFIG_405GP) + if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + return 1; +#elif defined (CONFIG_405EP) + if (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN) + return 1; +#endif + return 0; +} +int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host"))); + /*-----------------------------------------------------------------------------+ * pci_init. Initializes the 405GP PCI Configuration regs. *-----------------------------------------------------------------------------*/ @@ -270,7 +297,7 @@ void pci_405gp_init(struct pci_controller *hose) */ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID); #ifdef CONFIG_CPCI405 - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + if (is_pci_host(hose)) pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); else pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2); @@ -295,7 +322,7 @@ void pci_405gp_init(struct pci_controller *hose) #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER) #if (CONFIG_PCI_HOST == PCI_HOST_AUTO) - if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || + if (is_pci_host(hose) || (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) #endif { @@ -310,8 +337,15 @@ void pci_405gp_init(struct pci_controller *hose) } #endif -#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */ - pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */ +#if defined(CONFIG_405EP) + /* + * on ppc405ep vendor/device id is not set + * The user manual says 0x1014 (IBM) / 0x0156 (405GP!) + * are the correct values. + */ + pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM); + pci_write_config_word(PCIDEVID_405GP, + PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP); #endif /* @@ -325,7 +359,7 @@ void pci_405gp_init(struct pci_controller *hose) * Scan the PCI bus and configure devices found. *--------------------------------------------------------------------------*/ #if (CONFIG_PCI_HOST == PCI_HOST_AUTO) - if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || + if (is_pci_host(hose) || (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) #endif { diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 06f44ad..fb3837c 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -54,6 +54,7 @@ int __get_cpu_num(void) } int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num"))); +#if defined(CONFIG_PCI) #if defined(CONFIG_405GP) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) @@ -76,6 +77,7 @@ static int pci_async_enabled(void) #endif } #endif +#endif /* CONFIG_PCI */ #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \ !defined(CONFIG_405) && !defined(CONFIG_405EX) diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 577d33f..bbd795d 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -174,11 +174,6 @@ cpu_init_f (void) * Set EMAC noise filter bits */ mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); - - /* - * Enable the internal PCI arbiter - */ - mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); #endif /* CONFIG_405EP */ #if defined(CONFIG_SYS_4xx_GPIO_TABLE) diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index ac96fc2..582c781 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -2021,6 +2021,7 @@ pci_wait: ! Output r3 = none !----------------------------------------------------------------------------- */ + .globl pll_write pll_write: mfdcr r5, CPC0_UCR andis. r5,r5,0xFFFF diff --git a/cpu/ppc4xx/uic.c b/cpu/ppc4xx/uic.c index a95d1cb..d298b31 100644 --- a/cpu/ppc4xx/uic.c +++ b/cpu/ppc4xx/uic.c @@ -164,7 +164,7 @@ void pic_irq_enable(unsigned int vec) else if (vec >= 96) mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec)); - debug("Install interrupt for vector %d ==> %p\n", vec, handler); + debug("Install interrupt vector %d\n", vec); } void pic_irq_disable(unsigned int vec) diff --git a/cpu/sh2/u-boot.lds b/cpu/sh2/u-boot.lds new file mode 100644 index 0000000..6db5a00 --- /dev/null +++ b/cpu/sh2/u-boot.lds @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2008 Nobuhiro Iwamatsu + * Copyright (C) 2008 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * entry and reloct_dst will be provided via ldflags + */ + . = .; + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh2/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/cpu/sh3/u-boot.lds b/cpu/sh3/u-boot.lds new file mode 100644 index 0000000..1e55b83 --- /dev/null +++ b/cpu/sh3/u-boot.lds @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2007 + * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2008 + * Mark Jonas <mark.jonas@de.bosch.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * entry and reloct_dst will be provided via ldflags + */ + . = .; + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh3/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/cpu/sh4/u-boot.lds b/cpu/sh4/u-boot.lds new file mode 100644 index 0000000..bff9f43 --- /dev/null +++ b/cpu/sh4/u-boot.lds @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2008-2009 + * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * entry and reloct_dst will be provided via ldflags + */ + . = .; + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss (NOLOAD) : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} |