summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mcf5227x/start.S1
-rw-r--r--cpu/mcf523x/start.S1
-rw-r--r--cpu/mcf52x2/config.mk4
-rw-r--r--cpu/mcf52x2/cpu.c66
-rw-r--r--cpu/mcf52x2/cpu_init.c111
-rw-r--r--cpu/mcf52x2/interrupts.c4
-rw-r--r--cpu/mcf52x2/speed.c12
-rw-r--r--cpu/mcf52x2/start.S65
-rw-r--r--cpu/mcf532x/start.S1
-rw-r--r--cpu/mcf5445x/Makefile2
-rw-r--r--cpu/mcf5445x/dspi.c73
-rw-r--r--cpu/mcf5445x/start.S1
-rw-r--r--cpu/mcf547x_8x/start.S1
13 files changed, 305 insertions, 37 deletions
diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S
index 0e2db12..1b47c97 100644
--- a/cpu/mcf5227x/start.S
+++ b/cpu/mcf5227x/start.S
@@ -354,3 +354,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S
index 2bd603d..ad04c09 100644
--- a/cpu/mcf523x/start.S
+++ b/cpu/mcf523x/start.S
@@ -338,3 +338,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk
index c3899c5..650e340 100644
--- a/cpu/mcf52x2/config.mk
+++ b/cpu/mcf52x2/config.mk
@@ -30,6 +30,7 @@ is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
+is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
@@ -47,6 +48,9 @@ endif
ifneq (,$(findstring CONFIG_M5272,$(is5272)))
PLATFORM_CPPFLAGS += -mcpu=5272
endif
+ifneq (,$(findstring CONFIG_M5275,$(is5275)))
+PLATFORM_CPPFLAGS += -mcpu=5275
+endif
ifneq (,$(findstring CONFIG_M5282,$(is5282)))
PLATFORM_CPPFLAGS += -mcpu=5282
endif
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index 71ea408..d5d3d33 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -6,6 +6,9 @@
* (C) Copyright 2005
* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
*
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -180,6 +183,69 @@ int watchdog_init(void)
#endif /* #ifdef CONFIG_M5272 */
+#ifdef CONFIG_M5275
+int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+
+ udelay(1000);
+
+ rcm->rcr = RCM_RCR_SOFTRST;
+
+ /* we don't return! */
+ return 0;
+};
+
+int checkcpu(void)
+{
+ char buf[32];
+
+ printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
+ strmhz(buf, CFG_CLK));
+ return 0;
+};
+
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdt->wsr = 0x5555;
+ wdt->wsr = 0xAAAA;
+}
+
+int watchdog_disable(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+ wdt->wsr = 0x5555; /* reset watchdog counter */
+ wdt->wsr = 0xAAAA;
+ wdt->wcr = 0; /* disable watchdog timer */
+
+ puts("WATCHDOG:disabled\n");
+ return (0);
+}
+
+int watchdog_init(void)
+{
+ volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+ wdt->wcr = 0; /* disable watchdog */
+
+ /* set timeout and enable watchdog */
+ wdt->wmr =
+ ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
+ wdt->wsr = 0x5555; /* reset watchdog counter */
+ wdt->wsr = 0xAAAA;
+
+ puts("WATCHDOG:enabled\n");
+ return (0);
+}
+#endif /* #ifdef CONFIG_WATCHDOG */
+
+#endif /* #ifdef CONFIG_M5275 */
+
#ifdef CONFIG_M5282
int checkcpu(void)
{
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 458b85e..207a37e 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -10,6 +10,9 @@
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -245,6 +248,114 @@ void uart_port_conf(void)
}
#endif /* #if defined(CONFIG_M5272) */
+#if defined(CONFIG_M5275)
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ /* if we come from RAM we assume the CPU is
+ * already initialized.
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+ volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
+ volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+ volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
+
+ /* Kill watchdog so we can initialize the PLL */
+ wdog_reg->wcr = 0;
+
+ /* Memory Controller: */
+ /* Flash */
+ csctrl_reg->ar0 = CFG_AR0_PRELIM;
+ csctrl_reg->cr0 = CFG_CR0_PRELIM;
+ csctrl_reg->mr0 = CFG_MR0_PRELIM;
+
+#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
+ csctrl_reg->ar1 = CFG_AR1_PRELIM;
+ csctrl_reg->cr1 = CFG_CR1_PRELIM;
+ csctrl_reg->mr1 = CFG_MR1_PRELIM;
+#endif
+
+#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
+ csctrl_reg->ar2 = CFG_AR2_PRELIM;
+ csctrl_reg->cr2 = CFG_CR2_PRELIM;
+ csctrl_reg->mr2 = CFG_MR2_PRELIM;
+#endif
+
+#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
+ csctrl_reg->ar3 = CFG_AR3_PRELIM;
+ csctrl_reg->cr3 = CFG_CR3_PRELIM;
+ csctrl_reg->mr3 = CFG_MR3_PRELIM;
+#endif
+
+#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
+ csctrl_reg->ar4 = CFG_AR4_PRELIM;
+ csctrl_reg->cr4 = CFG_CR4_PRELIM;
+ csctrl_reg->mr4 = CFG_MR4_PRELIM;
+#endif
+
+#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
+ csctrl_reg->ar5 = CFG_AR5_PRELIM;
+ csctrl_reg->cr5 = CFG_CR5_PRELIM;
+ csctrl_reg->mr5 = CFG_MR5_PRELIM;
+#endif
+
+#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
+ csctrl_reg->ar6 = CFG_AR6_PRELIM;
+ csctrl_reg->cr6 = CFG_CR6_PRELIM;
+ csctrl_reg->mr6 = CFG_MR6_PRELIM;
+#endif
+
+#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
+ csctrl_reg->ar7 = CFG_AR7_PRELIM;
+ csctrl_reg->cr7 = CFG_CR7_PRELIM;
+ csctrl_reg->mr7 = CFG_MR7_PRELIM;
+#endif
+
+#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
+
+#ifdef CONFIG_FSL_I2C
+ gpio_reg->par_feci2c = 0x000F;
+#endif
+
+ /* enable instruction cache now */
+ icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ gpio->par_uart |= UART0_ENABLE_MASK;
+ break;
+ case 1:
+ gpio->par_uart |= UART1_ENABLE_MASK;
+ break;
+ case 2:
+ gpio->par_uart |= UART2_ENABLE_MASK;
+ break;
+ }
+}
+#endif /* #if defined(CONFIG_M5275) */
+
#if defined(CONFIG_M5282)
/*
* Breath some life into the CPU...
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c
index 9167cec..b8fb7bb 100644
--- a/cpu/mcf52x2/interrupts.c
+++ b/cpu/mcf52x2/interrupts.c
@@ -59,7 +59,7 @@ void dtimer_intr_setup(void)
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
int interrupt_init(void)
{
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
@@ -81,7 +81,7 @@ void dtimer_intr_setup(void)
intp->imrl0 &= ~CFG_TMRINTR_MASK;
}
#endif /* CONFIG_MCFTMR */
-#endif /* CONFIG_M5282 | CONFIG_M5271 */
+#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
int interrupt_init(void)
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index bc1e200..85a5c4d 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -64,8 +64,18 @@ int get_clocks (void)
#endif /* CONFIG_M5249 || CONFIG_M5253 */
+#if defined(CONFIG_M5275)
+ volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+
+ /* Setup PLL */
+ pll->syncr = 0x01080000;
+ while (!(pll->synsr & FMPLL_SYNSR_LOCK));
+ pll->syncr = 0x01000000;
+ while (!(pll->synsr & FMPLL_SYNSR_LOCK));
+#endif
+
gd->cpu_clk = CFG_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
#else
gd->bus_clk = gd->cpu_clk;
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index 260a09a..2bc0df3 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -56,9 +56,7 @@
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_R5200)
-.long 0x400
-#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
.long _start - TEXT_BASE
#else
.long _START
@@ -160,7 +158,7 @@ _copy_flash:
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
- movec %d0, %RAMBAR0
+ movec %d0, %FLASHBAR
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
nop
@@ -168,7 +166,7 @@ _after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
- movec %d0, %RAMBAR0
+ movec %d0, %RAMBAR1
#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
#endif
@@ -185,16 +183,15 @@ _after_flashbar_copy:
movec %d0, %VBR
#endif
-#ifdef CONFIG_R5200
- move.l #(_flash_setup-CFG_FLASH_BASE), %a0
- move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1
- move.l #(CFG_INIT_RAM_ADDR), %a2
-_copy_flash:
- move.l (%a0)+, (%a2)+
- cmp.l %a0, %a1
- bgt.s _copy_flash
- jmp CFG_INIT_RAM_ADDR
-_after_flash_copy:
+#ifdef CONFIG_M5275
+ /* Initialize IPSBAR */
+ move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
+ move.l %d0, 0x40000000
+/* movec %d0, %MBAR */
+
+ /* Initialize RAMBAR: locate SRAM and validate it */
+ move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
+ movec %d0, %RAMBAR1
#endif
#if 0
@@ -219,24 +216,6 @@ _after_flash_copy:
/*------------------------------------------------------------------------------*/
-#ifdef CONFIG_R5200
-_flash_setup:
- /* CSAR0 */
- move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0
- move.w %d0, 0x40000080
-
- /* CSCR0 */
- move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */
- move.w %d0, 0x4000008A
-
- /* CSMR0 */
- move.l #0x001f0001, %d0 /* 2 MB, valid */
- move.l %d0, 0x40000084
-
- jmp _after_flash_copy.L
-_flash_setup_end:
-#endif
-
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
@@ -394,6 +373,25 @@ icache_enable:
rts
#endif
+#if defined(CONFIG_M5275)
+/*
+ * Instruction cache only
+ */
+ .globl icache_enable
+icache_enable:
+ move.l #0x01400000, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #0x0000c000, %d0 /* Setup SDRAM caching */
+ movec %d0, %ACR0 /* Enable cache */
+ move.l #0x00000000, %d0 /* No other caching */
+ movec %d0, %ACR1 /* Enable cache */
+ move.l #0x80400100, %d0 /* Setup cache mask */
+ movec %d0, %CACR /* Enable cache */
+ moveq #1, %d0
+ move.l %d0, icache_state
+ rts
+#endif
+
#ifdef CONFIG_M5282
.globl icache_enable
icache_enable:
@@ -478,3 +476,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index 61be2ea..a524f70 100644
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -333,3 +333,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf5445x/Makefile b/cpu/mcf5445x/Makefile
index 26ec298..a549fdd 100644
--- a/cpu/mcf5445x/Makefile
+++ b/cpu/mcf5445x/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
-COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o
+COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c
new file mode 100644
index 0000000..44d8505
--- /dev/null
+++ b/cpu/mcf5445x/dspi.c
@@ -0,0 +1,73 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+
+#if defined(CONFIG_CF_DSPI)
+#include <asm/immap.h>
+void dspi_init(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 |
+ GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 |
+ GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+ GPIO_PAR_DSPI_SCK_SCK;
+
+ dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
+ DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
+ DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
+ DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
+
+ dspi->dctar0 = DSPI_DCTAR_TRSZ(7) | DSPI_DCTAR_CPOL | DSPI_DCTAR_CPHA |
+ DSPI_DCTAR_PCSSCK_1CLK | DSPI_DCTAR_PASC(0) |
+ DSPI_DCTAR_PDT(0) | DSPI_DCTAR_CSSCK(0) |
+ DSPI_DCTAR_ASC(0) | DSPI_DCTAR_PBR(0) |
+ DSPI_DCTAR_DT(1) | DSPI_DCTAR_BR(1);
+}
+
+void dspi_tx(int chipsel, u8 attrib, u16 data)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ while ((dspi->dsr & 0x0000F000) >= 4) ;
+
+ dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
+}
+
+u16 dspi_rx(void)
+{
+ volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+ while ((dspi->dsr & 0x000000F0) == 0) ;
+
+ return (dspi->drfr & 0xFFFF);
+}
+
+#endif /* CONFIG_HARD_SPI */
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index d64c5af..0c5194a 100644
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -379,3 +379,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S
index 442665f..c12d7a0 100644
--- a/cpu/mcf547x_8x/start.S
+++ b/cpu/mcf547x_8x/start.S
@@ -359,3 +359,4 @@ version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
generated by cgit v1.1 at 2024-12-19 15:24:29 +0000