summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'cpu')
-rw-r--r--cpu/arm1176/cpu.c2
-rw-r--r--cpu/arm1176/start.S4
-rw-r--r--cpu/arm920t/ep93xx/timer.c62
-rw-r--r--cpu/arm926ejs/at91/clock.c3
-rw-r--r--cpu/arm926ejs/nomadik/timer.c15
-rw-r--r--cpu/arm_cortexa8/s5pc1xx/Makefile2
-rw-r--r--cpu/arm_cortexa8/s5pc1xx/clock.c7
-rw-r--r--cpu/arm_cortexa8/s5pc1xx/gpio.c143
-rw-r--r--cpu/arm_cortexa8/s5pc1xx/sromc.c53
9 files changed, 248 insertions, 43 deletions
diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c
index 2c0014f..befa0cd 100644
--- a/cpu/arm1176/cpu.c
+++ b/cpu/arm1176/cpu.c
@@ -33,7 +33,9 @@
#include <common.h>
#include <command.h>
+#ifdef CONFIG_S3C64XX
#include <asm/arch/s3c6400.h>
+#endif
#include <asm/system.h>
static void cache_flush (void);
diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S
index 68a356d..e2b6c9b 100644
--- a/cpu/arm1176/start.S
+++ b/cpu/arm1176/start.S
@@ -35,7 +35,9 @@
#ifdef CONFIG_ENABLE_MMU
#include <asm/proc/domain.h>
#endif
+#ifdef CONFIG_S3C64XX
#include <asm/arch/s3c6400.h>
+#endif
#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
@@ -190,10 +192,12 @@ mmu_disable:
#endif
mmu_disable_phys:
+#ifdef CONFIG_S3C64XX
/* Peri port setup */
ldr r0, =0x70000000
orr r0, r0, #0x13
mcr p15,0,r0,c15,c2,4 @ 256M (0x70000000 - 0x7fffffff)
+#endif
/*
* Go setup Memory and board specific bits prior to relocation.
diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c
index 31304b7..4a0ce4d 100644
--- a/cpu/arm920t/ep93xx/timer.c
+++ b/cpu/arm920t/ep93xx/timer.c
@@ -1,8 +1,7 @@
/*
* Cirrus Logic EP93xx timer support.
*
- * Copyright (C) 2009, 2010
- * Matthias Kaehlcke <matthias@kaehlcke.net>
+ * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2004, 2005
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
@@ -42,17 +41,9 @@
static struct ep93xx_timer
{
unsigned long long ticks;
- unsigned long last_update;
+ unsigned long last_read;
} timer;
-static inline unsigned long clk_to_systicks(unsigned long long clk_ticks)
-{
- unsigned long long sys_ticks = (clk_ticks * CONFIG_SYS_HZ);
- do_div(sys_ticks, TIMER_FREQ);
-
- return (unsigned long)sys_ticks;
-}
-
static inline unsigned long long usecs_to_ticks(unsigned long usecs)
{
unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
@@ -61,11 +52,18 @@ static inline unsigned long long usecs_to_ticks(unsigned long usecs)
return ticks;
}
-static inline unsigned long read_timer(void)
+static inline void read_timer(void)
{
- struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
+ struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+ const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
+
+ if (now >= timer.last_read)
+ timer.ticks += now - timer.last_read;
+ else
+ /* an overflow occurred */
+ timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
- return TIMER_MAX_VAL - readl(&timer->timer3.value);
+ timer.last_read = now;
}
/*
@@ -73,17 +71,14 @@ static inline unsigned long read_timer(void)
*/
unsigned long long get_ticks(void)
{
- const unsigned long now = read_timer();
+ unsigned long long sys_ticks;
- if (now >= timer.last_update)
- timer.ticks += now - timer.last_update;
- else
- /* an overflow occurred */
- timer.ticks += TIMER_MAX_VAL - timer.last_update + now;
+ read_timer();
- timer.last_update = now;
+ sys_ticks = timer.ticks * CONFIG_SYS_HZ;
+ do_div(sys_ticks, TIMER_FREQ);
- return clk_to_systicks(timer.ticks);
+ return sys_ticks;
}
unsigned long get_timer_masked(void)
@@ -98,7 +93,7 @@ unsigned long get_timer(unsigned long base)
void reset_timer_masked(void)
{
- timer.last_update = read_timer();
+ read_timer();
timer.ticks = 0;
}
@@ -109,28 +104,29 @@ void reset_timer(void)
void __udelay(unsigned long usec)
{
- /* read the timer and update timer.ticks */
- get_ticks();
+ unsigned long long target;
+
+ read_timer();
- const unsigned long long target = timer.ticks + usecs_to_ticks(usec);
+ target = timer.ticks + usecs_to_ticks(usec);
while (timer.ticks < target)
- get_ticks();
+ read_timer();
}
int timer_init(void)
{
- struct timer_regs *timer = (struct timer_regs *)TIMER_BASE;
+ struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
- /* use timer 3 with 508KHz and free running */
- writel(TIMER_CLKSEL, &timer->timer3.control);
+ /* use timer 3 with 508KHz and free running, not enabled now */
+ writel(TIMER_CLKSEL, &timer_regs->timer3.control);
- /* set initial timer value 3 */
- writel(TIMER_MAX_VAL, &timer->timer3.load);
+ /* set initial timer value */
+ writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
/* Enable the timer */
writel(TIMER_ENABLE | TIMER_CLKSEL,
- &timer->timer3.control);
+ &timer_regs->timer3.control);
reset_timer_masked();
diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c
index b06d760..ecf91f5 100644
--- a/cpu/arm926ejs/at91/clock.c
+++ b/cpu/arm926ejs/at91/clock.c
@@ -203,7 +203,8 @@ int at91_clock_init(unsigned long main_clock)
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
- mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3
+ mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+ (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
? freq / 3
: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#else
diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c
index 047b9e3..1d98ef3 100644
--- a/cpu/arm926ejs/nomadik/timer.c
+++ b/cpu/arm926ejs/nomadik/timer.c
@@ -34,8 +34,8 @@
#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
-/* macro to read the 32 bit timer: since it decrements, we invert read value */
-#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
+/* macro to read the decrementing 32 bit timer as an increasing count */
+#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
/* Configure a free-running, auto-wrap counter with no prescaler */
int timer_init(void)
@@ -49,7 +49,16 @@ int timer_init(void)
/* Restart counting from 0 */
void reset_timer(void)
{
- writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */
+ ulong val;
+ writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
+ /*
+ * The load-register isn't really immediate: it changes on clock
+ * edges, so we must wait for our newly-written value to appear.
+ * Since we might miss reading 0, wait for any change in value.
+ */
+ val = READ_TIMER();
+ while (READ_TIMER() == val)
+ ;
}
/* Return how many HZ passed since "base" */
diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile
index 4f922e6..01c93fe 100644
--- a/cpu/arm_cortexa8/s5pc1xx/Makefile
+++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
@@ -33,6 +33,8 @@ SOBJS += reset.o
COBJS += clock.o
COBJS += cpu_info.o
+COBJS += gpio.o
+COBJS += sromc.o
COBJS += timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/cpu/arm_cortexa8/s5pc1xx/clock.c
index a9e78dd..19619f9 100644
--- a/cpu/arm_cortexa8/s5pc1xx/clock.c
+++ b/cpu/arm_cortexa8/s5pc1xx/clock.c
@@ -25,12 +25,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-
-#define APLL 0
-#define MPLL 1
-#define EPLL 2
-#define HPLL 3
-#define VPLL 4
+#include <asm/arch/clk.h>
#define CLK_M 0
#define CLK_D 1
diff --git a/cpu/arm_cortexa8/s5pc1xx/gpio.c b/cpu/arm_cortexa8/s5pc1xx/gpio.c
new file mode 100644
index 0000000..a97244b
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/gpio.c
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+#define CON_MASK(x) (0xf << ((x) << 2))
+#define CON_SFR(x, v) ((v) << ((x) << 2))
+
+#define DAT_MASK(x) (0x1 << (x))
+#define DAT_SET(x) (0x1 << (x))
+
+#define PULL_MASK(x) (0x3 << ((x) << 1))
+#define PULL_MODE(x, v) ((v) << ((x) << 1))
+
+#define DRV_MASK(x) (0x3 << ((x) << 1))
+#define DRV_SET(x, m) ((m) << ((x) << 1))
+#define RATE_MASK(x) (0x1 << (x + 16))
+#define RATE_SET(x) (0x1 << (x + 16))
+
+void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg)
+{
+ unsigned int value;
+
+ value = readl(&bank->con);
+ value &= ~CON_MASK(gpio);
+ value |= CON_SFR(gpio, cfg);
+ writel(value, &bank->con);
+}
+
+void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en)
+{
+ unsigned int value;
+
+ gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
+
+ value = readl(&bank->dat);
+ value &= ~DAT_MASK(gpio);
+ if (en)
+ value |= DAT_SET(gpio);
+ writel(value, &bank->dat);
+}
+
+void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio)
+{
+ gpio_cfg_pin(bank, gpio, GPIO_INPUT);
+}
+
+void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en)
+{
+ unsigned int value;
+
+ value = readl(&bank->dat);
+ value &= ~DAT_MASK(gpio);
+ if (en)
+ value |= DAT_SET(gpio);
+ writel(value, &bank->dat);
+}
+
+unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio)
+{
+ unsigned int value;
+
+ value = readl(&bank->dat);
+ return !!(value & DAT_MASK(gpio));
+}
+
+void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+ unsigned int value;
+
+ value = readl(&bank->pull);
+ value &= ~PULL_MASK(gpio);
+
+ switch (mode) {
+ case GPIO_PULL_DOWN:
+ case GPIO_PULL_UP:
+ value |= PULL_MODE(gpio, mode);
+ break;
+ default:
+ return;
+ }
+
+ writel(value, &bank->pull);
+}
+
+void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+ unsigned int value;
+
+ value = readl(&bank->drv);
+ value &= ~DRV_MASK(gpio);
+
+ switch (mode) {
+ case GPIO_DRV_1X:
+ case GPIO_DRV_2X:
+ case GPIO_DRV_3X:
+ case GPIO_DRV_4X:
+ value |= DRV_SET(gpio, mode);
+ break;
+ default:
+ return;
+ }
+
+ writel(value, &bank->drv);
+}
+
+void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+ unsigned int value;
+
+ value = readl(&bank->drv);
+ value &= ~RATE_MASK(gpio);
+
+ switch (mode) {
+ case GPIO_DRV_FAST:
+ case GPIO_DRV_SLOW:
+ value |= RATE_SET(gpio);
+ break;
+ default:
+ return;
+ }
+
+ writel(value, &bank->drv);
+}
diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c b/cpu/arm_cortexa8/s5pc1xx/sromc.c
new file mode 100644
index 0000000..380be81
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/smc.h>
+
+/*
+ * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank - SROM Bank 0 to 5
+ * smc_bw_conf - SMC Band witdh reg configuration value
+ * smc_bc_conf - SMC Bank Control reg configuration value
+ */
+void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
+{
+ u32 tmp;
+ struct s5pc1xx_smc *srom;
+
+ if (cpu_is_s5pc100())
+ srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE;
+ else
+ srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE;
+
+ /* Configure SMC_BW register to handle proper SROMC bank */
+ tmp = srom->bw;
+ tmp &= ~(0xF << (srom_bank * 4));
+ tmp |= smc_bw_conf;
+ srom->bw = tmp;
+
+ /* Configure SMC_BC register */
+ srom->bc[srom_bank] = smc_bc_conf;
+}
generated by cgit v1.1 at 2024-12-02 22:56:27 +0000