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-rw-r--r--cpu/mpc85xx/cpu.c7
-rw-r--r--cpu/mpc85xx/fdt.c15
-rw-r--r--cpu/mpc85xx/pci.c32
-rw-r--r--cpu/mpc85xx/speed.c10
-rw-r--r--cpu/mpc8xxx/ddr/ctrl_regs.c48
-rw-r--r--cpu/mpc8xxx/ddr/options.c2
6 files changed, 78 insertions, 36 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 15ba7f1..a34e251 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -90,6 +90,7 @@ int checkcpu (void)
#else
u32 ddr_ratio = 0;
#endif
+ int i;
svr = get_svr();
ver = SVR_SOC_VER(svr);
@@ -141,8 +142,10 @@ int checkcpu (void)
get_sys_info(&sysinfo);
- puts("Clock Configuration:\n");
- printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
+ puts("Clock Configuration:\n ");
+ for (i = 0; i < CONFIG_NUM_CPUS; i++)
+ printf("CPU%d:%-4s MHz, ",
+ i,strmhz(buf1, sysinfo.freqProcessor[i]));
printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
switch (ddr_ratio) {
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 69fab99..1fae47c 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -213,6 +213,10 @@ void fdt_add_enet_stashing(void *fdt)
void ft_cpu_setup(void *blob, bd_t *bd)
{
+ int off;
+ int val;
+ sys_info_t sysinfo;
+
/* delete crypto node if not on an E-processor */
if (!IS_E_PROCESSOR(get_svr()))
fdt_fixup_crypto_node(blob, 0);
@@ -228,8 +232,15 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"timebase-frequency", bd->bi_busfreq / 8, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "clock-frequency", bd->bi_intfreq, 1);
+ get_sys_info(&sysinfo);
+ off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
+ while (off != -FDT_ERR_NOTFOUND) {
+ u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
+ val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
+ fdt_setprop(blob, off, "clock-frequency", &val, 4);
+ off = fdt_node_offset_by_prop_value(blob, off, "device_type",
+ "cpu", 4);
+ }
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index 787c6eb..fedf1a5 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -31,6 +31,22 @@
#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)
+#ifndef CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
+#endif
+
+#ifndef CONFIG_SYS_PCI1_IO_BUS
+#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
+#endif
+
+#ifndef CONFIG_SYS_PCI2_MEM_BUS
+#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
+#endif
+
+#ifndef CONFIG_SYS_PCI2_IO_BUS
+#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
+#endif
+
static struct pci_controller *pci_hose;
void
@@ -80,14 +96,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
}
- pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & 0x000fffff;
+ pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
pcix->potear1 = 0x00000000;
pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
pcix->powbear1 = 0x00000000;
pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
- pcix->potar2 = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff;
+ pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
pcix->potear2 = 0x00000000;
pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
pcix->powbear2 = 0x00000000;
@@ -105,13 +121,13 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pcix->piwar3 = 0;
pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
@@ -165,14 +181,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
*/
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & 0x000fffff;
+ pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
pcix2->potear1 = 0x00000000;
pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
pcix2->powbear1 = 0x00000000;
pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
- pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff;
+ pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
pcix2->potear2 = 0x00000000;
pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
pcix2->powbear2 = 0x00000000;
@@ -190,13 +206,13 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pcix2->piwar3 = 0;
pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI2_MEM_BASE,
+ CONFIG_SYS_PCI2_MEM_BUS,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI2_IO_BASE,
+ CONFIG_SYS_PCI2_IO_BUS,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 0d55228..b0f47e0 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -39,17 +39,19 @@ void get_sys_info (sys_info_t * sysInfo)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint plat_ratio,e500_ratio,half_freqSystemBus;
uint lcrr_div;
+ int i;
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
- e500_ratio = (gur->porpllsr) & 0x003f0000;
- e500_ratio >>= 16;
/* Divide before multiply to avoid integer
* overflow for processor speeds above 2GHz */
half_freqSystemBus = sysInfo->freqSystemBus/2;
- sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
+ for (i = 0; i < CONFIG_NUM_CPUS; i++) {
+ e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
+ sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
+ }
/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
sysInfo->freqDDRBus = sysInfo->freqSystemBus;
@@ -105,7 +107,7 @@ int get_clocks (void)
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
get_sys_info (&sys_info);
- gd->cpu_clk = sys_info.freqProcessor;
+ gd->cpu_clk = sys_info.freqProcessor[0];
gd->bus_clk = sys_info.freqSystemBus;
gd->mem_clk = sys_info.freqDDRBus;
gd->lbc_clk = sys_info.freqLocalBus;
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 1783e92..292980d 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -167,7 +167,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
| ((trrt_mclk & 0x3) << 26) /* RRT */
| ((twwt_mclk & 0x3) << 24) /* WWT */
| ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
- | ((pre_pd_exit_mclk & 0x7) << 16) /* PRE_PD_EXIT */
+ | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
| ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
| ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
);
@@ -185,10 +185,14 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
unsigned int cntl_adj = 0; /* Control Adjust */
+ /* If the tRAS > 19 MCLK, we use the ext mode */
+ if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
+ ext_acttopre = 1;
+
ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
ddr->timing_cfg_3 = (0
| ((ext_acttopre & 0x1) << 24)
- | ((ext_refrec & 0x7) << 16)
+ | ((ext_refrec & 0xF) << 16)
| ((ext_caslat & 0x1) << 12)
| ((cntl_adj & 0x7) << 0)
);
@@ -251,12 +255,12 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
ddr->timing_cfg_1 = (0
- | ((pretoact_mclk & 0x07) << 28)
+ | ((pretoact_mclk & 0x0F) << 28)
| ((acttopre_mclk & 0x0F) << 24)
- | ((acttorw_mclk & 0x7) << 20)
+ | ((acttorw_mclk & 0xF) << 20)
| ((caslat_ctrl & 0xF) << 16)
| ((refrec_ctrl & 0xF) << 12)
- | ((wrrec_mclk & 0x07) << 8)
+ | ((wrrec_mclk & 0x0F) << 8)
| ((acttoact_mclk & 0x07) << 4)
| ((wrtord_mclk & 0x07) << 0)
);
@@ -309,13 +313,13 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
ddr->timing_cfg_2 = (0
- | ((add_lat_mclk & 0x7) << 28)
+ | ((add_lat_mclk & 0xf) << 28)
| ((cpo & 0x1f) << 23)
- | ((wr_lat & 0x7) << 19)
+ | ((wr_lat & 0xf) << 19)
| ((rd_to_pre & 0x7) << 13)
| ((wr_data_delay & 0x7) << 10)
| ((cke_pls & 0x7) << 6)
- | ((four_act & 0x1f) << 0)
+ | ((four_act & 0x3f) << 0)
);
debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
}
@@ -332,7 +336,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
unsigned int sdram_type; /* Type of SDRAM */
unsigned int dyn_pwr; /* Dynamic power management mode */
unsigned int dbw; /* DRAM dta bus width */
- unsigned int eight_be; /* 8-beat burst enable */
+ unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
unsigned int ncap = 0; /* Non-concurrent auto-precharge */
unsigned int threeT_en; /* Enable 3T timing */
unsigned int twoT_en; /* Enable 2T timing */
@@ -359,7 +363,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
dyn_pwr = popts->dynamic_power;
dbw = popts->data_bus_width;
- eight_be = 0; /* always 0 for DDR2 */
+ /* DDR3 must use 8-beat bursts when using 32-bit bus mode */
+ if ((sdram_type == SDRAM_TYPE_DDR3) && (dbw == 0x1))
+ eight_be = 1;
threeT_en = popts->threeT_en;
twoT_en = popts->twoT_en;
ba_intlv_ctl = popts->ba_intlv_ctl;
@@ -691,10 +697,10 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
unsigned int wodt_off = 0; /* Write to ODT off */
ddr->timing_cfg_5 = (0
- | ((rodt_on & 0xf) << 24)
- | ((rodt_off & 0xf) << 20)
- | ((wodt_on & 0xf) << 12)
- | ((wodt_off & 0xf) << 8)
+ | ((rodt_on & 0x1f) << 24)
+ | ((rodt_off & 0x7) << 20)
+ | ((wodt_on & 0x1f) << 12)
+ | ((wodt_off & 0x7) << 8)
);
debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
}
@@ -744,15 +750,14 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr)
| ((wrlvl_dqsen & 0x7) << 16)
| ((wrlvl_smpl & 0xf) << 12)
| ((wrlvl_wlr & 0x7) << 8)
- | ((wrlvl_start & 0xF) << 0)
+ | ((wrlvl_start & 0x1F) << 0)
);
}
/* DDR Self Refresh Counter (DDR_SR_CNTR) */
-static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr)
+static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
{
- unsigned int sr_it = 0; /* Self Refresh Idle Threshold */
-
+ /* Self Refresh Idle Threshold */
ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
}
@@ -855,6 +860,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
unsigned int i;
unsigned int cas_latency;
unsigned int additive_latency;
+ unsigned int sr_it;
memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
@@ -876,6 +882,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
? popts->additive_latency_override_value
: common_dimm->additive_latency;
+ sr_it = (popts->auto_self_refresh_en)
+ ? popts->sr_it
+ : 0;
+
/* Chip Select Memory Bounds (CSn_BNDS) */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
phys_size_t sa = 0;
@@ -1036,7 +1046,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_ddr_wrlvl_cntl(ddr);
set_ddr_pd_cntl(ddr);
- set_ddr_sr_cntr(ddr);
+ set_ddr_sr_cntr(ddr, sr_it);
set_ddr_sdram_rcw_1(ddr);
set_ddr_sdram_rcw_2(ddr);
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index af7f73a..d4702d7 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -142,7 +142,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
* - number of components, number of active ranks
* - how much time you want to spend playing around
*/
- popts->twoT_en = 1;
+ popts->twoT_en = 0;
popts->threeT_en = 0;
/*
generated by cgit v1.1 at 2024-11-05 17:01:47 +0000