diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/bf533/flush.S | 4 | ||||
| -rw-r--r-- | cpu/bf533/start.S | 10 |
2 files changed, 7 insertions, 7 deletions
diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S index 4a6c64b..0512f3b 100644 --- a/cpu/bf533/flush.S +++ b/cpu/bf533/flush.S @@ -90,7 +90,7 @@ ENTRY(_icplb_flush) /* Save in extraction pattern for later deposit. */ R3.H = R4.L << 0; - + /* So: * R0 = Page start * R1 = Page length (actually, offset into size/prefix tables) @@ -264,7 +264,7 @@ ENTRY(_dcplb_flush) * (b) on whether address bit A[x] is set. x is determined * by DCBS in DMEM_CONTROL */ - + R2 = 0; /* Default to Bank A (Bank B would be 1)*/ P0.L = (DMEM_CONTROL & 0xFFFF); diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S index 3a31e2f..94556d6 100644 --- a/cpu/bf533/start.S +++ b/cpu/bf533/start.S @@ -82,7 +82,7 @@ _stext: SSYNC; /* As per HW reference manual DAG registers, - * DATA and Address resgister shall be zero'd + * DATA and Address resgister shall be zero'd * in initialization, after a reset state */ r1 = 0; /* Data registers zero'd */ @@ -99,7 +99,7 @@ _stext: p3 = 0; p4 = 0; p5 = 0; - + i0 = 0; /* DAG Registers zero'd */ i1 = 0; i2 = 0; @@ -150,7 +150,7 @@ no_soft_reset: r1 = 0; LSETUP(4,4) lc0 = p1; [ p0 ++ ] = r1; - + p0.h = hi(SIC_IWR); p0.l = lo(SIC_IWR); r0.l = 0x1; @@ -259,8 +259,8 @@ DMA: /* Set Destination DMAConfig = DMA Enable, Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; - -WAIT_DMA_DONE: + +WAIT_DMA_DONE: p0.h = hi(MDMA_D0_IRQ_STATUS); p0.l = lo(MDMA_D0_IRQ_STATUS); R0 = W[P0](Z); |