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-rw-r--r--cpu/mpc83xx/start.S12
-rw-r--r--cpu/mpc85xx/speed.c4
-rw-r--r--cpu/ppc4xx/44x_spd_ddr2.c10
3 files changed, 20 insertions, 6 deletions
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index 565cc39..cd566b2 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -167,6 +167,18 @@ boot_warm: /* time t 5 */
/* Initialise the E300 processor core */
/*------------------------------------------*/
+#ifdef CONFIG_NAND_SPL
+ /* The FCM begins execution after only the first page
+ * is loaded. Wait for the rest before branching
+ * to another flash page.
+ */
+ addi r7, r3, 0x50b0
+1: dcbi 0, r7
+ lwz r6, 0(r7)
+ andi. r6, r6, 1
+ beq 1b
+#endif
+
bl init_e300_core
#ifdef CONFIG_SYS_FLASHBOOT
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index d9f9a8c..1e0f483 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -102,9 +102,9 @@ int get_clocks (void)
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
*/
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
- gd->i2c1_clk = sys_info.freqSystemBus / 2;
- else
gd->i2c1_clk = sys_info.freqSystemBus / 3;
+ else
+ gd->i2c1_clk = sys_info.freqSystemBus / 2;
#else
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
gd->i2c1_clk = sys_info.freqSystemBus / 2;
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 30c2e44..4544b78 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -2261,10 +2261,12 @@ static void program_memory_queue(unsigned long *dimm_populated,
/*
* Set optimal value for Memory Queue HB/LL Configuration registers
*/
- mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
- SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
- mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
- SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+ mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
+ SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
+ SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
+ mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
+ SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
+ SDRAM_CONF1LL_RPLM);
mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
#endif
}