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-rw-r--r--cpu/arm1136/mx31/interrupts.c24
-rw-r--r--cpu/arm920t/at91rm9200/i2c.c10
-rw-r--r--cpu/arm920t/imx/interrupts.c2
-rw-r--r--cpu/arm920t/imx/serial.c56
-rw-r--r--cpu/arm920t/start.S6
-rw-r--r--cpu/arm926ejs/davinci/dp83848.c27
-rw-r--r--cpu/ppc4xx/sdram.c14
-rw-r--r--cpu/pxa/mmc.c4
8 files changed, 95 insertions, 48 deletions
diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c
index 21b77a5..6e08c71 100644
--- a/cpu/arm1136/mx31/interrupts.c
+++ b/cpu/arm1136/mx31/interrupts.c
@@ -38,6 +38,9 @@
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
#define GPTCR_TEN (1) /* Timer enable */
+static ulong timestamp;
+static ulong lastinc;
+
/* nothing really to do with interrupts, just starts up a counter. */
int interrupt_init (void)
{
@@ -54,14 +57,27 @@ int interrupt_init (void)
void reset_timer_masked (void)
{
- GPTCR = 0;
- GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */
+ /* reset time */
+ lastinc = GPTCNT; /* capture current incrementer value time */
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
}
ulong get_timer_masked (void)
{
- ulong val = GPTCNT;
- return val;
+ ulong now = GPTCNT; /* current tick value */
+
+ if (now >= lastinc) /* normal mode (non roll) */
+ /* move stamp forward with absolut diff ticks */
+ timestamp += (now - lastinc);
+ else /* we have rollover of incrementer */
+ timestamp += (0xFFFFFFFF - lastinc) + now;
+ lastinc = now;
+ return timestamp;
}
ulong get_timer (ulong base)
diff --git a/cpu/arm920t/at91rm9200/i2c.c b/cpu/arm920t/at91rm9200/i2c.c
index 826cea8..90f95df 100644
--- a/cpu/arm920t/at91rm9200/i2c.c
+++ b/cpu/arm920t/at91rm9200/i2c.c
@@ -203,4 +203,14 @@ void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
i2c_write(i2c_addr, reg, 1, &val, 1);
}
+int i2c_set_bus_speed(unsigned int speed)
+{
+ return -1;
+}
+
+unsigned int i2c_get_bus_speed(void)
+{
+ return CFG_I2C_SPEED;
+}
+
#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/arm920t/imx/interrupts.c b/cpu/arm920t/imx/interrupts.c
index 03ce06d..c61d3bc 100644
--- a/cpu/arm920t/imx/interrupts.c
+++ b/cpu/arm920t/imx/interrupts.c
@@ -60,7 +60,7 @@ void reset_timer (void)
ulong get_timer (ulong base)
{
- return get_timer_masked ();
+ return get_timer_masked() - base;
}
void set_timer (ulong t)
diff --git a/cpu/arm920t/imx/serial.c b/cpu/arm920t/imx/serial.c
index 6c56acb..85f1167 100644
--- a/cpu/arm920t/imx/serial.c
+++ b/cpu/arm920t/imx/serial.c
@@ -52,6 +52,8 @@ struct imx_serial {
volatile uint32_t uts;
};
+DECLARE_GLOBAL_DATA_PTR;
+
void serial_setbrg (void)
{
serial_init();
@@ -67,6 +69,9 @@ extern void imx_gpio_mode(int gpio_mode);
int serial_init (void)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
+ unsigned int ufcr_rfdiv;
+ unsigned int refclk;
+
#ifdef CONFIG_IMX_SERIAL1
imx_gpio_mode(PC11_PF_UART1_TXD);
imx_gpio_mode(PC12_PF_UART1_RXD);
@@ -95,11 +100,33 @@ int serial_init (void)
/* Configure FIFOs */
base->ufcr = 0xa81;
+ /* set the baud rate.
+ *
+ * baud * 16 x
+ * --------- = -
+ * refclk y
+ *
+ * x - 1 = UBIR
+ * y - 1 = UBMR
+ *
+ * each register is 16 bits wide. refclk max is 96 MHz
+ *
+ */
+
+ ufcr_rfdiv = ((base->ufcr) & UFCR_RFDIV) >> 7;
+ if (ufcr_rfdiv == 6)
+ ufcr_rfdiv = 7;
+ else
+ ufcr_rfdiv = 6 - ufcr_rfdiv;
+
+ refclk = get_PERCLK1();
+ refclk /= ufcr_rfdiv;
+
/* Set the numerator value minus one of the BRM ratio */
- base->ubir = (CONFIG_BAUDRATE / 100) - 1;
+ base->ubir = (gd->baudrate / 100) - 1;
/* Set the denominator value minus one of the BRM ratio */
- base->ubmr = 10000 - 1;
+ base->ubmr = (refclk/(16 * 100)) - 1;
/* Set to 8N1 */
base->ucr2 &= ~UCR2_PREN;
@@ -117,22 +144,21 @@ int serial_init (void)
/* Clear status flags */
base->usr2 |= USR2_ADET |
- USR2_DTRF |
- USR2_IDLE |
- USR2_IRINT |
- USR2_WAKE |
- USR2_RTSF |
- USR2_BRCD |
- USR2_ORE |
- USR2_RDR;
+ USR2_DTRF |
+ USR2_IDLE |
+ USR2_IRINT |
+ USR2_WAKE |
+ USR2_RTSF |
+ USR2_BRCD |
+ USR2_ORE;
/* Clear status flags */
base->usr1 |= USR1_PARITYERR |
- USR1_RTSD |
- USR1_ESCF |
- USR1_FRAMERR |
- USR1_AIRINT |
- USR1_AWAKE;
+ USR1_RTSD |
+ USR1_ESCF |
+ USR1_FRAMERR |
+ USR1_AIRINT |
+ USR1_AWAKE;
return (0);
}
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 62231f8..5d0fec6 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -315,7 +315,8 @@ cpu_init_crit:
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_STACKSIZE)
+ sub r2, r2, #(CFG_MALLOC_LEN)
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@@ -348,7 +349,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_STACKSIZE)
+ sub r13, r13, #(CFG_MALLOC_LEN)
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
diff --git a/cpu/arm926ejs/davinci/dp83848.c b/cpu/arm926ejs/davinci/dp83848.c
index 59f039b..c71c685 100644
--- a/cpu/arm926ejs/davinci/dp83848.c
+++ b/cpu/arm926ejs/davinci/dp83848.c
@@ -64,29 +64,16 @@ int dp83848_get_link_speed(int phy_addr)
return(0);
/* Speed doesn't matter, there is no setting for it in EMAC... */
- if (tmp & DP83848_SPEED) {
- if (tmp & DP83848_DUPLEX) {
- /* set DM644x EMAC for Full Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
+ if (tmp & DP83848_DUPLEX) {
+ /* set DM644x EMAC for Full Duplex */
+ emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
+ EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
} else {
- if (tmp & DP83848_DUPLEX) {
- /* set DM644x EMAC for Full Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
+ /*set DM644x EMAC for Half Duplex */
+ emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
}
- return(0);
+ return(1);
}
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index 7d60ad6..b5a6a4c 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -209,15 +209,15 @@ phys_size_t initdram(int board_type)
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
+ phys_size_t size = mb0cf[i].size;
+
/*
* OK, size detected. Enable second bank if
* defined (assumes same type as bank 0)
*/
#ifdef CONFIG_SDRAM_BANK1
- u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
-
mtsdram(mem_mcopt1, 0x00000000);
- mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
+ mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg);
mtsdram(mem_mcopt1, 0x80800000);
udelay(10000);
@@ -230,13 +230,19 @@ phys_size_t initdram(int board_type)
mb0cf[i].size) {
mtsdram(mem_mb1cf, 0);
mtsdram(mem_mcopt1, 0);
+ } else {
+ /*
+ * We have two identical banks, so the size
+ * is twice the bank size
+ */
+ size = 2 * size;
}
#endif
/*
* OK, size detected -> all done
*/
- return mb0cf[i].size;
+ return size;
}
}
diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c
index 121dcbe..1cfede7 100644
--- a/cpu/pxa/mmc.c
+++ b/cpu/pxa/mmc.c
@@ -575,8 +575,8 @@ mmc_init(int verbose)
break;
}
- /* Select 3.2-3.3 and 3.3-3.4V */
- resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0020, 0,
+ /* Select 3.2-3.3V and 3.3-3.4V */
+ resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0030, 0x0000,
MMC_CMDAT_R3 | (retries < 2 ? 0
: MMC_CMDAT_INIT));
if (resp[0] & 0x80000000) {
generated by cgit v1.1 at 2024-11-19 13:37:41 +0000