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-rw-r--r--cpu/ixp/npe/Makefile2
-rw-r--r--cpu/mpc5xxx/cpu.c16
-rw-r--r--cpu/mpc85xx/cpu.c69
-rw-r--r--cpu/mpc85xx/cpu_init.c2
-rw-r--r--cpu/mpc85xx/pci.c8
-rw-r--r--cpu/mpc85xx/spd_sdram.c31
-rw-r--r--cpu/mpc85xx/speed.c44
-rw-r--r--cpu/mpc85xx/start.S16
-rw-r--r--cpu/mpc86xx/cpu.c24
-rw-r--r--cpu/mpc86xx/spd_sdram.c28
-rw-r--r--cpu/mpc86xx/start.S42
-rw-r--r--cpu/ppc4xx/4xx_enet.c30
12 files changed, 197 insertions, 115 deletions
diff --git a/cpu/ixp/npe/Makefile b/cpu/ixp/npe/Makefile
index 4de34fd..7f020b5 100644
--- a/cpu/ixp/npe/Makefile
+++ b/cpu/ixp/npe/Makefile
@@ -87,7 +87,7 @@ START := $(addprefix $(obj),$(START))
all: $(LIB)
-$(LIB): $(obj).depend $(OBJS)
+$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index 813aa79..1eac2bb 100644
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -53,12 +53,16 @@ int checkcpu (void)
#else
svr = get_svr();
pvr = get_pvr();
- switch (SVR_VER (svr)) {
- case SVR_MPC5200:
- printf ("MPC5200");
+
+ switch (pvr) {
+ case PVR_5200:
+ printf("MPC5200");
+ break;
+ case PVR_5200B:
+ printf("MPC5200B");
break;
default:
- printf ("MPC52?? (SVR %08x)", svr);
+ printf("Unknown MPC5xxx");
break;
}
@@ -127,5 +131,9 @@ ft_cpu_setup(void *blob, bd_t *bd)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/local-mac-address", &len);
+ if (p != NULL)
+ memcpy(p, bd->bi_enetaddr, 6);
}
#endif
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 0507c47..7735a52 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004,2007 Freescale Semiconductor, Inc.
* (C) Copyright 2002, 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
@@ -70,6 +70,15 @@ int checkcpu (void)
case SVR_8548_E:
puts("8548_E");
break;
+ case SVR_8544:
+ puts("8544");
+ break;
+ case SVR_8544_E:
+ puts("8544_E");
+ break;
+ case SVR_8568_E:
+ puts("8568_E");
+ break;
default:
puts("Unknown");
break;
@@ -112,7 +121,7 @@ int checkcpu (void)
#endif
clkdiv = lcrr & 0x0f;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#ifdef CONFIG_MPC8548
+#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
/*
* Yes, the entire PQ38 family use the same
* bit-representation for twice the clock divider values.
@@ -140,16 +149,25 @@ int checkcpu (void)
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
+ uint pvr;
+ uint ver;
+ pvr = get_pvr();
+ ver = PVR_VER(pvr);
+ if (ver & 1){
+ /* e500 v2 core has reset control register */
+ volatile unsigned int * rstcr;
+ rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
+ *rstcr = 0x2; /* HRESET_REQ */
+ }else{
/*
* Initiate hard reset in debug control register DBCR0
* Make sure MSR[DE] = 1
*/
- unsigned long val;
-
- val = mfspr(DBCR0);
- val |= 0x70000000;
- mtspr(DBCR0,val);
-
+ unsigned long val;
+ val = mfspr(DBCR0);
+ val |= 0x70000000;
+ mtspr(DBCR0,val);
+ }
return 1;
}
@@ -183,9 +201,9 @@ reset_85xx_watchdog(void)
* Clear TSR(WIS) bit by writing 1
*/
unsigned long val;
- val = mfspr(tsr);
- val |= 0x40000000;
- mtspr(tsr, val);
+ val = mfspr(SPRN_TSR);
+ val |= TSR_WIS;
+ mtspr(SPRN_TSR, val);
}
#endif /* CONFIG_WATCHDOG */
@@ -196,6 +214,7 @@ void dma_init(void) {
dma->satr0 = 0x02c40000;
dma->datr0 = 0x02c40000;
+ dma->sr0 = 0xfffffff; /* clear any errors */
asm("sync; isync; msync");
return;
}
@@ -210,6 +229,10 @@ uint dma_check(void) {
status = dma->sr0;
}
+ /* clear MR0[CS] channel start bit */
+ dma->mr0 &= 0x00000001;
+ asm("sync;isync;msync");
+
if (status != 0) {
printf ("DMA Error: status = %x\n", status);
}
@@ -245,6 +268,10 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL)
*p = cpu_to_be32(clock);
+ p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
if (p != NULL)
*p = cpu_to_be32(clock);
@@ -255,21 +282,41 @@ ft_cpu_setup(void *blob, bd_t *bd)
#if defined(CONFIG_MPC85XX_TSEC1)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enetaddr, 6);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
+ if (p)
memcpy(p, bd->bi_enetaddr, 6);
#endif
#if defined(CONFIG_HAS_ETH1)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enet1addr, 6);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
+ if (p)
memcpy(p, bd->bi_enet1addr, 6);
#endif
#if defined(CONFIG_HAS_ETH2)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enet2addr, 6);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
+ if (p)
memcpy(p, bd->bi_enet2addr, 6);
#endif
#if defined(CONFIG_HAS_ETH3)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enet3addr, 6);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
+ if (p)
memcpy(p, bd->bi_enet3addr, 6);
#endif
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 9f4d36c..9517146 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -143,12 +143,10 @@ void cpu_init_f (void)
memctl->br1 = CFG_BR1_PRELIM;
#endif
-#if !defined(CONFIG_MPC85xx)
#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
memctl->or2 = CFG_OR2_PRELIM;
memctl->br2 = CFG_BR2_PRELIM;
#endif
-#endif
#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
memctl->or3 = CFG_OR3_PRELIM;
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index 84f839a..3c1a323 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -90,14 +90,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
pcix->powbear1 = 0x00000000;
pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
- POWAR_MEM_WRITE | POWAR_MEM_512M);
+ POWAR_MEM_WRITE | (__ilog2(CFG_PCI1_MEM_SIZE) - 1));
pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
pcix->potear2 = 0x00000000;
pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
pcix->powbear2 = 0x00000000;
pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
- POWAR_IO_WRITE | POWAR_IO_1M);
+ POWAR_IO_WRITE | (__ilog2(CFG_PCI1_IO_SIZE) - 1));
pcix->pitar1 = 0x00000000;
pcix->piwbar1 = 0x00000000;
@@ -175,14 +175,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
pcix2->powbear1 = 0x00000000;
pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
- POWAR_MEM_WRITE | POWAR_MEM_512M);
+ POWAR_MEM_WRITE | (__ilog2(CFG_PCI2_MEM_SIZE) - 1));
pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
pcix2->potear2 = 0x00000000;
pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
pcix2->powbear2 = 0x00000000;
pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
- POWAR_IO_WRITE | POWAR_IO_1M);
+ POWAR_IO_WRITE | (__ilog2(CFG_PCI2_IO_SIZE) - 1));
pcix2->pitar1 = 0x00000000;
pcix2->piwbar1 = 0x00000000;
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 6da5367..3777f49 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -263,13 +263,14 @@ spd_sdram(void)
}
/*
- * Adjust DDR II IO voltage biasing. It just makes it work.
+ * Adjust DDR II IO voltage biasing.
+ * Only 8548 rev 1 needs the fix
*/
- if (spd.mem_type == SPD_MEMTYPE_DDR2) {
- gur->ddrioovcr = (0
- | 0x80000000 /* Enable */
- | 0x10000000 /* VSEL to 1.8V */
- );
+ if ((SVR_VER(get_svr()) == SVR_8548_E) &&
+ (SVR_MJREV(get_svr()) == 1) &&
+ (spd.mem_type == SPD_MEMTYPE_DDR2)) {
+ gur->ddrioovcr = (0x80000000 /* Enable */
+ | 0x10000000);/* VSEL to 1.8V */
}
/*
@@ -786,14 +787,17 @@ spd_sdram(void)
* Is this an ECC DDR chip?
* But don't mess with it if the DDR controller will init mem.
*/
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+#ifdef CONFIG_DDR_ECC
if (spd.config == 0x02) {
+#ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
ddr->err_disable = 0x0000000d;
+#endif
ddr->err_sbe = 0x00ff0000;
}
+
debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
-#endif
+#endif /* CONFIG_DDR_ECC */
asm("sync;isync;msync");
udelay(500);
@@ -991,17 +995,24 @@ setup_laws_and_tlbs(unsigned int memsize)
break;
case 256:
case 512:
+ tlb_size = BOOKE_PAGESZ_256M;
+ break;
case 1024:
case 2048:
- tlb_size = BOOKE_PAGESZ_256M;
+ if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
+ tlb_size = BOOKE_PAGESZ_1G;
+ else
+ tlb_size = BOOKE_PAGESZ_256M;
break;
default:
puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
/*
* The memory was not able to be mapped.
+ * Default to a small size.
*/
- return 0;
+ tlb_size = BOOKE_PAGESZ_64M;
+ memsize=64;
break;
}
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index ca81ee7..12359a2 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -37,49 +37,21 @@ void get_sys_info (sys_info_t * sysInfo)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
- uint plat_ratio,e500_ratio;
+ uint plat_ratio,e500_ratio,half_freqSystemBus;
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
- switch(plat_ratio) {
- case 0x02:
- case 0x03:
- case 0x04:
- case 0x05:
- case 0x06:
- case 0x08:
- case 0x09:
- case 0x0a:
- case 0x0c:
- case 0x10:
- sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
- break;
- default:
- sysInfo->freqSystemBus = 0;
- break;
- }
-
+ sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
e500_ratio = (gur->porpllsr) & 0x003f0000;
e500_ratio >>= 16;
- switch(e500_ratio) {
- case 0x04:
- sysInfo->freqProcessor = 2*sysInfo->freqSystemBus;
- break;
- case 0x05:
- sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2;
- break;
- case 0x06:
- sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
- break;
- case 0x07:
- sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2;
- break;
- default:
- sysInfo->freqProcessor = 0;
- break;
- }
+
+ /* Divide before multiply to avoid integer
+ * overflow for processor speeds above 2GHz */
+ half_freqSystemBus = sysInfo->freqSystemBus/2;
+ sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
}
+
int get_clocks (void)
{
sys_info_t sys_info;
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index f96a4c3..20c7ebc 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -251,13 +251,10 @@ _start_e500:
*/
bl tlb1_entry
mr r5,r0
- li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */
- mtctr r1
lwzu r4,0(r5) /* how many TLB1 entries we actually use */
+ mtctr r4
-0: cmpwi r4,0
- beq 1f
- lwzu r0,4(r5)
+0: lwzu r0,4(r5)
lwzu r1,4(r5)
lwzu r2,4(r5)
lwzu r3,4(r5)
@@ -269,7 +266,6 @@ _start_e500:
msync
tlbwe
isync
- addi r4,r4,-1
bdnz 0b
1:
@@ -301,20 +297,16 @@ _start_e500:
bl law_entry
mr r6,r0
- li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */
- mtctr r1
lwzu r5,0(r6) /* how many windows we actually use */
+ mtctr r5
li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
li r1,0x0c30
-0: cmpwi r5,0
- beq 1f
- lwzu r4,4(r6)
+0: lwzu r4,4(r6)
lwzu r3,4(r6)
stwx r4,r7,r2
stwx r3,r7,r1
- addi r5,r5,-1
addi r2,r2,0x0020
addi r1,r1,0x0020
bdnz 0b
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 84f5bef..a33acfe 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -280,22 +280,38 @@ ft_cpu_setup(void *blob, bd_t *bd)
#if defined(CONFIG_MPC86XX_TSEC1)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
- memcpy(p, bd->bi_enetaddr, 6);
+ if (p != NULL)
+ memcpy(p, bd->bi_enetaddr, 6);
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enetaddr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC2)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
- memcpy(p, bd->bi_enet1addr, 6);
+ if (p != NULL)
+ memcpy(p, bd->bi_enet1addr, 6);
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
+ if (p != NULL)
+ memcpy(p, bd->bi_enet1addr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC3)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
- memcpy(p, bd->bi_enet2addr, 6);
+ if (p != NULL)
+ memcpy(p, bd->bi_enet2addr, 6);
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
+ if (p != NULL)
+ memcpy(p, bd->bi_enet2addr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC4)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
- memcpy(p, bd->bi_enet3addr, 6);
+ if (p != NULL)
+ memcpy(p, bd->bi_enet3addr, 6);
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
+ if (p != NULL)
+ memcpy(p, bd->bi_enet3addr, 6);
#endif
}
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index ac9ff81..f37ab43 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -51,20 +51,32 @@ extern int dma_xfer(void *dest, uint count, void *src);
#define CFG_SUPER_BANK_INTERLEAVING 0
/*
- * Convert picoseconds into clock cycles (rounding up if needed).
+ * Convert picoseconds into DRAM clock cycles (rounding up if needed).
*/
-int
-picos_to_clk(int picos)
+static unsigned int
+picos_to_clk(unsigned int picos)
{
- int clks;
-
- clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
- if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+ /* use unsigned long long to avoid rounding errors */
+ const unsigned long long ULL_2e12 = 2000000000000ULL;
+ unsigned long long clks;
+ unsigned long long clks_temp;
+
+ if (! picos)
+ return 0;
+
+ clks = get_bus_freq(0) * (unsigned long long) picos;
+ clks_temp = clks;
+ clks = clks / ULL_2e12;
+ if (clks_temp % ULL_2e12) {
clks++;
}
- return clks;
+ if (clks > 0xFFFFFFFFULL) {
+ clks = 0xFFFFFFFFULL;
+ }
+
+ return (unsigned int) clks;
}
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 7406fe2..67c56db 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -241,26 +241,40 @@ in_flash:
bl setup_ccsrbar
#endif
- /* Fix for SMP linux - Changing arbitration to round-robin */
- lis r3, CFG_CCSRBAR@h
- ori r3, r3, 0x1000
- xor r4, r4, r4
- li r4, 0x1000
- stw r4, 0(r3)
- /* setup the law entries */
- bl law_entry
+ /* -- MPC8641 Rev 1.0 MCM Errata fixups -- */
+
+ /* skip fixups if not Rev 1.0 */
+ mfspr r4, SVR
+ rlwinm r4,r4,0,24,31
+ cmpwi r4,0x10
+ bne 1f
+
+ lis r3,MCM_ABCR@ha
+ lwz r4,MCM_ABCR@l(r3) /* ABCR -> r4 */
+
+ /* set ABCR[A_STRM_CNT] = 0 */
+ rlwinm r4,r4,0,0,29
+
+ /* set ABCR[ARB_POLICY] to 0x1 (round-robin) */
+ addi r0,r0,1
+ rlwimi r4,r0,12,18,19
+
+ stw r4,MCM_ABCR@l(r3) /* r4 -> ABCR */
sync
- /* Don't use this feature due to bug in 8641D PD4 */
- /* Disable ERD_DIS */
- lis r3, CFG_CCSRBAR@h
- ori r3, r3, 0x1008
- lwz r4, 0(r3)
+ /* Set DBCR[ERD_DIS] */
+ lis r3,MCM_DBCR@ha
+ lwz r4,MCM_DBCR@l(r3)
oris r4, r4, 0x4000
- stw r4, 0(r3)
+ stw r4,MCM_DBCR@l(r3)
+ sync
+1:
+ /* setup the law entries */
+ bl law_entry
sync
+
#if (EMULATOR_RUN == 1)
/* On the emulator we want to adjust these ASAP */
/* otherwise things are sloooow */
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index cf56581..1200d02 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -339,29 +339,41 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
unsigned long zmiifer=0x0;
+ unsigned long pfc1;
- /*
- * Right now only 2*RGMII is supported. Please extend when needed.
- * sr - 2006-08-29
- */
- switch (1) {
- case 0:
+ mfsdr(sdr_pfc1, pfc1);
+ pfc1 &= SDR0_PFC1_SELECT_MASK;
+
+ switch (pfc1) {
+ case SDR0_PFC1_SELECT_CONFIG_2:
/* 1 x GMII port */
out32 (ZMII_FER, 0x00);
out32 (RGMII_FER, 0x00000037);
bis->bi_phymode[0] = BI_PHYMODE_GMII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
- case 1:
+ case SDR0_PFC1_SELECT_CONFIG_4:
/* 2 x RGMII ports */
out32 (ZMII_FER, 0x00);
out32 (RGMII_FER, 0x00000055);
bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII;
break;
- case 2:
+ case SDR0_PFC1_SELECT_CONFIG_6:
/* 2 x SMII ports */
-
+ out32 (ZMII_FER,
+ ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
+ ((ZMII_FER_SMII) << ZMII_FER_V(1)));
+ out32 (RGMII_FER, 0x00000000);
+ bis->bi_phymode[0] = BI_PHYMODE_SMII;
+ bis->bi_phymode[1] = BI_PHYMODE_SMII;
+ break;
+ case SDR0_PFC1_SELECT_CONFIG_1_2:
+ /* only 1 x MII supported */
+ out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
+ out32 (RGMII_FER, 0x00000000);
+ bis->bi_phymode[0] = BI_PHYMODE_MII;
+ bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
default:
break;
generated by cgit v1.1 at 2024-11-18 15:24:01 +0000