diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm1136/mx31/Makefile | 4 | ||||
| -rw-r--r-- | cpu/arm1136/mx31/nand_load.S | 160 | ||||
| -rw-r--r-- | cpu/arm1136/start.S | 113 | ||||
| -rw-r--r-- | cpu/arm926ejs/mx27/timer.c | 1 |
4 files changed, 248 insertions, 30 deletions
diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile index c8e18f7..a57465f 100644 --- a/cpu/arm1136/mx31/Makefile +++ b/cpu/arm1136/mx31/Makefile @@ -29,6 +29,10 @@ COBJS += generic.o COBJS += timer.o COBJS += devices.o +ifdef CONFIG_NAND_BOOT +SOBJS = nand_load.o +endif + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm1136/mx31/nand_load.S b/cpu/arm1136/mx31/nand_load.S new file mode 100644 index 0000000..c0d099a --- /dev/null +++ b/cpu/arm1136/mx31/nand_load.S @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/mx31-regs.h> + +.section ".text.load", "x" + +.macro wait_op_done +1: ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE + beq 1b +.endm + +data_output: + strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF] + mov r3, #FDO_PAGE_SPARE_VAL + strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + wait_op_done + bx lr + +send_addr: + strh r3, [r12, #NAND_FLASH_ADD_REG_OFF] + mov r3, #NAND_FLASH_CONFIG2_FADD_EN + strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + wait_op_done + bx lr + +send_cmd: + strh r3, [r12, #NAND_FLASH_CMD_REG_OFF] + mov r3, #NAND_FLASH_CONFIG2_FCMD_EN + strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + wait_op_done + bx lr + + +nand_read_page: + + mov r7, lr + + mov r3, #0x0 + /* send command */ + bl send_cmd + /* 5 cycles address input */ + mov r3, #0x0 + bl send_addr + mov r3, #0x0 + bl send_addr + mov r3, r0 + bl send_addr + mov r3, #0x0 + bl send_addr + mov r3, #0x0 + bl send_addr + /* confirm read */ + mov r3, #0x30 + bl send_cmd + /* data output */ + mov r8, #0x0 + mov r4, #0x4 +1: + bl data_output + add r8, r8, #0x01 + cmp r8, r4 + bne 1b + ldrh r3, [r12, #ECC_STATUS_RESULT_REG_OFF] + tst r3, #0x0a + bne . + mov pc, r7 + +.global mxc_nand_load +mxc_nand_load: + + /* Copy image from flash to SDRAM first */ + mov r0, #NFC_BASE_ADDR + add r12, r0, #0xE00 /* register */ + add r2, r0, #0x800 /* 2K */ + ldr r1, __TEXT_BASE + +1: ldmia r0!, {r3-r10} + stmia r1!, {r3-r10} + cmp r0, r2 + blo 1b + /* Jump to SDRAM */ + ldr r1, =0x0FFF + and r0, pc, r1 /* offset of pc */ + ldr r1, __TEXT_BASE + add r1, r1, #0x10 + add pc, r0, r1 + nop + nop + nop + nop + +nand_copy_block: + + /* wait for boot complete */ +4: + ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF] + tst r3, #0x8000 + beq 4b + + /* unlock buffer and blocks */ + mov r3, #0x02 + strh r3, [r12, #NFC_CONFIGURATION_REG_OFF] + mov r3, #0x0 + strh r3, [r12, #UNLOCK_START_BLK_ADD_REG_OFF] + mov r3, #0x800 + strh r3, [r12, #UNLOCK_END_BLK_ADD_REG_OFF] + mov r3, #0x04 + strh r3, [r12, #NF_WR_PROT_REG_OFF] + mov r3, #0x10 + strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF] + + /* read 1 block, 256K */ + mov r0, #0x01 /* page offset */ + ldr r11, __TEXT_BASE + add r11, r11, #0x800 + + mov r1, #NFC_BASE_ADDR + add r2, r1, #0x800 +2: + bl nand_read_page /* r0, r1, r2, r11 has been used */ + /* copy data from internal buffer */ +3: ldmia r1!, {r3-r10} + stmia r11!, {r3-r10} + cmp r1, r2 + blo 3b + + add r0, r0, #0x01 + cmp r0, #0x80 + mov r1, #NFC_BASE_ADDR + bne 2b + + /* set pc to _set_env */ + ldr r11, __TEXT_BASE + ldr r1, =0x7FF + /* correct the lr */ + and r13, r13, r1 + add r13, r13, r11 + mov pc, r13 + +__TEXT_BASE: + .word TEXT_BASE diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 957f438..a957ccc 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -85,40 +85,15 @@ _end_vect: ************************************************************************* */ -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - /* - * These are defined in the board-specific linker script. + * the actual reset code */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de +#ifdef CONFIG_NAND_BOOT +.section ".text.head", "x" #endif -/* - * the actual reset code - */ - +.globl reset reset: /* * set the cpu to SVC32 mode @@ -150,6 +125,86 @@ next: #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit #endif + b setup_env + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + mcr p15, 0, r0, c1, c0, 0 + + /* + * Jump to board specific initialization... The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle wake up conditions. + */ + mov ip, lr /* persevere link reg across call */ + bl lowlevel_init /* go setup pll,mux,memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ + + +#ifdef CONFIG_NAND_BOOT +.section ".text.setup" +#endif + +.globl _TEST_BASE +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: +#ifndef CONFIG_NAND_BOOT + .word _start +#else + .word reset +#endif + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +setup_env: #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ diff --git a/cpu/arm926ejs/mx27/timer.c b/cpu/arm926ejs/mx27/timer.c index 9011058..1e13627 100644 --- a/cpu/arm926ejs/mx27/timer.c +++ b/cpu/arm926ejs/mx27/timer.c @@ -118,7 +118,6 @@ int timer_init(void) writel(readl(®s->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, ®s->gpt_tctl); writel(readl(®s->gpt_tctl) | GPTCR_TEN, ®s->gpt_tctl); - return 0; } |