diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm_cortexa8/omap3/mem.c | 33 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/omap3/sys_info.c | 4 |
2 files changed, 15 insertions, 22 deletions
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index 3cc22c4..965de3a 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -51,7 +51,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG6, 0 }; -gpmc_csx_t *nand_cs_base; gpmc_t *gpmc_cfg_base; #if defined(CONFIG_ENV_IS_IN_NAND) @@ -72,8 +71,6 @@ static u32 gpmc_onenand[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG6, 0 }; -gpmc_csx_t *onenand_cs_base; - #if defined(CONFIG_ENV_IS_IN_ONENAND) #define GPMC_CS 0 #else @@ -195,21 +192,21 @@ void do_sdrc_init(u32 cs, u32 early) writel(0, &sdrc_base->cs[cs].mcfg); } -void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base, u32 base, +void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size) { - writel(0, &gpmc_cs_base->config7); + writel(0, &cs->config7); sdelay(1000); /* Delay for settling */ - writel(gpmc_config[0], &gpmc_cs_base->config1); - writel(gpmc_config[1], &gpmc_cs_base->config2); - writel(gpmc_config[2], &gpmc_cs_base->config3); - writel(gpmc_config[3], &gpmc_cs_base->config4); - writel(gpmc_config[4], &gpmc_cs_base->config5); - writel(gpmc_config[5], &gpmc_cs_base->config6); + writel(gpmc_config[0], &cs->config1); + writel(gpmc_config[1], &cs->config2); + writel(gpmc_config[2], &cs->config3); + writel(gpmc_config[3], &cs->config4); + writel(gpmc_config[4], &cs->config5); + writel(gpmc_config[5], &cs->config6); /* Enable the config */ writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), &gpmc_cs_base->config7); + (1 << 6)), &cs->config7); sdelay(2000); } @@ -223,7 +220,6 @@ void gpmc_init(void) /* putting a blanket check on GPMC based on ZeBu for now */ u32 *gpmc_config = NULL; gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE; - gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE; u32 base = 0; u32 size = 0; u32 f_off = CONFIG_SYS_MONITOR_LEN; @@ -242,17 +238,16 @@ void gpmc_init(void) * Disable the GPMC0 config set by ROM code * It conflicts with our MPDB (both at 0x08000000) */ - writel(0, &gpmc_cs_base->config7); + writel(0, &gpmc_base->cs[0].config7); sdelay(1000); #if defined(CONFIG_CMD_NAND) /* CS 0 */ gpmc_config = gpmc_m_nand; gpmc_cfg_base = gpmc_base; - nand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE + - (GPMC_CS * GPMC_CONFIG_WIDTH)); + base = PISMO1_NAND_BASE; size = PISMO1_NAND_SIZE; - enable_gpmc_config(gpmc_config, nand_cs_base, base, size); + enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_NAND) f_off = SMNAND_ENV_OFFSET; f_sec = SZ_128K; @@ -266,11 +261,9 @@ void gpmc_init(void) #if defined(CONFIG_CMD_ONENAND) gpmc_config = gpmc_onenand; - onenand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE + - (GPMC_CS * GPMC_CONFIG_WIDTH)); base = PISMO1_ONEN_BASE; size = PISMO1_ONEN_SIZE; - enable_gpmc_config(gpmc_config, onenand_cs_base, base, size); + enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_ONENAND) f_off = ONENAND_ENV_OFFSET; f_sec = SZ_128K; diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index 2f04cd6..91ee2ff 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -32,7 +32,7 @@ #include <i2c.h> extern omap3_sysinfo sysinfo; -static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE; +static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE; static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE; static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; static char *rev_s[CPU_3XX_MAX_REV] = { @@ -160,7 +160,7 @@ u32 get_gpmc0_base(void) { u32 b; - b = readl(&gpmc_cs_base->config7); + b = readl(&gpmc_base->cs[0].config7); b &= 0x1F; /* keep base [5:0] */ b = b << 24; /* ret 0x0b000000 */ return b; |