diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/sh4/cache.c | 48 | ||||
| -rw-r--r-- | cpu/sh4/config.mk | 2 | ||||
| -rw-r--r-- | cpu/sh4/cpu.c | 2 | ||||
| -rw-r--r-- | cpu/sh4/interrupts.c | 7 | ||||
| -rw-r--r-- | cpu/sh4/start.S | 19 | ||||
| -rw-r--r-- | cpu/sh4/watchdog.c | 6 |
6 files changed, 40 insertions, 44 deletions
diff --git a/cpu/sh4/cache.c b/cpu/sh4/cache.c index 55acb31..4e744d7 100644 --- a/cpu/sh4/cache.c +++ b/cpu/sh4/cache.c @@ -30,36 +30,36 @@ * Jump to P2 area. * When handling TLB or caches, we need to do it from P2 area. */ -#define jump_to_P2() \ - do { \ +#define jump_to_P2() \ + do { \ unsigned long __dummy; \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "or %1, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy) \ - : "r" (0x20000000)); \ + __asm__ __volatile__( \ + "mov.l 1f, %0\n\t" \ + "or %1, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy) \ + : "r" (0x20000000)); \ } while (0) /* * Back to P1 area. */ -#define back_to_P1() \ - do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "mov.l 1f, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy)); \ +#define back_to_P1() \ + do { \ + unsigned long __dummy; \ + __asm__ __volatile__( \ + "nop;nop;nop;nop;nop;nop;nop\n\t" \ + "mov.l 1f, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy)); \ } while (0) #define CACHE_VALID 1 diff --git a/cpu/sh4/config.mk b/cpu/sh4/config.mk index 2dc7b91..b3feb2a 100644 --- a/cpu/sh4/config.mk +++ b/cpu/sh4/config.mk @@ -4,7 +4,7 @@ # # (C) Copyright 2007 # Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -# +# # See file CREDITS for list of people who contributed to this # project. # diff --git a/cpu/sh4/cpu.c b/cpu/sh4/cpu.c index d76d518..0ebf951 100644 --- a/cpu/sh4/cpu.c +++ b/cpu/sh4/cpu.c @@ -66,7 +66,7 @@ void icache_disable (void) int icache_status (void) { - return 0; + return 0; } void dcache_enable (void) diff --git a/cpu/sh4/interrupts.c b/cpu/sh4/interrupts.c index d310dd2..6988ecc 100644 --- a/cpu/sh4/interrupts.c +++ b/cpu/sh4/interrupts.c @@ -25,7 +25,7 @@ int interrupt_init (void) { - return 0; + return 0; } void enable_interrupts (void) @@ -33,7 +33,6 @@ void enable_interrupts (void) } -int disable_interrupts (void){ - return 0; +int disable_interrupts (void){ + return 0; } - diff --git a/cpu/sh4/start.S b/cpu/sh4/start.S index d88b705..a68ebb8 100644 --- a/cpu/sh4/start.S +++ b/cpu/sh4/start.S @@ -33,21 +33,21 @@ _start: bsr 1f nop 1: sts pr, r5 - mov.l ._reloc_dst, r4 - add #(_start-1b), r5 - mov.l ._reloc_dst_end, r6 + mov.l ._reloc_dst, r4 + add #(_start-1b), r5 + mov.l ._reloc_dst_end, r6 2: mov.l @r5+, r1 mov.l r1, @r4 add #4, r4 cmp/hs r6, r4 bf 2b - - mov.l ._bss_start, r4 - mov.l ._bss_end, r5 + + mov.l ._bss_start, r4 + mov.l ._bss_end, r5 mov #0, r1 -3: mov.l r1, @r4 /* bss clear */ +3: mov.l r1, @r4 /* bss clear */ add #4, r4 cmp/hs r5, r4 bf 3b @@ -56,8 +56,8 @@ _start: mov.l ._stack_init, r15 /* stack */ mov.l ._sh_generic_init, r0 - jsr @r0 - nop + jsr @r0 + nop loop: bra loop @@ -72,4 +72,3 @@ loop: ._gd_init: .long (_start - CFG_GBL_DATA_SIZE) ._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16) ._sh_generic_init: .long sh_generic_init - diff --git a/cpu/sh4/watchdog.c b/cpu/sh4/watchdog.c index 04723a7..346e217 100644 --- a/cpu/sh4/watchdog.c +++ b/cpu/sh4/watchdog.c @@ -32,12 +32,12 @@ static void cnt_write (unsigned char value){ while (csr_read() & (1 << 5)) { /* delay */ } - *((volatile unsigned short *)(WDT_BASE + 0x00)) + *((volatile unsigned short *)(WDT_BASE + 0x00)) = ((unsigned short) value) | 0x5A00; } static void csr_write (unsigned char value){ - *((volatile unsigned short *)(WDT_BASE + 0x04)) + *((volatile unsigned short *)(WDT_BASE + 0x04)) = ((unsigned short) value) | 0xA500; } @@ -48,5 +48,3 @@ void reset_cpu (unsigned long ignored) { while(1); } - - |