diff options
Diffstat (limited to 'cpu')
31 files changed, 251 insertions, 3668 deletions
diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile index b648ffd..0e06f0a 100644 --- a/cpu/arm1136/mx31/Makefile +++ b/cpu/arm1136/mx31/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o serial.o generic.o +COBJS = interrupts.o generic.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm1136/mx31/serial.c b/cpu/arm1136/mx31/serial.c deleted file mode 100644 index e025e94..0000000 --- a/cpu/arm1136/mx31/serial.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> - -#if defined CONFIG_MX31_UART - -#include <asm/arch/mx31.h> - -#define __REG(x) (*((volatile u32 *)(x))) - -#ifdef CONFIG_SYS_MX31_UART1 -#define UART_PHYS 0x43f90000 -#elif defined(CONFIG_SYS_MX31_UART2) -#define UART_PHYS 0x43f94000 -#elif defined(CONFIG_SYS_MX31_UART3) -#define UART_PHYS 0x5000c000 -#elif defined(CONFIG_SYS_MX31_UART4) -#define UART_PHYS 0x43fb0000 -#elif defined(CONFIG_SYS_MX31_UART5) -#define UART_PHYS 0x43fb4000 -#else -#error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver" -#endif - -/* Register definitions */ -#define URXD 0x0 /* Receiver Register */ -#define UTXD 0x40 /* Transmitter Register */ -#define UCR1 0x80 /* Control Register 1 */ -#define UCR2 0x84 /* Control Register 2 */ -#define UCR3 0x88 /* Control Register 3 */ -#define UCR4 0x8c /* Control Register 4 */ -#define UFCR 0x90 /* FIFO Control Register */ -#define USR1 0x94 /* Status Register 1 */ -#define USR2 0x98 /* Status Register 2 */ -#define UESC 0x9c /* Escape Character Register */ -#define UTIM 0xa0 /* Escape Timer Register */ -#define UBIR 0xa4 /* BRM Incremental Register */ -#define UBMR 0xa8 /* BRM Modulator Register */ -#define UBRC 0xac /* Baud Rate Count Register */ -#define UTS 0xb4 /* UART Test Register (mx31) */ - -/* UART Control Register Bit Fields.*/ -#define URXD_CHARRDY (1<<15) -#define URXD_ERR (1<<14) -#define URXD_OVRRUN (1<<13) -#define URXD_FRMERR (1<<12) -#define URXD_BRK (1<<11) -#define URXD_PRERR (1<<10) -#define URXD_RX_DATA (0xFF) -#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ -#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ -#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ -#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ -#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ -#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ -#define UCR1_IREN (1<<7) /* Infrared interface enable */ -#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ -#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ -#define UCR1_SNDBRK (1<<4) /* Send break */ -#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ -#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ -#define UCR1_DOZE (1<<1) /* Doze */ -#define UCR1_UARTEN (1<<0) /* UART enabled */ -#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ -#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ -#define UCR2_CTSC (1<<13) /* CTS pin control */ -#define UCR2_CTS (1<<12) /* Clear to send */ -#define UCR2_ESCEN (1<<11) /* Escape enable */ -#define UCR2_PREN (1<<8) /* Parity enable */ -#define UCR2_PROE (1<<7) /* Parity odd/even */ -#define UCR2_STPB (1<<6) /* Stop */ -#define UCR2_WS (1<<5) /* Word size */ -#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ -#define UCR2_TXEN (1<<2) /* Transmitter enabled */ -#define UCR2_RXEN (1<<1) /* Receiver enabled */ -#define UCR2_SRST (1<<0) /* SW reset */ -#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ -#define UCR3_PARERREN (1<<12) /* Parity enable */ -#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ -#define UCR3_DSR (1<<10) /* Data set ready */ -#define UCR3_DCD (1<<9) /* Data carrier detect */ -#define UCR3_RI (1<<8) /* Ring indicator */ -#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ -#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ -#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ -#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ -#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ -#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ -#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ -#define UCR3_BPEN (1<<0) /* Preset registers enable */ -#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ -#define UCR4_INVR (1<<9) /* Inverted infrared reception */ -#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ -#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ -#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ -#define UCR4_IRSC (1<<5) /* IR special case */ -#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ -#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ -#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ -#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ -#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ -#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ -#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ -#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ -#define USR1_RTSS (1<<14) /* RTS pin status */ -#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ -#define USR1_RTSD (1<<12) /* RTS delta */ -#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ -#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ -#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ -#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ -#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ -#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ -#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ -#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ -#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ -#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ -#define USR2_IDLE (1<<12) /* Idle condition */ -#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ -#define USR2_WAKE (1<<7) /* Wake */ -#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ -#define USR2_TXDC (1<<3) /* Transmitter complete */ -#define USR2_BRCD (1<<2) /* Break condition */ -#define USR2_ORE (1<<1) /* Overrun error */ -#define USR2_RDR (1<<0) /* Recv data ready */ -#define UTS_FRCPERR (1<<13) /* Force parity error */ -#define UTS_LOOP (1<<12) /* Loop tx and rx */ -#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ -#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ -#define UTS_TXFULL (1<<4) /* TxFIFO full */ -#define UTS_RXFULL (1<<3) /* RxFIFO full */ -#define UTS_SOFTRST (1<<0) /* Software reset */ - -DECLARE_GLOBAL_DATA_PTR; - -void serial_setbrg (void) -{ - u32 clk = mx31_get_ipg_clk(); - - if (!gd->baudrate) - gd->baudrate = CONFIG_BAUDRATE; - - __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ - __REG(UART_PHYS + UBIR) = 0xf; - __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); - -} - -int serial_getc (void) -{ - while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); - return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ -} - -void serial_putc (const char c) -{ - __REG(UART_PHYS + UTXD) = c; - - /* wait for transmitter to be ready */ - while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int serial_tstc (void) -{ - /* If receive fifo is empty, return false */ - if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) - return 0; - return 1; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - __REG(UART_PHYS + UCR1) = 0x0; - __REG(UART_PHYS + UCR2) = 0x0; - - while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); - - __REG(UART_PHYS + UCR3) = 0x0704; - __REG(UART_PHYS + UCR4) = 0x8000; - __REG(UART_PHYS + UESC) = 0x002b; - __REG(UART_PHYS + UTIM) = 0x0; - - __REG(UART_PHYS + UTS) = 0x0; - - serial_setbrg(); - - __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; - - __REG(UART_PHYS + UCR1) = UCR1_UARTEN; - - return 0; -} - - -#endif /* CONFIG_MX31 */ diff --git a/cpu/arm1136/omap24xx/interrupts.c b/cpu/arm1136/omap24xx/interrupts.c index fb02a49..6be1262 100644 --- a/cpu/arm1136/omap24xx/interrupts.c +++ b/cpu/arm1136/omap24xx/interrupts.c @@ -49,7 +49,7 @@ int interrupt_init (void) /* Start the counter ticking up */ *((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ - val = (CONFIG_SYS_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ + val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ *((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */ reset_timer_masked(); /* init the timestamp and lastinc value */ diff --git a/cpu/arm1176/s3c64xx/Makefile b/cpu/arm1176/s3c64xx/Makefile index 4ab1811..fa4ee3f 100644 --- a/cpu/arm1176/s3c64xx/Makefile +++ b/cpu/arm1176/s3c64xx/Makefile @@ -30,7 +30,6 @@ LIB = $(obj)lib$(SOC).a COBJS-y = interrupts.o COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o -COBJS-$(CONFIG_USB_OHCI_NEW) += usb.o OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/cpu/arm1176/s3c64xx/usb.c b/cpu/arm1176/s3c64xx/usb.c deleted file mode 100644 index 274a4ed..0000000 --- a/cpu/arm1176/s3c64xx/usb.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) initialization for USB on the S3C64XX. - * - * Copyright (C) 2008, - * Guennadi Liakhovetski, DENX Software Engineering <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include <common.h> -#include <s3c6400.h> - -int usb_cpu_init(void) -{ - OTHERS_REG |= 0x10000; - return 0; -} - -int usb_cpu_stop(void) -{ - OTHERS_REG &= ~0x10000; - return 0; -} - -void usb_cpu_init_fail(void) -{ - OTHERS_REG &= ~0x10000; -} diff --git a/cpu/arm720t/Makefile b/cpu/arm720t/Makefile index c97f329..d5ac7d3 100644 --- a/cpu/arm720t/Makefile +++ b/cpu/arm720t/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = serial.o serial_netarm.o interrupts.o cpu.o +COBJS = interrupts.o cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 5ac8f59..8166982 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -188,71 +188,9 @@ int dcache_status (void) { return (read_p15_c1 () & C1_IDC) != 0; } - -#elif defined(CONFIG_S3C4510B) - -void icache_enable (void) -{ - s32 i; - - /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); - - /* 8KB cache, write enable */ - SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); - - /* clear TAG RAM bits */ - for ( i = 0; i < 256; i++) - PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); - - /* clear SET0 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); - - /* clear SET1 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); - - /* enable cache */ - SET_REG( REG_SYSCFG, CACHE_ENABLE); - -} - -void icache_disable (void) -{ - /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); -} - -int icache_status (void) -{ - return GET_REG( REG_SYSCFG) & CACHE_ENABLE; -} - -void dcache_enable (void) -{ - /* we don't have seperate instruction/data caches */ - icache_enable(); -} - -void dcache_disable (void) -{ - /* we don't have seperate instruction/data caches */ - icache_disable(); -} - -int dcache_status (void) -{ - /* we don't have seperate instruction/data caches */ - return icache_status(); -} - #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific cache setup for IntegratorAP/CM720T as yet */ void icache_enable (void) { } -#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */ -#else -#error No icache/dcache enable/disable functions defined for this CPU type #endif diff --git a/cpu/arm720t/s3c4510b/Makefile b/cpu/arm720t/s3c4510b/Makefile new file mode 100644 index 0000000..c9520b6 --- /dev/null +++ b/cpu/arm720t/s3c4510b/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y += cache.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/cpu/arm720t/s3c4510b/cache.c b/cpu/arm720t/s3c4510b/cache.c new file mode 100644 index 0000000..104d287 --- /dev/null +++ b/cpu/arm720t/s3c4510b/cache.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/hardware.h> + +void icache_enable (void) +{ + s32 i; + + /* disable all cache bits */ + CLR_REG( REG_SYSCFG, 0x3F); + + /* 8KB cache, write enable */ + SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); + + /* clear TAG RAM bits */ + for ( i = 0; i < 256; i++) + PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); + + /* clear SET0 RAM */ + for(i=0; i < 1024; i++) + PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); + + /* clear SET1 RAM */ + for(i=0; i < 1024; i++) + PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); + + /* enable cache */ + SET_REG( REG_SYSCFG, CACHE_ENABLE); + +} + +void icache_disable (void) +{ + /* disable all cache bits */ + CLR_REG( REG_SYSCFG, 0x3F); +} + +int icache_status (void) +{ + return GET_REG( REG_SYSCFG) & CACHE_ENABLE; +} + +void dcache_enable (void) +{ + /* we don't have seperate instruction/data caches */ + icache_enable(); +} + +void dcache_disable (void) +{ + /* we don't have seperate instruction/data caches */ + icache_disable(); +} + +int dcache_status (void) +{ + /* we don't have seperate instruction/data caches */ + return icache_status(); +} diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c deleted file mode 100644 index 54a9b31..0000000 --- a/cpu/arm720t/serial.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> - -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - -#include <clps7111.h> - -DECLARE_GLOBAL_DATA_PTR; - -void serial_setbrg (void) -{ - unsigned int reg = 0; - - switch (gd->baudrate) { - case 1200: reg = 191; break; - case 9600: reg = 23; break; - case 19200: reg = 11; break; - case 38400: reg = 5; break; - case 57600: reg = 3; break; - case 115200: reg = 1; break; - default: hang (); break; - } - - /* init serial serial 1,2 */ - IO_SYSCON1 = SYSCON1_UART1EN; - IO_SYSCON2 = SYSCON2_UART2EN; - - reg |= UBRLCR_WRDLEN8; - - IO_UBRLCR1 = reg; - IO_UBRLCR2 = reg; -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - int tmo; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); - - tmo = get_timer (0) + 1 * CONFIG_SYS_HZ; - while (IO_SYSFLG1 & SYSFLG1_UTXFF) - if (get_timer (0) > tmo) - break; - - IO_UARTDR1 = c; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_tstc (void) -{ - return !(IO_SYSFLG1 & SYSFLG1_URXFE); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - while (IO_SYSFLG1 & SYSFLG1_URXFE); - - return IO_UARTDR1 & 0xff; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -#elif defined(CONFIG_LPC2292) - -DECLARE_GLOBAL_DATA_PTR; - -#include <asm/arch/hardware.h> - -void serial_setbrg (void) -{ - unsigned short divisor = 0; - - switch (gd->baudrate) { - case 1200: divisor = 3072; break; - case 9600: divisor = 384; break; - case 19200: divisor = 192; break; - case 38400: divisor = 96; break; - case 57600: divisor = 64; break; - case 115200: divisor = 32; break; - default: hang (); break; - } - - /* init serial UART0 */ - PUT8(U0LCR, 0); - PUT8(U0IER, 0); - PUT8(U0LCR, 0x80); /* DLAB=1 */ - PUT8(U0DLL, (unsigned char)(divisor & 0x00FF)); - PUT8(U0DLM, (unsigned char)(divisor >> 8)); - PUT8(U0LCR, 0x03); /* 8N1, DLAB=0 */ - PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */ -} - -int serial_init (void) -{ - unsigned long pinsel0; - - serial_setbrg (); - - pinsel0 = GET32(PINSEL0); - pinsel0 &= ~(0x00000003); - pinsel0 |= 5; - PUT32(PINSEL0, pinsel0); - - return (0); -} - -void serial_putc (const char c) -{ - if (c == '\n') - { - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ - PUT8(U0THR, '\r'); - } - - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ - PUT8(U0THR, c); -} - -int serial_getc (void) -{ - while((GET8(U0LSR) & 1) == 0); - return GET8(U0RBR); -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -/* Test if there is a byte to read */ -int serial_tstc (void) -{ - return (GET8(U0LSR) & 1); -} - -#endif diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c deleted file mode 100644 index 1a1b2db..0000000 --- a/cpu/arm720t/serial_netarm.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Serial Port stuff - taken from Linux - * - * (C) Copyright 2002 - * MAZeT GmbH <www.mazet.de> - * Stephan Linz <linz@mazet.de>, <linz@li-pro.net> - * - * (c) 2004 - * IMMS gGmbH <www.imms.de> - * Thomas Elste <info@elste.org> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> - -#ifdef CONFIG_NETARM - -#include <asm/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA)) -#if !defined(CONFIG_NETARM_NS7520) -#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB)) -#else -#define PORTC (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC)) -#endif - -/* wait until transmitter is ready for another character */ -#define TXWAITRDY(registers) \ -{ \ - ulong tmo = get_timer(0) + 1 * CONFIG_SYS_HZ; \ - while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \ - if (get_timer(0) > tmo) \ - break; \ - } \ -} - - -#ifndef CONFIG_UART1_CONSOLE -volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0); -volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1); -#else -volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(1); -volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(0); -#endif - -extern void _netarm_led_FAIL1(void); - -/* - * Setup both serial i/f with given baudrate - */ -void serial_setbrg (void) -{ - /* set 0 ... make sure pins are configured for serial */ -#if !defined(CONFIG_NETARM_NS7520) - PORTA = PORTB = - NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); -#else - PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); - PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); -#endif - - /* first turn em off */ - serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0; - - /* clear match register, we don't need it */ - serial_reg_ch1->rx_match = serial_reg_ch2->rx_match = 0; - - /* setup bit rate generator and rx buffer gap timer (1 byte only) */ - if ((gd->baudrate >= MIN_BAUD_RATE) - && (gd->baudrate <= MAX_BAUD_RATE)) { - serial_reg_ch1->bitrate = serial_reg_ch2->bitrate = - NETARM_SER_BR_X16 (gd->baudrate); - serial_reg_ch1->rx_buf_timer = serial_reg_ch2->rx_buf_timer = - 0; - serial_reg_ch1->rx_char_timer = serial_reg_ch2->rx_char_timer = - NETARM_SER_RXGAP (gd->baudrate); - } else { - hang (); - } - - /* setup port mode */ - serial_reg_ch1->ctrl_b = serial_reg_ch2->ctrl_b = - ( NETARM_SER_CTLB_RCGT_EN | - NETARM_SER_CTLB_UART_MODE); - serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = - ( NETARM_SER_CTLA_ENABLE | - NETARM_SER_CTLA_P_NONE | - /* see errata */ - NETARM_SER_CTLA_2STOP | - NETARM_SER_CTLA_8BITS | - NETARM_SER_CTLA_DTR_EN | - NETARM_SER_CTLA_RTS_EN); -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - */ -int serial_init (void) -{ - serial_setbrg (); - return 0; -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - volatile unsigned char *fifo; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); - - fifo = (volatile unsigned char *) &(serial_reg_ch1->fifo); - TXWAITRDY (serial_reg_ch1); - *fifo = c; -} - -/* - * Test of a single byte from the serial port. Returns 1 on success, 0 - * otherwise. - */ -int serial_tstc(void) -{ - return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. - */ -int serial_getc (void) -{ - unsigned int ch_uint; - volatile unsigned int *fifo; - volatile unsigned char *fifo_char = NULL; - int buf_count = 0; - - while (!(serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY)) - /* NOP */ ; - - fifo = (volatile unsigned int *) &(serial_reg_ch1->fifo); - fifo_char = (unsigned char *) &ch_uint; - ch_uint = *fifo; - - buf_count = NETARM_SER_STATA_RXFDB (serial_reg_ch1->status_a); - switch (buf_count) { - case NETARM_SER_STATA_RXFDB_4BYTES: - buf_count = 4; - break; - case NETARM_SER_STATA_RXFDB_3BYTES: - buf_count = 3; - break; - case NETARM_SER_STATA_RXFDB_2BYTES: - buf_count = 2; - break; - case NETARM_SER_STATA_RXFDB_1BYTES: - buf_count = 1; - break; - default: - /* panic, be never here */ - break; - } - - serial_reg_ch1->status_a |= NETARM_SER_STATA_RX_CLOSED; - - return ch_uint & 0xff; -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -#endif /* CONFIG_NETARM */ diff --git a/cpu/arm920t/imx/Makefile b/cpu/arm920t/imx/Makefile index 9207ec1..d3352de 100644 --- a/cpu/arm920t/imx/Makefile +++ b/cpu/arm920t/imx/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = generic.o interrupts.o serial.o speed.o +COBJS = generic.o interrupts.o speed.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm920t/imx/serial.c b/cpu/arm920t/imx/serial.c deleted file mode 100644 index 85f1167..0000000 --- a/cpu/arm920t/imx/serial.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * (c) 2004 Sascha Hauer <sascha@saschahauer.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> -#if defined (CONFIG_IMX) - -#include <asm/arch/imx-regs.h> - -#ifndef CONFIG_IMX_SERIAL_NONE - -#if defined CONFIG_IMX_SERIAL1 -#define UART_BASE IMX_UART1_BASE -#elif defined CONFIG_IMX_SERIAL2 -#define UART_BASE IMX_UART2_BASE -#else -#error "define CONFIG_IMX_SERIAL1, CONFIG_IMX_SERIAL2 or CONFIG_IMX_SERIAL_NONE" -#endif - -struct imx_serial { - volatile uint32_t urxd[16]; - volatile uint32_t utxd[16]; - volatile uint32_t ucr1; - volatile uint32_t ucr2; - volatile uint32_t ucr3; - volatile uint32_t ucr4; - volatile uint32_t ufcr; - volatile uint32_t usr1; - volatile uint32_t usr2; - volatile uint32_t uesc; - volatile uint32_t utim; - volatile uint32_t ubir; - volatile uint32_t ubmr; - volatile uint32_t ubrc; - volatile uint32_t bipr[4]; - volatile uint32_t bmpr[4]; - volatile uint32_t uts; -}; - -DECLARE_GLOBAL_DATA_PTR; - -void serial_setbrg (void) -{ - serial_init(); -} - -extern void imx_gpio_mode(int gpio_mode); - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; - unsigned int ufcr_rfdiv; - unsigned int refclk; - -#ifdef CONFIG_IMX_SERIAL1 - imx_gpio_mode(PC11_PF_UART1_TXD); - imx_gpio_mode(PC12_PF_UART1_RXD); -#else - imx_gpio_mode(PB30_PF_UART2_TXD); - imx_gpio_mode(PB31_PF_UART2_RXD); -#endif - - /* Disable UART */ - base->ucr1 &= ~UCR1_UARTEN; - - /* Set to default POR state */ - - base->ucr1 = 0x00000004; - base->ucr2 = 0x00000000; - base->ucr3 = 0x00000000; - base->ucr4 = 0x00008040; - base->uesc = 0x0000002B; - base->utim = 0x00000000; - base->ubir = 0x00000000; - base->ubmr = 0x00000000; - base->uts = 0x00000000; - /* Set clocks */ - base->ucr4 |= UCR4_REF16; - - /* Configure FIFOs */ - base->ufcr = 0xa81; - - /* set the baud rate. - * - * baud * 16 x - * --------- = - - * refclk y - * - * x - 1 = UBIR - * y - 1 = UBMR - * - * each register is 16 bits wide. refclk max is 96 MHz - * - */ - - ufcr_rfdiv = ((base->ufcr) & UFCR_RFDIV) >> 7; - if (ufcr_rfdiv == 6) - ufcr_rfdiv = 7; - else - ufcr_rfdiv = 6 - ufcr_rfdiv; - - refclk = get_PERCLK1(); - refclk /= ufcr_rfdiv; - - /* Set the numerator value minus one of the BRM ratio */ - base->ubir = (gd->baudrate / 100) - 1; - - /* Set the denominator value minus one of the BRM ratio */ - base->ubmr = (refclk/(16 * 100)) - 1; - - /* Set to 8N1 */ - base->ucr2 &= ~UCR2_PREN; - base->ucr2 |= UCR2_WS; - base->ucr2 &= ~UCR2_STPB; - - /* Ignore RTS */ - base->ucr2 |= UCR2_IRTS; - - /* Enable UART */ - base->ucr1 |= UCR1_UARTEN | UCR1_UARTCLKEN; - - /* Enable FIFOs */ - base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN; - - /* Clear status flags */ - base->usr2 |= USR2_ADET | - USR2_DTRF | - USR2_IDLE | - USR2_IRINT | - USR2_WAKE | - USR2_RTSF | - USR2_BRCD | - USR2_ORE; - - /* Clear status flags */ - base->usr1 |= USR1_PARITYERR | - USR1_RTSD | - USR1_ESCF | - USR1_FRAMERR | - USR1_AIRINT | - USR1_AWAKE; - return (0); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is successful, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; - unsigned char ch; - - while(base->uts & UTS_RXEMPTY); - - ch = (char)base->urxd[0]; - - return ch; -} - -#ifdef CONFIG_HWFLOW -static int hwflow = 0; /* turned off by default */ -int hwflow_onoff(int on) -{ -} -#endif - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; - - /* Wait for Tx FIFO not full */ - while (base->uts & UTS_TXFULL); - - base->utxd[0] = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int serial_tstc (void) -{ - volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; - - /* If receive fifo is empty, return false */ - if (base->uts & UTS_RXEMPTY) - return 0; - return 1; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} -#endif /* CONFIG_IMX_SERIAL_NONE */ -#endif /* defined CONFIG_IMX */ diff --git a/cpu/arm920t/ks8695/Makefile b/cpu/arm920t/ks8695/Makefile index 7db9473..f6b0063 100644 --- a/cpu/arm920t/ks8695/Makefile +++ b/cpu/arm920t/ks8695/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o serial.o +COBJS = interrupts.o SOBJS = lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm920t/ks8695/serial.c b/cpu/arm920t/ks8695/serial.c deleted file mode 100644 index aacd1be..0000000 --- a/cpu/arm920t/ks8695/serial.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * serial.c -- KS8695 serial driver - * - * (C) Copyright 2004, Greg Ungerer <greg.ungerer@opengear.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/platform.h> - -#ifndef CONFIG_SERIAL1 -#error "Bad: you didn't configure serial ..." -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Define the UART hardware register access structure. - */ -struct ks8695uart { - unsigned int RX; /* 0x00 - Receive data (r) */ - unsigned int TX; /* 0x04 - Transmit data (w) */ - unsigned int FCR; /* 0x08 - Fifo Control (r/w) */ - unsigned int LCR; /* 0x0c - Line Control (r/w) */ - unsigned int MCR; /* 0x10 - Modem Control (r/w) */ - unsigned int LSR; /* 0x14 - Line Status (r/w) */ - unsigned int MSR; /* 0x18 - Modem Status (r/w) */ - unsigned int BD; /* 0x1c - Baud Rate (r/w) */ - unsigned int SR; /* 0x20 - Status (r/w) */ -}; - -#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER)) -#define KS8695_UART_CLK 25000000 - - -/* - * Under some circumstances we want to be "quiet" and not issue any - * serial output - though we want u-boot to otherwise work and behave - * the same. By default be noisy. - */ -int serial_console = 1; - - -void serial_setbrg(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - - /* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/ - uartp->BD = KS8695_UART_CLK / gd->baudrate; - uartp->LCR = KS8695_UART_LINEC_WLEN8; -} - -int serial_init(void) -{ - serial_console = 1; - serial_setbrg(); - return 0; -} - -void serial_raw_putc(const char c) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - int i; - - for (i = 0; (i < 0x100000); i++) { - if (uartp->LSR & KS8695_UART_LINES_TXFE) - break; - } - - uartp->TX = c; -} - -void serial_putc(const char c) -{ - if (serial_console) { - serial_raw_putc(c); - if (c == '\n') - serial_raw_putc('\r'); - } -} - -int serial_tstc(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - if (serial_console) - return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0); - return 0; -} - -void serial_puts(const char *s) -{ - char c; - while ((c = *s++) != 0) - serial_putc(c); -} - -int serial_getc(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - - while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0) - ; - return (uartp->RX); -} diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile index 6764920..3afe19c 100644 --- a/cpu/arm920t/s3c24x0/Makefile +++ b/cpu/arm920t/s3c24x0/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = i2c.o interrupts.o serial.o speed.o \ - usb.o usb_ohci.o nand.o +COBJS = interrupts.o speed.o usb.o usb_ohci.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm920t/s3c24x0/i2c.c b/cpu/arm920t/s3c24x0/i2c.c deleted file mode 100644 index fba5cd1..0000000 --- a/cpu/arm920t/s3c24x0/i2c.c +++ /dev/null @@ -1,447 +0,0 @@ -/* - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This code should work for both the S3C2400 and the S3C2410 - * as they seem to have the same I2C controller inside. - * The different address mapping is handled by the s3c24xx.h files below. - */ - -#include <common.h> - -#ifdef CONFIG_DRIVER_S3C24X0_I2C - -#if defined(CONFIG_S3C2400) -#include <s3c2400.h> -#elif defined(CONFIG_S3C2410) -#include <s3c2410.h> -#endif -#include <i2c.h> - -#ifdef CONFIG_HARD_I2C - -#define I2C_WRITE 0 -#define I2C_READ 1 - -#define I2C_OK 0 -#define I2C_NOK 1 -#define I2C_NACK 2 -#define I2C_NOK_LA 3 /* Lost arbitration */ -#define I2C_NOK_TOUT 4 /* time out */ - -#define I2CSTAT_BSY 0x20 /* Busy bit */ -#define I2CSTAT_NACK 0x01 /* Nack bit */ -#define I2CCON_IRPND 0x10 /* Interrupt pending bit */ -#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ -#define I2C_MODE_MR 0x80 /* Master Receive Mode */ -#define I2C_START_STOP 0x20 /* START / STOP */ -#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ - -#define I2C_TIMEOUT 1 /* 1 second */ - - -static int GetI2CSDA(void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - -#ifdef CONFIG_S3C2410 - return (gpio->GPEDAT & 0x8000) >> 15; -#endif -#ifdef CONFIG_S3C2400 - return (gpio->PGDAT & 0x0020) >> 5; -#endif -} - -#if 0 -static void SetI2CSDA(int x) -{ - rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15; -} -#endif - -static void SetI2CSCL(int x) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - -#ifdef CONFIG_S3C2410 - gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14; -#endif -#ifdef CONFIG_S3C2400 - gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6; -#endif -} - - -static int WaitForXfer (void) -{ - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - int i, status; - - i = I2C_TIMEOUT * 10000; - status = i2c->IICCON; - while ((i > 0) && !(status & I2CCON_IRPND)) { - udelay (100); - status = i2c->IICCON; - i--; - } - - return (status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; -} - -static int IsACK (void) -{ - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - - return (!(i2c->IICSTAT & I2CSTAT_NACK)); -} - -static void ReadWriteByte (void) -{ - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - - i2c->IICCON &= ~I2CCON_IRPND; -} - -void i2c_init (int speed, int slaveadd) -{ - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - S3C24X0_GPIO *const gpio = S3C24X0_GetBase_GPIO (); - ulong freq, pres = 16, div; - int i, status; - - /* wait for some time to give previous transfer a chance to finish */ - - i = I2C_TIMEOUT * 1000; - status = i2c->IICSTAT; - while ((i > 0) && (status & I2CSTAT_BSY)) { - udelay (1000); - status = i2c->IICSTAT; - i--; - } - - if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) { -#ifdef CONFIG_S3C2410 - ulong old_gpecon = gpio->GPECON; -#endif -#ifdef CONFIG_S3C2400 - ulong old_gpecon = gpio->PGCON; -#endif - /* bus still busy probably by (most) previously interrupted transfer */ - -#ifdef CONFIG_S3C2410 - /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ - gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000; -#endif -#ifdef CONFIG_S3C2400 - /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ - gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00001000; -#endif - - /* toggle I2CSCL until bus idle */ - SetI2CSCL (0); - udelay (1000); - i = 10; - while ((i > 0) && (GetI2CSDA () != 1)) { - SetI2CSCL (1); - udelay (1000); - SetI2CSCL (0); - udelay (1000); - i--; - } - SetI2CSCL (1); - udelay (1000); - - /* restore pin functions */ -#ifdef CONFIG_S3C2410 - gpio->GPECON = old_gpecon; -#endif -#ifdef CONFIG_S3C2400 - gpio->PGCON = old_gpecon; -#endif - } - - /* calculate prescaler and divisor values */ - freq = get_PCLK (); - if ((freq / pres / (16 + 1)) > speed) - /* set prescaler to 512 */ - pres = 512; - - div = 0; - while ((freq / pres / (div + 1)) > speed) - div++; - - /* set prescaler, divisor according to freq, also set - * ACKGEN, IRQ */ - i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0); - - /* init to SLAVE REVEIVE and set slaveaddr */ - i2c->IICSTAT = 0; - i2c->IICADD = slaveadd; - /* program Master Transmit (and implicit STOP) */ - i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; - -} - -/* - * cmd_type is 0 for write, 1 for read. - * - * addr_len can take any value from 0-255, it is only limited - * by the char, we could make it larger if needed. If it is - * 0 we skip the address write cycle. - */ -static -int i2c_transfer (unsigned char cmd_type, - unsigned char chip, - unsigned char addr[], - unsigned char addr_len, - unsigned char data[], unsigned short data_len) -{ - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - int i, status, result; - - if (data == 0 || data_len == 0) { - /*Don't support data transfer of no length or to address 0 */ - printf ("i2c_transfer: bad call\n"); - return I2C_NOK; - } - - /* Check I2C bus idle */ - i = I2C_TIMEOUT * 1000; - status = i2c->IICSTAT; - while ((i > 0) && (status & I2CSTAT_BSY)) { - udelay (1000); - status = i2c->IICSTAT; - i--; - } - - if (status & I2CSTAT_BSY) - return I2C_NOK_TOUT; - - i2c->IICCON |= 0x80; - result = I2C_OK; - - switch (cmd_type) { - case I2C_WRITE: - if (addr && addr_len) { - i2c->IICDS = chip; - /* send START */ - i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; - i = 0; - while ((i < addr_len) && (result == I2C_OK)) { - result = WaitForXfer (); - i2c->IICDS = addr[i]; - ReadWriteByte (); - i++; - } - i = 0; - while ((i < data_len) && (result == I2C_OK)) { - result = WaitForXfer (); - i2c->IICDS = data[i]; - ReadWriteByte (); - i++; - } - } else { - i2c->IICDS = chip; - /* send START */ - i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; - i = 0; - while ((i < data_len) && (result = I2C_OK)) { - result = WaitForXfer (); - i2c->IICDS = data[i]; - ReadWriteByte (); - i++; - } - } - - if (result == I2C_OK) - result = WaitForXfer (); - - /* send STOP */ - i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; - ReadWriteByte (); - break; - - case I2C_READ: - if (addr && addr_len) { - i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; - i2c->IICDS = chip; - /* send START */ - i2c->IICSTAT |= I2C_START_STOP; - result = WaitForXfer (); - if (IsACK ()) { - i = 0; - while ((i < addr_len) && (result == I2C_OK)) { - i2c->IICDS = addr[i]; - ReadWriteByte (); - result = WaitForXfer (); - i++; - } - - i2c->IICDS = chip; - /* resend START */ - i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA | - I2C_START_STOP; - ReadWriteByte (); - result = WaitForXfer (); - i = 0; - while ((i < data_len) && (result == I2C_OK)) { - /* disable ACK for final READ */ - if (i == data_len - 1) - i2c->IICCON &= ~0x80; - ReadWriteByte (); - result = WaitForXfer (); - data[i] = i2c->IICDS; - i++; - } - } else { - result = I2C_NACK; - } - - } else { - i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; - i2c->IICDS = chip; - /* send START */ - i2c->IICSTAT |= I2C_START_STOP; - result = WaitForXfer (); - - if (IsACK ()) { - i = 0; - while ((i < data_len) && (result == I2C_OK)) { - /* disable ACK for final READ */ - if (i == data_len - 1) - i2c->IICCON &= ~0x80; - ReadWriteByte (); - result = WaitForXfer (); - data[i] = i2c->IICDS; - i++; - } - } else { - result = I2C_NACK; - } - } - - /* send STOP */ - i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; - ReadWriteByte (); - break; - - default: - printf ("i2c_transfer: bad call\n"); - result = I2C_NOK; - break; - } - - return (result); -} - -int i2c_probe (uchar chip) -{ - uchar buf[1]; - - buf[0] = 0; - - /* - * What is needed is to send the chip address and verify that the - * address was <ACK>ed (i.e. there was a chip at that address which - * drove the data line low). - */ - return (i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK); -} - -int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - uchar xaddr[4]; - int ret; - - if (alen > 4) { - printf ("I2C read: addr len %d not supported\n", alen); - return 1; - } - - if (alen > 0) { - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - } - -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - if (alen > 0) - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); -#endif - if ((ret = - i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen, - buffer, len)) != 0) { - printf ("I2c read: failed %d\n", ret); - return 1; - } - return 0; -} - -int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - uchar xaddr[4]; - - if (alen > 4) { - printf ("I2C write: addr len %d not supported\n", alen); - return 1; - } - - if (alen > 0) { - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - } -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - if (alen > 0) - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); -#endif - return (i2c_transfer - (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, - len) != 0); -} -#endif /* CONFIG_HARD_I2C */ - -#endif /* CONFIG_DRIVER_S3C24X0_I2C */ diff --git a/cpu/arm920t/s3c24x0/nand.c b/cpu/arm920t/s3c24x0/nand.c deleted file mode 100644 index 60174fb..0000000 --- a/cpu/arm920t/s3c24x0/nand.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * (C) Copyright 2006 OpenMoko, Inc. - * Author: Harald Welte <laforge@openmoko.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#if 0 -#define DEBUGN printf -#else -#define DEBUGN(x, args ...) {} -#endif - -#if defined(CONFIG_CMD_NAND) -#if !defined(CONFIG_NAND_LEGACY) - -#include <nand.h> -#include <s3c2410.h> -#include <asm/io.h> - -#define __REGb(x) (*(volatile unsigned char *)(x)) -#define __REGi(x) (*(volatile unsigned int *)(x)) - -#define NF_BASE 0x4e000000 -#define NFCONF __REGi(NF_BASE + 0x0) -#define NFCMD __REGb(NF_BASE + 0x4) -#define NFADDR __REGb(NF_BASE + 0x8) -#define NFDATA __REGb(NF_BASE + 0xc) -#define NFSTAT __REGb(NF_BASE + 0x10) -#define NFECC0 __REGb(NF_BASE + 0x14) -#define NFECC1 __REGb(NF_BASE + 0x15) -#define NFECC2 __REGb(NF_BASE + 0x16) - -#define S3C2410_NFCONF_EN (1<<15) -#define S3C2410_NFCONF_512BYTE (1<<14) -#define S3C2410_NFCONF_4STEP (1<<13) -#define S3C2410_NFCONF_INITECC (1<<12) -#define S3C2410_NFCONF_nFCE (1<<11) -#define S3C2410_NFCONF_TACLS(x) ((x)<<8) -#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) -#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) - -#define S3C2410_ADDR_NALE 4 -#define S3C2410_ADDR_NCLE 8 - -static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *chip = mtd->priv; - - DEBUGN("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); - - if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = NF_BASE; - - if (!(ctrl & NAND_CLE)) - IO_ADDR_W |= S3C2410_ADDR_NCLE; - if (!(ctrl & NAND_ALE)) - IO_ADDR_W |= S3C2410_ADDR_NALE; - - chip->IO_ADDR_W = (void *)IO_ADDR_W; - - if (ctrl & NAND_NCE) - NFCONF &= ~S3C2410_NFCONF_nFCE; - else - NFCONF |= S3C2410_NFCONF_nFCE; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, chip->IO_ADDR_W); -} - -static int s3c2410_dev_ready(struct mtd_info *mtd) -{ - DEBUGN("dev_ready\n"); - return (NFSTAT & 0x01); -} - -#ifdef CONFIG_S3C2410_NAND_HWECC -void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) -{ - DEBUGN("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); - NFCONF |= S3C2410_NFCONF_INITECC; -} - -static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, - u_char *ecc_code) -{ - ecc_code[0] = NFECC0; - ecc_code[1] = NFECC1; - ecc_code[2] = NFECC2; - DEBUGN("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", - mtd , ecc_code[0], ecc_code[1], ecc_code[2]); - - return 0; -} - -static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *calc_ecc) -{ - if (read_ecc[0] == calc_ecc[0] && - read_ecc[1] == calc_ecc[1] && - read_ecc[2] == calc_ecc[2]) - return 0; - - printf("s3c2410_nand_correct_data: not implemented\n"); - return -1; -} -#endif - -int board_nand_init(struct nand_chip *nand) -{ - u_int32_t cfg; - u_int8_t tacls, twrph0, twrph1; - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - - DEBUGN("board_nand_init()\n"); - - clk_power->CLKCON |= (1 << 4); - - /* initialize hardware */ - twrph0 = 3; twrph1 = 0; tacls = 0; - - cfg = S3C2410_NFCONF_EN; - cfg |= S3C2410_NFCONF_TACLS(tacls - 1); - cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); - cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); - - NFCONF = cfg; - - /* initialize nand_chip data structure */ - nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)0x4e00000c; - - /* read_buf and write_buf are default */ - /* read_byte and write_byte are default */ - - /* hwcontrol always must be implemented */ - nand->cmd_ctrl = s3c2410_hwcontrol; - - nand->dev_ready = s3c2410_dev_ready; - -#ifdef CONFIG_S3C2410_NAND_HWECC - nand->ecc.hwctl = s3c2410_nand_enable_hwecc; - nand->ecc.calculate = s3c2410_nand_calculate_ecc; - nand->ecc.correct = s3c2410_nand_correct_data; - nand->ecc.mode = NAND_ECC_HW3_512; -#else - nand->ecc.mode = NAND_ECC_SOFT; -#endif - -#ifdef CONFIG_S3C2410_NAND_BBT - nand->options = NAND_USE_FLASH_BBT; -#else - nand->options = 0; -#endif - - DEBUGN("end of nand_init\n"); - - return 0; -} - -#else - #error "U-Boot legacy NAND support not available for S3C2410" -#endif -#endif diff --git a/cpu/arm920t/s3c24x0/serial.c b/cpu/arm920t/s3c24x0/serial.c deleted file mode 100644 index 064b998..0000000 --- a/cpu/arm920t/s3c24x0/serial.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> -#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) - -#if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB) -#include <s3c2400.h> -#elif defined(CONFIG_S3C2410) -#include <s3c2410.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SERIAL1 -#define UART_NR S3C24X0_UART0 - -#elif defined(CONFIG_SERIAL2) -# if defined(CONFIG_TRAB) -# error "TRAB supports only CONFIG_SERIAL1" -# endif -#define UART_NR S3C24X0_UART1 - -#elif defined(CONFIG_SERIAL3) -# if defined(CONFIG_TRAB) -# #error "TRAB supports only CONFIG_SERIAL1" -# endif -#define UART_NR S3C24X0_UART2 - -#else -#error "Bad: you didn't configure serial ..." -#endif - -#if defined(CONFIG_SERIAL_MULTI) -#include <serial.h> - -/* Multi serial device functions */ -#define DECLARE_S3C_SERIAL_FUNCTIONS(port) \ - int s3serial##port##_init (void) {\ - return serial_init_dev(port);}\ - void s3serial##port##_setbrg (void) {\ - serial_setbrg_dev(port);}\ - int s3serial##port##_getc (void) {\ - return serial_getc_dev(port);}\ - int s3serial##port##_tstc (void) {\ - return serial_tstc_dev(port);}\ - void s3serial##port##_putc (const char c) {\ - serial_putc_dev(port, c);}\ - void s3serial##port##_puts (const char *s) {\ - serial_puts_dev(port, s);} - -#define INIT_S3C_SERIAL_STRUCTURE(port,name,bus) {\ - name,\ - bus,\ - s3serial##port##_init,\ - s3serial##port##_setbrg,\ - s3serial##port##_getc,\ - s3serial##port##_tstc,\ - s3serial##port##_putc,\ - s3serial##port##_puts, } - -#endif /* CONFIG_SERIAL_MULTI */ - -void _serial_setbrg(const int dev_index) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); - unsigned int reg = 0; - int i; - - /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ - reg = get_PCLK() / (16 * gd->baudrate) - 1; - - uart->UBRDIV = reg; - for (i = 0; i < 100; i++); -} -#if defined(CONFIG_SERIAL_MULTI) -static inline void -serial_setbrg_dev(unsigned int dev_index) -{ - _serial_setbrg(dev_index); -} -#else -void serial_setbrg(void) -{ - _serial_setbrg(UART_NR); -} -#endif - - -/* Initialise the serial port. The settings are always 8 data bits, no parity, - * 1 stop bit, no start bits. - */ -static int serial_init_dev(const int dev_index) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); - - /* FIFO enable, Tx/Rx FIFO clear */ - uart->UFCON = 0x07; - uart->UMCON = 0x0; - - /* Normal,No parity,1 stop,8 bit */ - uart->ULCON = 0x3; - /* - * tx=level,rx=edge,disable timeout int.,enable rx error int., - * normal,interrupt or polling - */ - uart->UCON = 0x245; - -#ifdef CONFIG_HWFLOW - uart->UMCON = 0x1; /* RTS up */ -#endif - - /* FIXME: This is sooooooooooooooooooo ugly */ -#if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2) - /* we need auto hw flow control on the gsm and gps port */ - if (dev_index == 0 || dev_index == 1) - uart->UMCON = 0x10; -#endif - _serial_setbrg(dev_index); - - return (0); -} - -#if !defined(CONFIG_SERIAL_MULTI) -/* Initialise the serial port. The settings are always 8 data bits, no parity, - * 1 stop bit, no start bits. - */ -int serial_init (void) -{ - return serial_init_dev(UART_NR); -} -#endif - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int _serial_getc (const int dev_index) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); - - /* wait for character to arrive */ - while (!(uart->UTRSTAT & 0x1)); - - return uart->URXH & 0xff; -} -#if defined(CONFIG_SERIAL_MULTI) -static inline int serial_getc_dev(unsigned int dev_index) -{ - return _serial_getc(dev_index); -} -#else -int serial_getc (void) -{ - return _serial_getc(UART_NR); -} -#endif - -#ifdef CONFIG_HWFLOW -static int hwflow = 0; /* turned off by default */ -int hwflow_onoff(int on) -{ - switch(on) { - case 0: - default: - break; /* return current */ - case 1: - hwflow = 1; /* turn on */ - break; - case -1: - hwflow = 0; /* turn off */ - break; - } - return hwflow; -} -#endif - -#ifdef CONFIG_MODEM_SUPPORT -static int be_quiet = 0; -void disable_putc(void) -{ - be_quiet = 1; -} - -void enable_putc(void) -{ - be_quiet = 0; -} -#endif - - -/* - * Output a single byte to the serial port. - */ -void _serial_putc (const char c, const int dev_index) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); -#ifdef CONFIG_MODEM_SUPPORT - if (be_quiet) - return; -#endif - - /* wait for room in the tx FIFO */ - while (!(uart->UTRSTAT & 0x2)); - -#ifdef CONFIG_HWFLOW - /* Wait for CTS up */ - while(hwflow && !(uart->UMSTAT & 0x1)) - ; -#endif - - uart->UTXH = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} -#if defined(CONFIG_SERIAL_MULTI) -static inline void serial_putc_dev(unsigned int dev_index, const char c) -{ - _serial_putc(c, dev_index); -} -#else -void serial_putc(const char c) -{ - _serial_putc(c, UART_NR); -} -#endif - - -/* - * Test whether a character is in the RX buffer - */ -int _serial_tstc(const int dev_index) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); - - return uart->UTRSTAT & 0x1; -} -#if defined(CONFIG_SERIAL_MULTI) -static inline int -serial_tstc_dev(unsigned int dev_index) -{ - return _serial_tstc(dev_index); -} -#else -int serial_tstc(void) -{ - return _serial_tstc(UART_NR); -} -#endif - -void _serial_puts(const char *s, const int dev_index) -{ - while (*s) { - _serial_putc (*s++, dev_index); - } -} -#if defined(CONFIG_SERIAL_MULTI) -static inline void -serial_puts_dev(int dev_index, const char *s) -{ - _serial_puts(s, dev_index); -} -#else -void -serial_puts (const char *s) -{ - _serial_puts(s, UART_NR); -} -#endif - -#if defined(CONFIG_SERIAL_MULTI) -DECLARE_S3C_SERIAL_FUNCTIONS(0); -struct serial_device s3c24xx_serial0_device = - INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0", "S3UART1"); -DECLARE_S3C_SERIAL_FUNCTIONS(1); -struct serial_device s3c24xx_serial1_device = - INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1", "S3UART2"); -DECLARE_S3C_SERIAL_FUNCTIONS(2); -struct serial_device s3c24xx_serial2_device = - INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2", "S3UART3"); - -#endif /* CONFIG_SERIAL_MULTI */ - -#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/interrupts.c index 3ef4554..e5c77f7 100644 --- a/cpu/arm925t/interrupts.c +++ b/cpu/arm925t/interrupts.c @@ -35,29 +35,26 @@ #include <common.h> #include <arm925t.h> #include <configs/omap1510.h> +#include <asm/io.h> #define TIMER_LOAD_VAL 0xffffffff -/* macro to read the 32 bit timer */ -#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8)) - -static ulong timestamp; -static ulong lastdec; +static uint32_t timestamp; +static uint32_t lastdec; /* nothing really to do with interrupts, just starts up a counter. */ int interrupt_init (void) { - int32_t val; - /* Start the decrementer ticking down from 0xffffffff */ - *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; - val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT); - *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val; + __raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM); + __raw_writel(MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | + (CONFIG_SYS_PTV << MPUTIM_PTV_BIT), + CONFIG_SYS_TIMERBASE + CNTL_TIMER); /* init the timestamp and lastdec value */ reset_timer_masked(); - return (0); + return 0; } /* @@ -84,17 +81,17 @@ void udelay (unsigned long usec) { ulong tmo, tmp; - if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ - }else{ /* else small number, don't kill it prior to HZ multiply */ + } else { /* else small number, don't kill it prior to HZ multiply */ tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } tmp = get_timer (0); /* get current timestamp */ - if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ + if ((tmo + tmp + 1) < tmp) /* if setting this fordward will roll time stamp */ reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ else tmo += tmp; /* else, set advancing stamp wake up time */ @@ -106,13 +103,13 @@ void udelay (unsigned long usec) void reset_timer_masked (void) { /* reset time */ - lastdec = READ_TIMER; /* capure current decrementer value time */ + lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); timestamp = 0; /* start "advancing" time stamp from 0 */ } ulong get_timer_masked (void) { - ulong now = READ_TIMER; /* current tick value */ + uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); if (lastdec >= now) { /* normal mode (non roll) */ /* normal mode */ @@ -136,7 +133,7 @@ void udelay_masked (unsigned long usec) #ifdef CONFIG_INNOVATOROMAP1510 #define LOOPS_PER_MSEC 60 /* tuned on omap1510 */ volatile int i, time_remaining = LOOPS_PER_MSEC*usec; - for (i=time_remaining; i>0; i--) { } + for (i=time_remaining; i>0; i--) { } #else ulong tmo; @@ -145,7 +142,7 @@ void udelay_masked (unsigned long usec) if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ } else { /* else small number, don't kill it prior to HZ multiply */ tmo = usec * CONFIG_SYS_HZ; @@ -176,8 +173,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk (void) { - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; + return CONFIG_SYS_HZ; } diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index 0f77f40..ed24e65 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = timer.o ether.o lxt972.o dp83848.o i2c.o nand.o +COBJS = timer.o ether.o lxt972.o dp83848.o SOBJS = lowlevel_init.o reset.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm926ejs/davinci/i2c.c b/cpu/arm926ejs/davinci/i2c.c deleted file mode 100644 index 3ba20ef..0000000 --- a/cpu/arm926ejs/davinci/i2c.c +++ /dev/null @@ -1,334 +0,0 @@ -/* - * TI DaVinci (TMS320DM644x) I2C driver. - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * -------------------------------------------------------- - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#ifdef CONFIG_DRIVER_DAVINCI_I2C - -#include <i2c.h> -#include <asm/arch/hardware.h> -#include <asm/arch/i2c_defs.h> - -#define CHECK_NACK() \ - do {\ - if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\ - REG(I2C_CON) = 0;\ - return(1);\ - }\ - } while (0) - - -static int wait_for_bus(void) -{ - int stat, timeout; - - REG(I2C_STAT) = 0xffff; - - for (timeout = 0; timeout < 10; timeout++) { - if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) { - REG(I2C_STAT) = 0xffff; - return(0); - } - - REG(I2C_STAT) = stat; - udelay(50000); - } - - REG(I2C_STAT) = 0xffff; - return(1); -} - - -static int poll_i2c_irq(int mask) -{ - int stat, timeout; - - for (timeout = 0; timeout < 10; timeout++) { - udelay(1000); - stat = REG(I2C_STAT); - if (stat & mask) { - return(stat); - } - } - - REG(I2C_STAT) = 0xffff; - return(stat | I2C_TIMEOUT); -} - - -void flush_rx(void) -{ - int dummy; - - while (1) { - if (!(REG(I2C_STAT) & I2C_STAT_RRDY)) - break; - - dummy = REG(I2C_DRR); - REG(I2C_STAT) = I2C_STAT_RRDY; - udelay(1000); - } -} - - -void i2c_init(int speed, int slaveadd) -{ - u_int32_t div, psc; - - if (REG(I2C_CON) & I2C_CON_EN) { - REG(I2C_CON) = 0; - udelay (50000); - } - - psc = 2; - div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ - REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */ - REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */ - REG(I2C_SCLH) = div - REG(I2C_SCLL); - - REG(I2C_OA) = slaveadd; - REG(I2C_CNT) = 0; - - /* Interrupts must be enabled or I2C module won't work */ - REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | - I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE; - - /* Now enable I2C controller (get it out of reset) */ - REG(I2C_CON) = I2C_CON_EN; - - udelay(1000); -} - - -int i2c_probe(u_int8_t chip) -{ - int rc = 1; - - if (chip == REG(I2C_OA)) { - return(rc); - } - - REG(I2C_CON) = 0; - if (wait_for_bus()) {return(1);} - - /* try to read one byte from current (or only) address */ - REG(I2C_CNT) = 1; - REG(I2C_SA) = chip; - REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP); - udelay (50000); - - if (!(REG(I2C_STAT) & I2C_STAT_NACK)) { - rc = 0; - flush_rx(); - REG(I2C_STAT) = 0xffff; - } else { - REG(I2C_STAT) = 0xffff; - REG(I2C_CON) |= I2C_CON_STP; - udelay(20000); - if (wait_for_bus()) {return(1);} - } - - flush_rx(); - REG(I2C_STAT) = 0xffff; - REG(I2C_CNT) = 0; - return(rc); -} - - -int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) -{ - u_int32_t tmp; - int i; - - if ((alen < 0) || (alen > 2)) { - printf("%s(): bogus address length %x\n", __FUNCTION__, alen); - return(1); - } - - if (wait_for_bus()) {return(1);} - - if (alen != 0) { - /* Start address phase */ - tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; - REG(I2C_CNT) = alen; - REG(I2C_SA) = chip; - REG(I2C_CON) = tmp; - - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); - - CHECK_NACK(); - - switch (alen) { - case 2: - /* Send address MSByte */ - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = (addr >> 8) & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); - - CHECK_NACK(); - /* No break, fall through */ - case 1: - /* Send address LSByte */ - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = addr & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY); - - CHECK_NACK(); - - if (!(tmp & I2C_STAT_ARDY)) { - REG(I2C_CON) = 0; - return(1); - } - } - } - - /* Address phase is over, now read 'len' bytes and stop */ - tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; - REG(I2C_CNT) = len & 0xffff; - REG(I2C_SA) = chip; - REG(I2C_CON) = tmp; - - for (i = 0; i < len; i++) { - tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR); - - CHECK_NACK(); - - if (tmp & I2C_STAT_RRDY) { - buf[i] = REG(I2C_DRR); - } else { - REG(I2C_CON) = 0; - return(1); - } - } - - tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); - - CHECK_NACK(); - - if (!(tmp & I2C_STAT_SCD)) { - REG(I2C_CON) = 0; - return(1); - } - - flush_rx(); - REG(I2C_STAT) = 0xffff; - REG(I2C_CNT) = 0; - REG(I2C_CON) = 0; - - return(0); -} - - -int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) -{ - u_int32_t tmp; - int i; - - if ((alen < 0) || (alen > 2)) { - printf("%s(): bogus address length %x\n", __FUNCTION__, alen); - return(1); - } - if (len < 0) { - printf("%s(): bogus length %x\n", __FUNCTION__, len); - return(1); - } - - if (wait_for_bus()) {return(1);} - - /* Start address phase */ - tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP; - REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen; - REG(I2C_SA) = chip; - REG(I2C_CON) = tmp; - - switch (alen) { - case 2: - /* Send address MSByte */ - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); - - CHECK_NACK(); - - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = (addr >> 8) & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - /* No break, fall through */ - case 1: - /* Send address LSByte */ - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); - - CHECK_NACK(); - - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = addr & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - } - - for (i = 0; i < len; i++) { - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); - - CHECK_NACK(); - - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = buf[i]; - } else { - return(1); - } - } - - tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); - - CHECK_NACK(); - - if (!(tmp & I2C_STAT_SCD)) { - REG(I2C_CON) = 0; - return(1); - } - - flush_rx(); - REG(I2C_STAT) = 0xffff; - REG(I2C_CNT) = 0; - REG(I2C_CON) = 0; - - return(0); -} - -#endif /* CONFIG_DRIVER_DAVINCI_I2C */ diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c deleted file mode 100644 index 014e2b0..0000000 --- a/cpu/arm926ejs/davinci/nand.c +++ /dev/null @@ -1,475 +0,0 @@ -/* - * NAND driver for TI DaVinci based boards. - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * Based on Linux DaVinci NAND driver by TI. Original copyright follows: - */ - -/* - * - * linux/drivers/mtd/nand/nand_davinci.c - * - * NAND Flash Driver - * - * Copyright (C) 2006 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * ---------------------------------------------------------------------------- - * - * Overview: - * This is a device driver for the NAND flash device found on the - * DaVinci board which utilizes the Samsung k9k2g08 part. - * - Modifications: - ver. 1.0: Feb 2005, Vinod/Sudhakar - - - * - */ - -#include <common.h> -#include <asm/io.h> - -#ifdef CONFIG_SYS_USE_NAND -#if !defined(CONFIG_NAND_LEGACY) - -#include <nand.h> -#include <asm/arch/nand_defs.h> -#include <asm/arch/emif_defs.h> - -extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; - -static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; - - IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); - - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - IO_ADDR_W |= MASK_CLE; - if ( ctrl & NAND_ALE ) - IO_ADDR_W |= MASK_ALE; - this->IO_ADDR_W = (void __iomem *) IO_ADDR_W; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -/* Set WP on deselect, write enable on select */ -static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) -{ -#define GPIO_SET_DATA01 0x01c67018 -#define GPIO_CLR_DATA01 0x01c6701c -#define GPIO_NAND_WP (1 << 4) -#ifdef SONATA_BOARD_GPIOWP - if (chip < 0) { - REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP; - } else { - REG(GPIO_SET_DATA01) |= GPIO_NAND_WP; - } -#endif -} - -#ifdef CONFIG_SYS_NAND_HW_ECC -#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC -/* Linux-compatible ECC uses MTD defaults. */ -/* These layouts are not compatible with Linux or RBL/UBL. */ -#ifdef CONFIG_SYS_NAND_LARGEPAGE -static struct nand_ecclayout davinci_nand_ecclayout = { - .eccbytes = 12, - .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, - .oobfree = { - {.offset = 2, .length = 6}, - {.offset = 12, .length = 12}, - {.offset = 28, .length = 12}, - {.offset = 44, .length = 12}, - {.offset = 60, .length = 4} - } -}; -#elif defined(CONFIG_SYS_NAND_SMALLPAGE) -static struct nand_ecclayout davinci_nand_ecclayout = { - .eccbytes = 3, - .eccpos = {0, 1, 2}, - .oobfree = { - {.offset = 6, .length = 2}, - {.offset = 8, .length = 8} - } -}; -#else -#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!" -#endif -#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ - -static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) -{ - emifregs emif_addr; - int dummy; - - emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - - dummy = emif_addr->NANDF1ECC; - dummy = emif_addr->NANDF2ECC; - dummy = emif_addr->NANDF3ECC; - dummy = emif_addr->NANDF4ECC; - - emif_addr->NANDFCR |= (1 << 8); -} - -static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) -{ - u_int32_t ecc = 0; - emifregs emif_base_addr; - - emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - - if (region == 1) - ecc = emif_base_addr->NANDF1ECC; - else if (region == 2) - ecc = emif_base_addr->NANDF2ECC; - else if (region == 3) - ecc = emif_base_addr->NANDF3ECC; - else if (region == 4) - ecc = emif_base_addr->NANDF4ECC; - - return(ecc); -} - -static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) -{ - u_int32_t tmp; -#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC - /* - * This is not how you should read ECCs on large page Davinci devices. - * The region parameter gets you ECCs for flash chips on different chip - * selects, not the 4x512 byte pages in a 2048 byte page. - * - * Preserved for backwards compatibility though. - */ - - int region, n; - struct nand_chip *this = mtd->priv; - - n = (this->ecc.size/512); - - region = 1; - while (n--) { - tmp = nand_davinci_readecc(mtd, region); - *ecc_code++ = tmp; - *ecc_code++ = tmp >> 16; - *ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0); - region++; - } -#else - const int region = 1; - - tmp = nand_davinci_readecc(mtd, region); - - /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits - * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */ - tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4); - - /* Invert so that erased block ECC is correct */ - tmp = ~tmp; - - *ecc_code++ = tmp; - *ecc_code++ = tmp >> 8; - *ecc_code++ = tmp >> 16; -#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ - return(0); -} - -#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC -static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf) -{ - u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8); - - ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); - ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); - ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); -} - -static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data) -{ - u_int32_t i; - u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; - u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8]; - u_int8_t ecc_bit[24]; - u_int8_t ecc_sum = 0; - u_int8_t find_bit = 0; - u_int32_t find_byte = 0; - int is_ecc_ff; - - is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff)); - - nand_davinci_gen_true_ecc(ecc_nand); - nand_davinci_gen_true_ecc(ecc_calc); - - for (i = 0; i <= 2; i++) { - *(ecc_nand + i) = ~(*(ecc_nand + i)); - *(ecc_calc + i) = ~(*(ecc_calc + i)); - } - - for (i = 0; i < 8; i++) { - tmp0_bit[i] = *ecc_nand % 2; - *ecc_nand = *ecc_nand / 2; - } - - for (i = 0; i < 8; i++) { - tmp1_bit[i] = *(ecc_nand + 1) % 2; - *(ecc_nand + 1) = *(ecc_nand + 1) / 2; - } - - for (i = 0; i < 8; i++) { - tmp2_bit[i] = *(ecc_nand + 2) % 2; - *(ecc_nand + 2) = *(ecc_nand + 2) / 2; - } - - for (i = 0; i < 8; i++) { - comp0_bit[i] = *ecc_calc % 2; - *ecc_calc = *ecc_calc / 2; - } - - for (i = 0; i < 8; i++) { - comp1_bit[i] = *(ecc_calc + 1) % 2; - *(ecc_calc + 1) = *(ecc_calc + 1) / 2; - } - - for (i = 0; i < 8; i++) { - comp2_bit[i] = *(ecc_calc + 2) % 2; - *(ecc_calc + 2) = *(ecc_calc + 2) / 2; - } - - for (i = 0; i< 6; i++) - ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; - - for (i = 0; i < 8; i++) - ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; - - for (i = 0; i < 8; i++) - ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; - - ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; - ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; - - for (i = 0; i < 24; i++) - ecc_sum += ecc_bit[i]; - - switch (ecc_sum) { - case 0: - /* Not reached because this function is not called if - ECC values are equal */ - return 0; - case 1: - /* Uncorrectable error */ - MTDDEBUG (MTD_DEBUG_LEVEL0, - "ECC UNCORRECTED_ERROR 1\n"); - return(-1); - case 12: - /* Correctable error */ - find_byte = (ecc_bit[23] << 8) + - (ecc_bit[21] << 7) + - (ecc_bit[19] << 6) + - (ecc_bit[17] << 5) + - (ecc_bit[15] << 4) + - (ecc_bit[13] << 3) + - (ecc_bit[11] << 2) + - (ecc_bit[9] << 1) + - ecc_bit[7]; - - find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; - - MTDDEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC " - "error at offset: %d, bit: %d\n", - find_byte, find_bit); - - page_data[find_byte] ^= (1 << find_bit); - - return(0); - default: - if (is_ecc_ff) { - if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0) - return(0); - } - MTDDEBUG (MTD_DEBUG_LEVEL0, - "UNCORRECTED_ERROR default\n"); - return(-1); - } -} -#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ - -static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) -{ - struct nand_chip *this = mtd->priv; -#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC - int block_count = 0, i, rc; - - block_count = (this->ecc.size/512); - for (i = 0; i < block_count; i++) { - if (memcmp(read_ecc, calc_ecc, 3) != 0) { - rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat); - if (rc < 0) { - return(rc); - } - } - read_ecc += 3; - calc_ecc += 3; - dat += 512; - } -#else - u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) | - (read_ecc[2] << 16); - u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) | - (calc_ecc[2] << 16); - u_int32_t diff = ecc_calc ^ ecc_nand; - - if (diff) { - if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) { - /* Correctable error */ - if ((diff >> (12 + 3)) < this->ecc.size) { - uint8_t find_bit = 1 << ((diff >> 12) & 7); - uint32_t find_byte = diff >> (12 + 3); - - dat[find_byte] ^= find_bit; - MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single " - "bit ECC error at offset: %d, bit: " - "%d\n", find_byte, find_bit); - return 1; - } else { - return -1; - } - } else if (!(diff & (diff - 1))) { - /* Single bit ECC error in the ECC itself, - nothing to fix */ - MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in " - "ECC.\n"); - return 1; - } else { - /* Uncorrectable error */ - MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); - return -1; - } - } -#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ - return(0); -} -#endif /* CONFIG_SYS_NAND_HW_ECC */ - -static int nand_davinci_dev_ready(struct mtd_info *mtd) -{ - emifregs emif_addr; - - emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - - return(emif_addr->NANDFSR & 0x1); -} - -static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this) -{ - while(!nand_davinci_dev_ready(mtd)) {;} - *NAND_CE0CLE = NAND_STATUS; - return(*NAND_CE0DATA); -} - -static void nand_flash_init(void) -{ - u_int32_t acfg1 = 0x3ffffffc; - u_int32_t acfg2 = 0x3ffffffc; - u_int32_t acfg3 = 0x3ffffffc; - u_int32_t acfg4 = 0x3ffffffc; - emifregs emif_regs; - - /*------------------------------------------------------------------* - * NAND FLASH CHIP TIMEOUT @ 459 MHz * - * * - * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz * - * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * - * * - *------------------------------------------------------------------*/ - acfg1 = 0 - | (0 << 31 ) /* selectStrobe */ - | (0 << 30 ) /* extWait */ - | (1 << 26 ) /* writeSetup 10 ns */ - | (3 << 20 ) /* writeStrobe 40 ns */ - | (1 << 17 ) /* writeHold 10 ns */ - | (1 << 13 ) /* readSetup 10 ns */ - | (5 << 7 ) /* readStrobe 60 ns */ - | (1 << 4 ) /* readHold 10 ns */ - | (3 << 2 ) /* turnAround ?? ns */ - | (0 << 0 ) /* asyncSize 8-bit bus */ - ; - - emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - - emif_regs->AWCCR |= 0x10000000; - emif_regs->AB1CR = acfg1; /* 0x08244128 */; - emif_regs->AB2CR = acfg2; - emif_regs->AB3CR = acfg3; - emif_regs->AB4CR = acfg4; - emif_regs->NANDFCR = 0x00000101; -} - -int board_nand_init(struct nand_chip *nand) -{ - nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA; - nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA; - nand->chip_delay = 0; - nand->select_chip = nand_davinci_select_chip; -#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT - nand->options = NAND_USE_FLASH_BBT; -#endif -#ifdef CONFIG_SYS_NAND_HW_ECC - nand->ecc.mode = NAND_ECC_HW; -#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC - nand->ecc.layout = &davinci_nand_ecclayout; -#ifdef CONFIG_SYS_NAND_LARGEPAGE - nand->ecc.size = 2048; - nand->ecc.bytes = 12; -#elif defined(CONFIG_SYS_NAND_SMALLPAGE) - nand->ecc.size = 512; - nand->ecc.bytes = 3; -#else -#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!" -#endif -#else - nand->ecc.size = 512; - nand->ecc.bytes = 3; -#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ - nand->ecc.calculate = nand_davinci_calculate_ecc; - nand->ecc.correct = nand_davinci_correct_data; - nand->ecc.hwctl = nand_davinci_enable_hwecc; -#else - nand->ecc.mode = NAND_ECC_SOFT; -#endif /* CONFIG_SYS_NAND_HW_ECC */ - - /* Set address of hardware control function */ - nand->cmd_ctrl = nand_davinci_hwcontrol; - - nand->dev_ready = nand_davinci_dev_ready; - nand->waitfunc = nand_davinci_waitfunc; - - nand_flash_init(); - - return(0); -} - -#else -#error "U-Boot legacy NAND support not available for DaVinci chips" -#endif -#endif /* CONFIG_SYS_USE_NAND */ diff --git a/cpu/arm926ejs/omap/timer.c b/cpu/arm926ejs/omap/timer.c index 49e74ab..bedc2e7 100644 --- a/cpu/arm926ejs/omap/timer.c +++ b/cpu/arm926ejs/omap/timer.c @@ -52,7 +52,7 @@ int timer_init (void) /* Start the decrementer ticking down from 0xffffffff */ *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; - val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT); + val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT); *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val; /* init the timestamp and lastdec value */ diff --git a/cpu/arm_cortexa8/omap3/interrupts.c b/cpu/arm_cortexa8/omap3/interrupts.c index 9e9817d..5d9c4e3 100644 --- a/cpu/arm_cortexa8/omap3/interrupts.c +++ b/cpu/arm_cortexa8/omap3/interrupts.c @@ -175,7 +175,7 @@ int interrupt_init(void) /* start the counter ticking up, reload value on overflow */ writel(TIMER_LOAD_VAL, &timer_base->tldr); /* enable timer */ - writel((CONFIG_SYS_PVT << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, + writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, &timer_base->tclr); reset_timer_masked(); /* init the timestamp and lastinc value */ diff --git a/cpu/s3c44b0/Makefile b/cpu/s3c44b0/Makefile index 790faeb..ae909a6 100644 --- a/cpu/s3c44b0/Makefile +++ b/cpu/s3c44b0/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = serial.o interrupts.o cpu.o +COBJS = cache.o cpu.o interrupts.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/s3c44b0/cache.c b/cpu/s3c44b0/cache.c new file mode 100644 index 0000000..bc10171 --- /dev/null +++ b/cpu/s3c44b0/cache.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/hardware.h> + +static void s3c44b0_flush_cache(void) +{ + volatile int i; + /* flush cycle */ + for(i=0x10002000;i<0x10004800;i+=16) + { + *((int *)i)=0x0; + } +} + +void icache_enable (void) +{ + ulong reg; + + s3c44b0_flush_cache(); + + /* + Init cache + Non-cacheable area (everything outside RAM) + 0x0000:0000 - 0x0C00:0000 + */ + NCACHBE0 = 0xC0000000; + NCACHBE1 = 0x00000000; + + /* + Enable chache + */ + reg = SYSCFG; + reg |= 0x00000006; /* 8kB */ + SYSCFG = reg; +} + +void icache_disable (void) +{ + ulong reg; + + reg = SYSCFG; + reg &= ~0x00000006; /* 8kB */ + SYSCFG = reg; +} + +int icache_status (void) +{ + return 0; +} + +void dcache_enable (void) +{ + icache_enable(); +} + +void dcache_disable (void) +{ + icache_disable(); +} + +int dcache_status (void) +{ + return dcache_status(); +} + diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c index 2960f2f..e4cdb82 100644 --- a/cpu/s3c44b0/cpu.c +++ b/cpu/s3c44b0/cpu.c @@ -32,17 +32,6 @@ #include <command.h> #include <asm/hardware.h> -static void s3c44b0_flush_cache(void) -{ - volatile int i; - /* flush cycle */ - for(i=0x10002000;i<0x10004800;i+=16) - { - *((int *)i)=0x0; - } -} - - int cpu_init (void) { icache_enable(); @@ -92,422 +81,3 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /*NOTREACHED*/ return (0); } - -void icache_enable (void) -{ - ulong reg; - - s3c44b0_flush_cache(); - - /* - Init cache - Non-cacheable area (everything outside RAM) - 0x0000:0000 - 0x0C00:0000 - */ - NCACHBE0 = 0xC0000000; - NCACHBE1 = 0x00000000; - - /* - Enable chache - */ - reg = SYSCFG; - reg |= 0x00000006; /* 8kB */ - SYSCFG = reg; -} - -void icache_disable (void) -{ - ulong reg; - - reg = SYSCFG; - reg &= ~0x00000006; /* 8kB */ - SYSCFG = reg; -} - -int icache_status (void) -{ - return 0; -} - -void dcache_enable (void) -{ - icache_enable(); -} - -void dcache_disable (void) -{ - icache_disable(); -} - -int dcache_status (void) -{ - return dcache_status(); -} - -/* - RTC stuff -*/ -#include <rtc.h> -#ifndef BCD2HEX - #define BCD2HEX(n) ((n>>4)*10+(n&0x0f)) -#endif -#ifndef HEX2BCD - #define HEX2BCD(x) ((((x) / 10) << 4) + (x) % 10) -#endif - -int rtc_get (struct rtc_time* tm) -{ - RTCCON |= 1; - tm->tm_year = BCD2HEX(BCDYEAR); - tm->tm_mon = BCD2HEX(BCDMON); - tm->tm_wday = BCD2HEX(BCDDATE); - tm->tm_mday = BCD2HEX(BCDDAY); - tm->tm_hour = BCD2HEX(BCDHOUR); - tm->tm_min = BCD2HEX(BCDMIN); - tm->tm_sec = BCD2HEX(BCDSEC); - - if (tm->tm_sec==0) { - /* we have to re-read the rtc data because of the "one second deviation" problem */ - /* see RTC datasheet for more info about it */ - tm->tm_year = BCD2HEX(BCDYEAR); - tm->tm_mon = BCD2HEX(BCDMON); - tm->tm_mday = BCD2HEX(BCDDAY); - tm->tm_wday = BCD2HEX(BCDDATE); - tm->tm_hour = BCD2HEX(BCDHOUR); - tm->tm_min = BCD2HEX(BCDMIN); - tm->tm_sec = BCD2HEX(BCDSEC); - } - - RTCCON &= ~1; - - if(tm->tm_year >= 70) - tm->tm_year += 1900; - else - tm->tm_year += 2000; - - return 0; -} - -int rtc_set (struct rtc_time* tm) -{ - if(tm->tm_year < 2000) - tm->tm_year -= 1900; - else - tm->tm_year -= 2000; - - RTCCON |= 1; - BCDYEAR = HEX2BCD(tm->tm_year); - BCDMON = HEX2BCD(tm->tm_mon); - BCDDAY = HEX2BCD(tm->tm_mday); - BCDDATE = HEX2BCD(tm->tm_wday); - BCDHOUR = HEX2BCD(tm->tm_hour); - BCDMIN = HEX2BCD(tm->tm_min); - BCDSEC = HEX2BCD(tm->tm_sec); - RTCCON &= 1; - - return 0; -} - -void rtc_reset (void) -{ - RTCCON |= 1; - BCDYEAR = 0; - BCDMON = 0; - BCDDAY = 0; - BCDDATE = 0; - BCDHOUR = 0; - BCDMIN = 0; - BCDSEC = 0; - RTCCON &= 1; -} - - -/* - I2C stuff -*/ - -/* - * Initialization, must be called once on start up, may be called - * repeatedly to change the speed and slave addresses. - */ -void i2c_init(int speed, int slaveaddr) -{ - /* - setting up I2C support - */ - unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF; - - save_F = PCONF; - save_PF = PUPF; - - rPCONF = ((save_F & ~(0xF))| 0xa); - rPUPF = (save_PF | 0x3); - PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/ - PUPF = rPUPF; /* Disable pull-up */ - - /* Configuring pin for WC pin of EEprom */ - rPCONA = PCONA; - rPCONA &= ~(1<<9); - PCONA = rPCONA; - - rPDATA = PDATA; - rPDATA &= ~(1<<9); - PDATA = rPDATA; - - /* - Enable ACK, IICCLK=MCLK/16, enable interrupt - 75MHz/16/(12+1) = 390625 Hz - */ - rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC); - IICCON = rIICCON; - - IICADD = slaveaddr; -} - -/* - * Probe the given I2C chip address. Returns 0 if a chip responded, - * not 0 on failure. - */ -int i2c_probe(uchar chip) -{ - /* - not implemented - */ - - printf("i2c_probe chip %d\n", (int) chip); - return -1; -} - -/* - * Read/Write interface: - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ - -#define S3C44B0X_rIIC_INTPEND (1<<4) -#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0) -#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5) -#define S3C44B0_IIC_TIMEOUT 100 - -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - - int k, j, temp; - u32 rIICSTAT; - - /* - send the device offset - */ - - rIICSTAT = 0xD0; - IICSTAT = rIICSTAT; - - IICDS = chip; /* this is a write operation... */ - - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - /* wait and check ACK */ - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - IICDS = addr; - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - /* - now we can start with the read operation... - */ - - IICDS = chip | 0x01; /* this is a read operation... */ - - rIICSTAT = 0x90; /*master recv*/ - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - for (j=0; j<len-1; j++) { - - /*clear pending bit to resume */ - - temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); - IICCON = temp; - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - - buffer[j] = IICDS; /*save readed data*/ - - } /*end for(j)*/ - - /* - reading the last data - unset ACK generation - */ - temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7)); - IICCON = temp; - - /* wait but NOT check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - buffer[j] = IICDS; /*save readed data*/ - - rIICSTAT = 0x90; /*master recv*/ - - /* Write operation Terminate sending STOP */ - IICSTAT = rIICSTAT; - /*Clear Int Pending Bit to RESUME*/ - temp = IICCON; - IICCON = temp & (~S3C44B0X_rIIC_INTPEND); - - IICCON = IICCON | (1<<7); /*restore ACK generation*/ - - return 0; -} - -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - int j, k; - u32 rIICSTAT, temp; - - - /* - send the device offset - */ - - rIICSTAT = 0xD0; - IICSTAT = rIICSTAT; - - IICDS = chip; /* this is a write operation... */ - - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - IICDS = addr; - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - /* - now we can start with the read write operation - */ - for (j=0; j<len; j++) { - - IICDS = buffer[j]; /*prerare data to write*/ - - /*clear pending bit to resume*/ - - temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); - IICCON = temp; - - /* wait but NOT check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - - udelay(2000); - } - - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - } /* end for(j) */ - - /* sending stop to terminate */ - rIICSTAT = 0xD0; /*master send*/ - IICSTAT = rIICSTAT; - /*Clear Int Pending Bit to RESUME*/ - temp = IICCON; - IICCON = temp & (~S3C44B0X_rIIC_INTPEND); - - return 0; -} diff --git a/cpu/s3c44b0/serial.c b/cpu/s3c44b0/serial.c deleted file mode 100644 index 95d0266..0000000 --- a/cpu/s3c44b0/serial.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> -#include <asm/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* flush serial input queue. returns 0 on success or negative error - * number otherwise - */ -static int serial_flush_input(void) -{ - volatile u32 tmp; - - /* keep on reading as long as the receiver is not empty */ - while(UTRSTAT0&0x01) { - tmp = REGB(URXH0); - } - - return 0; -} - - -/* flush output queue. returns 0 on success or negative error number - * otherwise - */ -static int serial_flush_output(void) -{ - /* wait until the transmitter is no longer busy */ - while(!(UTRSTAT0 & 0x02)) { - } - - return 0; -} - - -void serial_setbrg (void) -{ - u32 divisor = 0; - - /* get correct divisor */ - switch(gd->baudrate) { - - case 1200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 3124; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 3905; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 9600: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 390; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 487; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 19200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 194; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 243; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 38400: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 97; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 121; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - - case 57600: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 64; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 80; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - - case 115200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 32; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 40; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - } - - serial_flush_output(); - serial_flush_input(); - UFCON0 = 0x0; - ULCON0 = 0x03; - UCON0 = 0x05; - UBRDIV0 = divisor; - - UFCON1 = 0x0; - ULCON1 = 0x03; - UCON1 = 0x05; - UBRDIV1 = divisor; - - for(divisor=0; divisor<100; divisor++) { - /* NOP */ - } -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - /* wait for room in the transmit FIFO */ - while(!(UTRSTAT0 & 0x02)); - - UTXH0 = (unsigned char)c; - - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n') - serial_putc('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_tstc (void) -{ - return (UTRSTAT0 & 0x01); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - int rv; - - for(;;) { - rv = serial_tstc(); - - if(rv > 0) - return URXH0; - } -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} diff --git a/cpu/sa1100/Makefile b/cpu/sa1100/Makefile index 790faeb..fd696f7 100644 --- a/cpu/sa1100/Makefile +++ b/cpu/sa1100/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = serial.o interrupts.o cpu.o +COBJS = interrupts.o cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/sa1100/serial.c b/cpu/sa1100/serial.c deleted file mode 100644 index 5d18875..0000000 --- a/cpu/sa1100/serial.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> -#include <SA-1100.h> - -DECLARE_GLOBAL_DATA_PTR; - -void serial_setbrg (void) -{ - unsigned int reg = 0; - - if (gd->baudrate == 1200) - reg = 191; - else if (gd->baudrate == 9600) - reg = 23; - else if (gd->baudrate == 19200) - reg = 11; - else if (gd->baudrate == 38400) - reg = 5; - else if (gd->baudrate == 57600) - reg = 3; - else if (gd->baudrate == 115200) - reg = 1; - else - hang (); - -#ifdef CONFIG_SERIAL1 - /* SA1110 uart function */ - Ser1SDCR0 |= SDCR0_SUS; - - /* Wait until port is ready ... */ - while(Ser1UTSR1 & UTSR1_TBY) {} - - /* init serial serial 1 */ - Ser1UTCR3 = 0x00; - Ser1UTSR0 = 0xff; - Ser1UTCR0 = ( UTCR0_1StpBit | UTCR0_8BitData ); - Ser1UTCR1 = 0; - Ser1UTCR2 = (u32)reg; - Ser1UTCR3 = ( UTCR3_RXE | UTCR3_TXE ); -#elif defined(CONFIG_SERIAL3) - /* Wait until port is ready ... */ - while (Ser3UTSR1 & UTSR1_TBY) { - } - - /* init serial serial 3 */ - Ser3UTCR3 = 0x00; - Ser3UTSR0 = 0xff; - Ser3UTCR0 = (UTCR0_1StpBit | UTCR0_8BitData); - Ser3UTCR1 = 0; - Ser3UTCR2 = (u32) reg; - Ser3UTCR3 = (UTCR3_RXE | UTCR3_TXE); -#else -#error "Bad: you didn't configured serial ..." -#endif -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ -#ifdef CONFIG_SERIAL1 - /* wait for room in the tx FIFO on SERIAL1 */ - while ((Ser1UTSR0 & UTSR0_TFS) == 0); - - Ser1UTDR = c; -#elif defined(CONFIG_SERIAL3) - /* wait for room in the tx FIFO on SERIAL3 */ - while ((Ser3UTSR0 & UTSR0_TFS) == 0); - - Ser3UTDR = c; -#endif - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_tstc (void) -{ -#ifdef CONFIG_SERIAL1 - return Ser1UTSR1 & UTSR1_RNE; -#elif defined(CONFIG_SERIAL3) - return Ser3UTSR1 & UTSR1_RNE; -#endif -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ -#ifdef CONFIG_SERIAL1 - while (!(Ser1UTSR1 & UTSR1_RNE)); - - return (char) Ser1UTDR & 0xff; -#elif defined(CONFIG_SERIAL3) - while (!(Ser3UTSR1 & UTSR1_RNE)); - - return (char) Ser3UTDR & 0xff; -#endif -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} |