diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm720t/cpu.c | 171 | ||||
| -rw-r--r-- | cpu/arm720t/interrupts.c | 60 | ||||
| -rw-r--r-- | cpu/arm720t/serial.c | 32 | ||||
| -rw-r--r-- | cpu/arm720t/serial_netarm.c | 3 | ||||
| -rw-r--r-- | cpu/arm720t/start.S | 46 | ||||
| -rw-r--r-- | cpu/mpc824x/cpu_init.c | 331 |
6 files changed, 403 insertions, 240 deletions
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 0ad5481..58eab4e 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -33,51 +33,7 @@ #include <common.h> #include <command.h> #include <clps7111.h> - -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1(void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - /* printf("p15/c1 is = %08lx\n", value); */ - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1(unsigned long value) -{ - /* printf("write %08lx to p15/c1\n", value); */ - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1(); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_IDC (1<<2) /* icache and/or dcache off/on */ -#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ +#include <asm/hardware.h> int cpu_init (void) { @@ -103,12 +59,11 @@ int cleanup_before_linux (void) * and we set the CPU-speed to 73 MHz - see start.S for details */ +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) unsigned long i; disable_interrupts (); -#ifdef CONFIG_NETARM - return 0; -#endif + /* turn off I-cache */ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); i &= ~0x1000; @@ -116,11 +71,16 @@ int cleanup_before_linux (void) /* flush I-cache */ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); - #ifdef CONFIG_ARM7_REVD /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; #endif +#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) + disable_interrupts (); + /* Nothing more needed */ +#else +#error No cleanup_before_linux() defined for this CPU type +#endif return 0; } @@ -134,6 +94,57 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); } +/* + * Instruction and Data cache enable and disable functions + * + */ + +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1(void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + /* printf("p15/c1 is = %08lx\n", value); */ + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1(unsigned long value) +{ + /* printf("write %08lx to p15/c1\n", value); */ + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1(); +} + +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++); +} + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_IDC (1<<2) /* icache and/or dcache off/on */ +#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ + void icache_enable (void) { ulong reg; @@ -179,3 +190,65 @@ int dcache_status (void) { return (read_p15_c1 () & C1_IDC) != 0; } + +#elif defined(CONFIG_S3C4510B) + +void icache_enable (void) +{ + s32 i; + + /* disable all cache bits */ + CLR_REG( REG_SYSCFG, 0x3F); + + /* 8KB cache, write enable */ + SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); + + /* clear TAG RAM bits */ + for ( i = 0; i < 256; i++) + PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); + + /* clear SET0 RAM */ + for(i=0; i < 1024; i++) + PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); + + /* clear SET1 RAM */ + for(i=0; i < 1024; i++) + PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); + + /* enable cache */ + SET_REG( REG_SYSCFG, CACHE_ENABLE); + +} + +void icache_disable (void) +{ + /* disable all cache bits */ + CLR_REG( REG_SYSCFG, 0x3F); +} + +int icache_status (void) +{ + return GET_REG( REG_SYSCFG) & CACHE_ENABLE; +} + +void dcache_enable (void) +{ + /* we don't have seperate instruction/data caches */ + icache_enable(); +} + +void dcache_disable (void) +{ + /* we don't have seperate instruction/data caches */ + icache_disable(); +} + +int dcache_status (void) +{ + /* we don't have seperate instruction/data caches */ + return icache_status(); +} + +#else +#error No icache/dcache enable/disable functions defined for this CPU type +#endif diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index 67e581a..485443f 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -28,11 +28,8 @@ #include <common.h> #include <clps7111.h> - #include <asm/proc-armv/ptrace.h> -#ifdef CONFIG_NETARM -#include <asm/arch/netarm_registers.h> -#endif +#include <asm/hardware.h> extern void reset_cpu(ulong addr); @@ -187,7 +184,8 @@ static ulong lastdec; int interrupt_init (void) { -#ifdef CONFIG_NETARM + +#if defined(CONFIG_NETARM) /* disable all interrupts */ IRQEN = 0; @@ -198,7 +196,7 @@ int interrupt_init (void) /* set timer 2 counter */ lastdec = TIMER_LOAD_VAL; -#else +#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) /* disable all interrupts */ IO_INTMR1 = 0; @@ -210,6 +208,11 @@ int interrupt_init (void) /* set timer 1 counter */ lastdec = IO_TC1D = TIMER_LOAD_VAL; +#elif defined(CONFIG_S3C4510B) + /* Nothing to do, interrupts not supported */ + lastdec = 0; +#else +#error No interrupt_init() defined for this CPU type #endif timestamp = 0; @@ -220,6 +223,9 @@ int interrupt_init (void) * timer without interrupts */ + +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) + void reset_timer (void) { reset_timer_masked (); @@ -285,3 +291,45 @@ void udelay_masked (unsigned long usec) while (get_timer_masked () < tmo) /*NOP*/; } + +#elif defined(CONFIG_S3C4510B) + +#define TMR_OFFSET (0x1000) + +void udelay (unsigned long usec) +{ + u32 rDATA; + + rDATA = t_data_us(usec); + + /* Stop timer 0 */ + CLR_REG( REG_TMOD, TM0_RUN); + + /* Configure for toggle mode */ + SET_REG( REG_TMOD, TM0_TOGGLE); + + /* Load Timer data register with count down value plus offset */ + PUT_REG( REG_TDATA0, rDATA + TMR_OFFSET); + + /* Clear timer counter register */ + PUT_REG( REG_TCNT0, 0x0); + + /* Start timer -- count down timer */ + SET_REG( REG_TMOD, TM0_RUN); + + /* spin during count down */ + while ( GET_REG( REG_TCNT0) > TMR_OFFSET); + + /* Stop timer */ + CLR_REG( REG_TMOD, TM0_RUN); + +} + +ulong get_timer (ulong base) +{ + return (0xFFFFFFFF - GET_REG( REG_TCNT1)) - base; +} + +#else +#error Timer routines not defined for this CPU type +#endif diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c index 5c6a0cc..a5da4b7 100644 --- a/cpu/arm720t/serial.c +++ b/cpu/arm720t/serial.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002-2004 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> * * (C) Copyright 2002 @@ -29,9 +29,10 @@ */ #include <common.h> -#include <clps7111.h> -#ifndef CONFIG_NETARM +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) + +#include <clps7111.h> void serial_setbrg (void) { @@ -39,20 +40,15 @@ void serial_setbrg (void) unsigned int reg = 0; - if (gd->baudrate == 1200) - reg = 191; - else if (gd->baudrate == 9600) - reg = 23; - else if (gd->baudrate == 19200) - reg = 11; - else if (gd->baudrate == 38400) - reg = 5; - else if (gd->baudrate == 57600) - reg = 3; - else if (gd->baudrate == 115200) - reg = 1; - else - hang (); + switch (gd->baudrate) { + case 1200: reg = 191; break; + case 9600: reg = 23; break; + case 19200: reg = 11; break; + case 38400: reg = 5; break; + case 57600: reg = 3; break; + case 115200: reg = 1; break; + default: hang (); break; + } /* init serial serial 1,2 */ IO_SYSCON1 = SYSCON1_UART1EN; @@ -127,4 +123,4 @@ serial_puts (const char *s) } } -#endif /* CONFIG_NETARM */ +#endif /* defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) */ diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c index 8cfe049..56cdb0a 100644 --- a/cpu/arm720t/serial_netarm.c +++ b/cpu/arm720t/serial_netarm.c @@ -29,10 +29,11 @@ */ #include <common.h> -#include <asm/arch/netarm_registers.h> #ifdef CONFIG_NETARM +#include <asm/hardware.h> + #define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA)) #define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB)) diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S index f6ae9d6..15b9a05 100644 --- a/cpu/arm720t/start.S +++ b/cpu/arm720t/start.S @@ -26,9 +26,7 @@ #include <config.h> #include <version.h> -#ifdef CONFIG_NETARM -#include <asm/arch/netarm_registers.h> -#endif +#include <asm/hardware.h> /* ************************************************************************* @@ -166,7 +164,6 @@ clbss_l:str r2, [r0] /* clear loop... */ _start_armboot: .word start_armboot - /* ************************************************************************* * @@ -178,6 +175,7 @@ _start_armboot: .word start_armboot ************************************************************************* */ +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) /* Interupt-Controller base addresses */ INTMR1: .word 0x80000280 @ 32 bit size @@ -195,8 +193,11 @@ SYSCON3: .word 0x80002200 #define CLKCTL_49 0x4 /* 49.152 MHz */ #define CLKCTL_73 0x6 /* 73.728 MHz */ +#endif + cpu_init_crit: -#ifndef CONFIG_NETARM +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) + /* * mask all IRQs by clearing all bits in the INTMRs */ @@ -223,7 +224,7 @@ cpu_init_crit: bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM) orr r0, r0, #0x00000002 @ set bit 2 (A) Align mcr p15,0,r0,c1,c0 -#else /* CONFIG_NETARM */ +#elif defined(CONFIG_NETARM) /* * prior to software reset : need to set pin PORTC4 to be *HRESET */ @@ -270,7 +271,26 @@ cpu_init_crit: mov r1, #0 ldr r0, =NETARM_GEN_MODULE_BASE str r1, [r0, #+NETARM_GEN_INTR_ENABLE] -#endif /* CONFIG_NETARM */ + +#elif defined(CONFIG_S3C4510B) + + /* + * Mask off all IRQ sources + */ + ldr r1, =REG_INTMASK + ldr r0, =0x3FFFFF + str r0, [r1] + + /* + * Disable Cache + */ + ldr r0, =REG_SYSCFG + ldr r1, =0x83ffffa0 /* cache-disabled */ + str r1, [r0] + +#else +#error No cpu_init_crit() defined for current CPU type +#endif #ifdef CONFIG_ARM7_REVD /* set clock speed */ @@ -462,10 +482,10 @@ fiq: #endif +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) .align 5 .globl reset_cpu reset_cpu: -#ifndef CONFIG_NETARM mov ip, #0 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) @@ -474,7 +494,10 @@ reset_cpu: bic ip, ip, #0x2100 @ ..v....s........ mcr p15, 0, ip, c1, c0, 0 @ ctrl register mov pc, r0 -#else +#elif defined(CONFIG_NETARM) + .align 5 +.globl reset_cpu +reset_cpu: ldr r1, =NETARM_MEM_MODULE_BASE ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR] ldr r1, =0xFFFFF000 @@ -491,4 +514,9 @@ reset_cpu: ldr r1, =NETARM_GEN_SW_SVC_RESETB str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] mov pc, r0 +#elif defined(CONFIG_S3C4510B) +/* Nothing done here as reseting the CPU is board specific, depending + * on external peripherals such as watchdog timers, etc. */ +#else +#error No reset_cpu() defined for current CPU type #endif diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c index 3b5fb79..08f5c4a 100644 --- a/cpu/mpc824x/cpu_init.c +++ b/cpu/mpc824x/cpu_init.c @@ -75,63 +75,80 @@ cpu_init_f (void) */ #define M_CONFIG_WRITE_HALFWORD( addr, data ) \ - __asm__ __volatile__( \ - " \ - stw %2,0(%0)\n \ - sync\n \ - sth %3,2(%1)\n \ - sync\n \ - " \ - : /* no output */ \ - : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \ - "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \ - ); - - M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000); + __asm__ __volatile__(" \ + stw %2,0(%0)\n \ + sync\n \ + sth %3,2(%1)\n \ + sync\n \ + " \ + : /* no output */ \ + : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \ + "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \ + ); + + M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000); #endif - CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */ + CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */ + + /* + * Note that although this bit is cleared after a hard reset, it + * must be explicitly set and then cleared by software during + * initialization in order to guarantee correct operation of the + * DLL and the SDRAM_CLK[0:3] signals (if they are used). + */ + CONFIG_READ_BYTE (AMBOR, val); + CONFIG_WRITE_BYTE(AMBOR, val & 0xDF); + CONFIG_WRITE_BYTE(AMBOR, val | 0x20); + CONFIG_WRITE_BYTE(AMBOR, val & 0xDF); +#ifdef CONFIG_MPC8245 + /* silicon bug 28 MPC8245 */ + CONFIG_READ_BYTE(AMBOR,val); + CONFIG_WRITE_BYTE(AMBOR,val|0x1); + + CONFIG_READ_BYTE(PCMBCR,val); + /* in order not to corrupt data which is being read over the PCI bus + * with the PPC as master, we need to reduce the number of PCMRBs to 1, + * 4.11 in the processor user manual + * */ - /* - * Note that although this bit is cleared after a hard reset, it - * must be explicitly set and then cleared by software during - * initialization in order to guarantee correct operation of the - * DLL and the SDRAM_CLK[0:3] signals (if they are used). - */ - CONFIG_READ_BYTE (AMBOR, val); - CONFIG_WRITE_BYTE(AMBOR, val & 0xDF); - CONFIG_WRITE_BYTE(AMBOR, val | 0x20); - CONFIG_WRITE_BYTE(AMBOR, val & 0xDF); +#if 1 + CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */ +#else + CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */ + CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */ +#endif +#endif - CONFIG_READ_WORD(PICR1, val); + CONFIG_READ_WORD(PICR1, val); #if defined(CONFIG_MPC8240) - CONFIG_WRITE_WORD( PICR1, - (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) | - PIRC1_MSK | PICR1_PROC_TYPE_603E | - PICR1_FLASH_WR_EN | PICR1_MCP_EN | - PICR1_CF_DPARK | PICR1_EN_PCS | - PICR1_CF_APARK ); + CONFIG_WRITE_WORD( PICR1, + (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) | + PIRC1_MSK | PICR1_PROC_TYPE_603E | + PICR1_FLASH_WR_EN | PICR1_MCP_EN | + PICR1_CF_DPARK | PICR1_EN_PCS | + PICR1_CF_APARK ); #elif defined(CONFIG_MPC8245) - CONFIG_WRITE_WORD( PICR1, - (val & (PICR1_RCS0)) | - PICR1_PROC_TYPE_603E | - PICR1_FLASH_WR_EN | PICR1_MCP_EN | - PICR1_CF_DPARK | PICR1_NO_BUSW_CK | - PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */ + CONFIG_WRITE_WORD( PICR1, + (val & (PICR1_RCS0)) | + PICR1_PROC_TYPE_603E | + PICR1_FLASH_WR_EN | PICR1_MCP_EN | + PICR1_CF_DPARK | PICR1_NO_BUSW_CK | + PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */ #else #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) #endif - CONFIG_READ_WORD(PICR2, val); - val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/ + CONFIG_READ_WORD(PICR2, val); + val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/ #ifndef CONFIG_PN62 - val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/ + val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/ #endif - CONFIG_WRITE_WORD(PICR2, val); + CONFIG_WRITE_WORD(PICR2, val); - CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR); + CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR); #ifndef CFG_RAMBOOT - CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | + CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_BANK0_ROW) | (CFG_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) | (CFG_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) | @@ -140,26 +157,26 @@ cpu_init_f (void) (CFG_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) | (CFG_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) | (CFG_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) | - (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)); + (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)); #endif #if defined(CFG_ASRISE) && defined(CFG_ASFALL) - CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT | - CFG_ASRISE << MCCR2_ASRISE_SHIFT | - CFG_ASFALL << MCCR2_ASFALL_SHIFT); + CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT | + CFG_ASRISE << MCCR2_ASRISE_SHIFT | + CFG_ASFALL << MCCR2_ASFALL_SHIFT); #else - CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT); + CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT); #endif #if defined(CONFIG_MPC8240) - CONFIG_WRITE_WORD(MCCR3, - (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | - (CFG_REFREC << MCCR3_REFREC_SHIFT) | - (CFG_RDLAT << MCCR3_RDLAT_SHIFT)); + CONFIG_WRITE_WORD(MCCR3, + (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | + (CFG_REFREC << MCCR3_REFREC_SHIFT) | + (CFG_RDLAT << MCCR3_RDLAT_SHIFT)); #elif defined(CONFIG_MPC8245) - CONFIG_WRITE_WORD(MCCR3, - (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | - (CFG_REFREC << MCCR3_REFREC_SHIFT)); + CONFIG_WRITE_WORD(MCCR3, + (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | + (CFG_REFREC << MCCR3_REFREC_SHIFT)); #else #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) #endif @@ -190,67 +207,67 @@ cpu_init_f (void) (CFG_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) | (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT )); #elif defined(CONFIG_MPC8245) - CONFIG_READ_WORD(MCCR1, val); - val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */ + CONFIG_READ_WORD(MCCR1, val); + val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */ - CONFIG_WRITE_WORD(MCCR4, - (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | - (CFG_EXTROM ? MCCR4_EXTROM : 0) | - (CFG_REGDIMM ? MCCR4_REGDIMM : 0) | - (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) | - (CFG_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) | - (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) | - (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) | - (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) | - (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT )); + CONFIG_WRITE_WORD(MCCR4, + (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | + (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | + (CFG_EXTROM ? MCCR4_EXTROM : 0) | + (CFG_REGDIMM ? MCCR4_REGDIMM : 0) | + (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | + ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) | + (CFG_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) | + (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) | + (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) | + (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) | + (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT )); #else #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) #endif - CONFIG_WRITE_WORD(MSAR1, - ( (CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMSAR1, - ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(MSAR2, - ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMSAR2, - ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(MEAR1, - ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMEAR1, - ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(MEAR2, - ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMEAR2, - ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - - CONFIG_WRITE_BYTE(ODCR, CFG_ODCR); + CONFIG_WRITE_WORD(MSAR1, + ( (CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(EMSAR1, + ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(MSAR2, + ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(EMSAR2, + ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(MEAR1, + ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(EMEAR1, + ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(MEAR2, + ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + CONFIG_WRITE_WORD(EMEAR2, + ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + + CONFIG_WRITE_BYTE(ODCR, CFG_ODCR); #ifdef CFG_DLL_MAX_DELAY CONFIG_WRITE_BYTE(MIOCR1, CFG_DLL_MAX_DELAY); /* needed to make DLL lock */ #endif @@ -261,31 +278,31 @@ cpu_init_f (void) CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD); /* change memory input */ #endif /* setup & hold time */ - CONFIG_WRITE_BYTE(MBER, - CFG_BANK0_ENABLE | - (CFG_BANK1_ENABLE << 1) | - (CFG_BANK2_ENABLE << 2) | - (CFG_BANK3_ENABLE << 3) | - (CFG_BANK4_ENABLE << 4) | - (CFG_BANK5_ENABLE << 5) | - (CFG_BANK6_ENABLE << 6) | - (CFG_BANK7_ENABLE << 7)); + CONFIG_WRITE_BYTE(MBER, + CFG_BANK0_ENABLE | + (CFG_BANK1_ENABLE << 1) | + (CFG_BANK2_ENABLE << 2) | + (CFG_BANK3_ENABLE << 3) | + (CFG_BANK4_ENABLE << 4) | + (CFG_BANK5_ENABLE << 5) | + (CFG_BANK6_ENABLE << 6) | + (CFG_BANK7_ENABLE << 7)); #ifdef CFG_PGMAX - CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX); + CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX); #endif - /* ! Wait 200us before initialize other registers */ - /*FIXME: write a decent udelay wait */ - __asm__ __volatile__( - " mtctr %0 \n \ - 0: bdnz 0b\n" - : - : "r" (0x10000)); + /* ! Wait 200us before initialize other registers */ + /*FIXME: write a decent udelay wait */ + __asm__ __volatile__( + " mtctr %0 \n \ + 0: bdnz 0b\n" + : + : "r" (0x10000)); - CONFIG_READ_WORD(MCCR1, val); - CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */ - __asm__ __volatile__("eieio"); + CONFIG_READ_WORD(MCCR1, val); + CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */ + __asm__ __volatile__("eieio"); #endif /* !CONFIG_MOUSSE && !CONFIG_BMW */ } @@ -293,32 +310,32 @@ cpu_init_f (void) #ifdef CONFIG_MOUSSE #ifdef INCLUDE_MPC107_REPORT -struct MPC107_s{ - unsigned int iobase; - char desc[120]; -} MPC107Regs[] ={ - {BMC_BASE+0x0, "MPC107 Vendor/Device ID"}, - {BMC_BASE+0x4, "MPC107 PCI Command/Status Register"}, - {BMC_BASE+0x8, "MPC107 Revision"}, - {BMC_BASE+0xC, "MPC107 Cache Line Size"}, - {BMC_BASE+0x10, "MPC107 LMBAR"}, - {BMC_BASE+0x14, "MPC824x PCSR"}, - {BMC_BASE+0xA8, "MPC824x PICR1"}, - {BMC_BASE+0xAC, "MPC824x PICR2"}, - {BMC_BASE+0x46, "MPC824x PACR"}, - {BMC_BASE+0x310, "MPC824x ITWR"}, - {BMC_BASE+0x300, "MPC824x OMBAR"}, - {BMC_BASE+0x308, "MPC824x OTWR"}, - {BMC_BASE+0x14, "MPC107 Peripheral Control and Status Register"}, - {BMC_BASE+0x78, "MPC107 EUMBAR"}, - {BMC_BASE+0xC0, "MPC107 Processor Bus Error Status"}, - {BMC_BASE+0xC4, "MPC107 PCI Bus Error Status"}, - {BMC_BASE+0xC8, "MPC107 Processor/PCI Error Address"}, - {BMC_BASE+0xE0, "MPC107 AMBOR Register"}, - {BMC_BASE+0xF0, "MPC107 MCCR1 Register"}, - {BMC_BASE+0xF4, "MPC107 MCCR2 Register"}, - {BMC_BASE+0xF8, "MPC107 MCCR3 Register"}, - {BMC_BASE+0xFC, "MPC107 MCCR4 Register"} +struct MPC107_s { + unsigned int iobase; + char desc[120]; +} MPC107Regs[] = { + { BMC_BASE + 0x00, "MPC107 Vendor/Device ID" }, + { BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" }, + { BMC_BASE + 0x08, "MPC107 Revision" }, + { BMC_BASE + 0x0C, "MPC107 Cache Line Size" }, + { BMC_BASE + 0x10, "MPC107 LMBAR" }, + { BMC_BASE + 0x14, "MPC824x PCSR" }, + { BMC_BASE + 0xA8, "MPC824x PICR1" }, + { BMC_BASE + 0xAC, "MPC824x PICR2" }, + { BMC_BASE + 0x46, "MPC824x PACR" }, + { BMC_BASE + 0x310, "MPC824x ITWR" }, + { BMC_BASE + 0x300, "MPC824x OMBAR" }, + { BMC_BASE + 0x308, "MPC824x OTWR" }, + { BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" }, + { BMC_BASE + 0x78, "MPC107 EUMBAR" }, + { BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" }, + { BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" }, + { BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" }, + { BMC_BASE + 0xE0, "MPC107 AMBOR Register" }, + { BMC_BASE + 0xF0, "MPC107 MCCR1 Register" }, + { BMC_BASE + 0xF4, "MPC107 MCCR2 Register" }, + { BMC_BASE + 0xF8, "MPC107 MCCR3 Register" }, + { BMC_BASE + 0xFC, "MPC107 MCCR4 Register" }, }; #define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0])) #endif /* INCLUDE_MPC107_REPORT */ |