diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm_cortexa8/mx50/Makefile | 3 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/mx50/crm_regs.h | 2 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/mx50/generic.c | 92 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/mx50/mmu.c | 61 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/mx50/serial.c | 226 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/mx50/timer.c | 5 |
6 files changed, 161 insertions, 228 deletions
diff --git a/cpu/arm_cortexa8/mx50/Makefile b/cpu/arm_cortexa8/mx50/Makefile index 460bdd9..51f6124 100644 --- a/cpu/arm_cortexa8/mx50/Makefile +++ b/cpu/arm_cortexa8/mx50/Makefile @@ -27,7 +27,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o serial.o generic.o iomux.o timer.o cache.o +COBJS = interrupts.o generic.o iomux.o timer.o cache.o +COBJS-$(CONFIG_ARCH_MMU) += mmu.o COBJS += $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm_cortexa8/mx50/crm_regs.h b/cpu/arm_cortexa8/mx50/crm_regs.h index e8915c8..1af5f9e 100644 --- a/cpu/arm_cortexa8/mx50/crm_regs.h +++ b/cpu/arm_cortexa8/mx50/crm_regs.h @@ -119,6 +119,8 @@ #define MXC_CCM_CLKSEQ_BYPASS (MXC_CCM_BASE + 0x90) #define MXC_CCM_CLK_SYS (MXC_CCM_BASE + 0x94) #define MXC_CCM_CLK_DDR (MXC_CCM_BASE + 0x98) +#define MXC_CCM_GPMI (MXC_CCM_BASE + 0xac) +#define MXC_CCM_BCH (MXC_CCM_BASE + 0xb0) /* Define the bits in register CCR */ #define MXC_CCM_CCR_COSC_EN (1 << 12) diff --git a/cpu/arm_cortexa8/mx50/generic.c b/cpu/arm_cortexa8/mx50/generic.c index 66ffaf9..bf24318 100644 --- a/cpu/arm_cortexa8/mx50/generic.c +++ b/cpu/arm_cortexa8/mx50/generic.c @@ -464,6 +464,88 @@ static u32 __get_esdhc4_clk(void) } #endif +#ifdef CONFIG_CMD_NAND +static inline void __enable_gpmi_clk(void) +{ + u32 reg1 = __REG(MXC_CCM_GPMI); + + reg1 |= 0x80000000; + + writel(reg1, MXC_CCM_GPMI); +} + +static inline void __enable_bch_clk(void) +{ + u32 reg1 = __REG(MXC_CCM_BCH); + + reg1 |= 0x80000000; + + writel(reg1, MXC_CCM_BCH); +} + + +static u32 __get_gpmi_clk(void) +{ + u32 ret_val = 0; + u32 clkseq_bypass = __REG(MXC_CCM_CLKSEQ_BYPASS); + u32 clk_sel = (clkseq_bypass & MXC_CCM_CLKSEQ_BYPASS_GPMI_MASK) + >> MXC_CCM_CLKSEQ_BYPASS_GPMI_OFFSET; + u32 div = __REG(MXC_CCM_GPMI) & 0x3f; + + __enable_gpmi_clk(); + + switch (clk_sel) { + case 0: + /* 24MHz xtal */ + ret_val = CONFIG_MX50_HCLK_FREQ; + break; + case 1: + /* PFD4 */ + puts("Warning, Fixme,not handle PFD mux\n"); + break; + case 2: + /* PLL1 */ + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ); + break; + default: + break; + } + + return (div > 0) ? (ret_val / div) : 0; +} + +static u32 __get_bch_clk(void) +{ + u32 ret_val = 0; + u32 clkseq_bypass = __REG(MXC_CCM_CLKSEQ_BYPASS); + u32 clk_sel = (clkseq_bypass & MXC_CCM_CLKSEQ_BYPASS_BCH_MASK) + >> MXC_CCM_CLKSEQ_BYPASS_BCH_OFFSET; + u32 div = __REG(MXC_CCM_BCH) & 0x3f; + + __enable_bch_clk(); + + switch (clk_sel) { + case 0: + /* 24MHz xtal */ + ret_val = CONFIG_MX50_HCLK_FREQ; + break; + case 1: + /* PFD4 */ + puts("Warning, Fixme,not handle PFD mux\n"); + break; + case 2: + /* PLL1 */ + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ); + break; + default: + break; + } + + return (div > 0) ? (ret_val / div) : 0; +} + +#endif + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { @@ -501,6 +583,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_ESDHC4_CLK: return __get_esdhc4_clk(); #endif +#ifdef CONFIG_CMD_NAND + case MXC_GPMI_CLK: + return __get_gpmi_clk(); + case MXC_BCH_CLK: + return __get_bch_clk(); +#endif default: break; } @@ -533,6 +621,10 @@ void mxc_dump_clocks(void) printf("esdhc3 clock : %dHz\n", mxc_get_clock(MXC_ESDHC3_CLK)); printf("esdhc4 clock : %dHz\n", mxc_get_clock(MXC_ESDHC4_CLK)); #endif +#ifdef CONFIG_CMD_NAND + printf("GPMI clock : %dHz\n", mxc_get_clock(MXC_GPMI_CLK)); + printf("BCH clock : %dHz\n", mxc_get_clock(MXC_BCH_CLK)); +#endif } #ifdef CONFIG_CMD_CLOCK diff --git a/cpu/arm_cortexa8/mx50/mmu.c b/cpu/arm_cortexa8/mx50/mmu.c new file mode 100644 index 0000000..8d5cd73 --- /dev/null +++ b/cpu/arm_cortexa8/mx50/mmu.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* + * Translate the virtual address of ram space to physical address + * It is dependent on the implementation of mmu_init + */ +inline void *iomem_to_phys(unsigned long virt) +{ + if (virt >= 0xB0000000) + return (void *)((virt - 0xB0000000) + PHYS_SDRAM_1); + + return (void *)virt; +} + +/* + * remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void *__ioremap(unsigned long offset, size_t size, unsigned long flags) +{ + if (1 == flags) { + if (offset >= PHYS_SDRAM_1 && + offset < (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + return (void *)(offset - PHYS_SDRAM_1) + 0xB0000000; + else + return NULL; + } else + return (void *)offset; +} + +/* + * Remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void __iounmap(void *addr) +{ + return; +} + diff --git a/cpu/arm_cortexa8/mx50/serial.c b/cpu/arm_cortexa8/mx50/serial.c deleted file mode 100644 index a0cef25..0000000 --- a/cpu/arm_cortexa8/mx50/serial.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> - * - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> - -#if defined CONFIG_MX50_UART - -#include <asm/arch/mx50.h> - -#ifdef CONFIG_MX50_UART1 -#define UART_PHYS UART1_BASE_ADDR -#elif defined(CONFIG_MX50_UART2) -#define UART_PHYS UART2_BASE_ADDR -#elif defined(CONFIG_MX50_UART3) -#define UART_PHYS UART3_BASE_ADDR -#else -#error "define CFG_MX50_UARTx to use the mx50 UART driver" -#endif - -/* Register definitions */ -#define URXD 0x0 /* Receiver Register */ -#define UTXD 0x40 /* Transmitter Register */ -#define UCR1 0x80 /* Control Register 1 */ -#define UCR2 0x84 /* Control Register 2 */ -#define UCR3 0x88 /* Control Register 3 */ -#define UCR4 0x8c /* Control Register 4 */ -#define UFCR 0x90 /* FIFO Control Register */ -#define USR1 0x94 /* Status Register 1 */ -#define USR2 0x98 /* Status Register 2 */ -#define UESC 0x9c /* Escape Character Register */ -#define UTIM 0xa0 /* Escape Timer Register */ -#define UBIR 0xa4 /* BRM Incremental Register */ -#define UBMR 0xa8 /* BRM Modulator Register */ -#define UBRC 0xac /* Baud Rate Count Register */ -#define UTS 0xb4 /* UART Test Register (mx31) */ - -/* UART Control Register Bit Fields.*/ -#define URXD_CHARRDY (1<<15) -#define URXD_ERR (1<<14) -#define URXD_OVRRUN (1<<13) -#define URXD_FRMERR (1<<12) -#define URXD_BRK (1<<11) -#define URXD_PRERR (1<<10) -#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ -#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ -#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ -#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ -#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ -#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ -#define UCR1_IREN (1<<7) /* Infrared interface enable */ -#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ -#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ -#define UCR1_SNDBRK (1<<4) /* Send break */ -#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ -#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ -#define UCR1_DOZE (1<<1) /* Doze */ -#define UCR1_UARTEN (1<<0) /* UART enabled */ -#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ -#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ -#define UCR2_CTSC (1<<13) /* CTS pin control */ -#define UCR2_CTS (1<<12) /* Clear to send */ -#define UCR2_ESCEN (1<<11) /* Escape enable */ -#define UCR2_PREN (1<<8) /* Parity enable */ -#define UCR2_PROE (1<<7) /* Parity odd/even */ -#define UCR2_STPB (1<<6) /* Stop */ -#define UCR2_WS (1<<5) /* Word size */ -#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ -#define UCR2_TXEN (1<<2) /* Transmitter enabled */ -#define UCR2_RXEN (1<<1) /* Receiver enabled */ -#define UCR2_SRST (1<<0) /* SW reset */ -#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ -#define UCR3_PARERREN (1<<12) /* Parity enable */ -#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ -#define UCR3_DSR (1<<10) /* Data set ready */ -#define UCR3_DCD (1<<9) /* Data carrier detect */ -#define UCR3_RI (1<<8) /* Ring indicator */ -#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ -#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ -#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ -#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ -#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ -#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ -#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ -#define UCR3_BPEN (1<<0) /* Preset registers enable */ -#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ -#define UCR4_INVR (1<<9) /* Inverted infrared reception */ -#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ -#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ -#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ -#define UCR4_IRSC (1<<5) /* IR special case */ -#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ -#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ -#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ -#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ -#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ -#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ -#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ -#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ -#define USR1_RTSS (1<<14) /* RTS pin status */ -#define USR1_TRDY (1<<13)/* Transmitter ready interrupt/dma flag */ -#define USR1_RTSD (1<<12) /* RTS delta */ -#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ -#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ -#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ -#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ -#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ -#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ -#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ -#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ -#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ -#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ -#define USR2_IDLE (1<<12) /* Idle condition */ -#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ -#define USR2_WAKE (1<<7) /* Wake */ -#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ -#define USR2_TXDC (1<<3) /* Transmitter complete */ -#define USR2_BRCD (1<<2) /* Break condition */ -#define USR2_ORE (1<<1) /* Overrun error */ -#define USR2_RDR (1<<0) /* Recv data ready */ -#define UTS_FRCPERR (1<<13) /* Force parity error */ -#define UTS_LOOP (1<<12) /* Loop tx and rx */ -#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ -#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ -#define UTS_TXFULL (1<<4) /* TxFIFO full */ -#define UTS_RXFULL (1<<3) /* RxFIFO full */ -#define UTS_SOFTRST (1<<0) /* Software reset */ - -DECLARE_GLOBAL_DATA_PTR; - -void serial_setbrg(void) -{ - u32 clk = mxc_get_clock(MXC_UART_CLK); - - if (!gd->baudrate) - gd->baudrate = CONFIG_BAUDRATE; - __REG(UART_PHYS + UFCR) = 0x4 << 7; /* divide input clock by 2 */ - __REG(UART_PHYS + UBIR) = 0xf; - __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); -} - -int serial_getc(void) -{ - while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) - ; - return __REG(UART_PHYS + URXD); -} - -void serial_putc(const char c) -{ - __REG(UART_PHYS + UTXD) = c; - - /* wait for transmitter to be ready */ - while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) - ; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int serial_tstc(void) -{ - /* If receive fifo is empty, return false */ - if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) - return 0; - return 1; -} - -void serial_puts(const char *s) -{ - while (*s) - serial_putc(*s++); -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init(void) -{ - __REG(UART_PHYS + UCR1) = 0x0; - __REG(UART_PHYS + UCR2) = 0x0; - - while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)) - ; - - __REG(UART_PHYS + UCR3) = 0x0704; - __REG(UART_PHYS + UCR4) = 0x8000; - __REG(UART_PHYS + UESC) = 0x002b; - __REG(UART_PHYS + UTIM) = 0x0; - - __REG(UART_PHYS + UTS) = 0x0; - - serial_setbrg(); - - __REG(UART_PHYS + UCR2) = - UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; - - __REG(UART_PHYS + UCR1) = UCR1_UARTEN; - - return 0; -} - -#endif /* CONFIG_MX50_UART */ diff --git a/cpu/arm_cortexa8/mx50/timer.c b/cpu/arm_cortexa8/mx50/timer.c index 00150ab..33ab82a 100644 --- a/cpu/arm_cortexa8/mx50/timer.c +++ b/cpu/arm_cortexa8/mx50/timer.c @@ -37,6 +37,7 @@ #define GPTCR_FRR (1<<9) /* Freerun / restart */ #define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ #define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_ENMOD_RESET (2) #define GPTCR_TEN (1) /* Timer enable */ #define GPTPR_VAL (50) @@ -56,6 +57,7 @@ static inline void setup_gpt(void) GPTCR = 0; /* We have no udelay by now */ GPTPR = GPTPR_VAL; /* 50Mhz / 50 */ /* Freerun Mode, PERCLK1 input */ + GPTCR |= GPTCR_ENMOD_RESET; GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN; } @@ -69,8 +71,9 @@ int timer_init(void) void reset_timer_masked(void) { GPTCR = 0; + GPTCR |= GPTCR_ENMOD_RESET; /* Freerun Mode, PERCLK1 input */ - GPTCR = GPTCR_CLKSOURCE_IPG | GPTCR_TEN; + GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN; } inline ulong get_timer_masked(void) |