diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm_cortexa8/cpu.c | 4 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/mx53/generic.c | 35 |
2 files changed, 39 insertions, 0 deletions
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index ac7ac13..a7a6fb7 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -136,6 +136,10 @@ int cleanup_before_linux(void) { unsigned int i; +#ifdef CONFIG_CMD_IMX_DOWNLOAD_MODE + clear_mfgmode_mem(); +#endif + #ifdef CONFIG_VIDEO_MX5 ipu_disable_channel(MEM_BG_SYNC); ipu_uninit_channel(MEM_BG_SYNC); diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c index d54bf2c..e53a720 100644 --- a/cpu/arm_cortexa8/mx53/generic.c +++ b/cpu/arm_cortexa8/mx53/generic.c @@ -1131,3 +1131,38 @@ void ipu_clk_disable(void) reg |= (0x1 << 18); writel(reg, CCM_BASE_ADDR + CLKCTL_CLPCR); } + +#ifdef CONFIG_CMD_IMX_DOWNLOAD_MODE + +/* this function should call before enter linux, otherwise, you + * watchdog reset will enter mfg download mode again, clear this bit + * to prevent this behavior */ +void clear_mfgmode_mem(void) +{ + u32 reg; + reg = readl(SRTC_BASE_ADDR + SRTC_LPGR); + reg &= ~0x12000000; + writel(reg, SRTC_BASE_ADDR + SRTC_LPGR); +} + +void do_switch_mfgmode(void) +{ + u32 reg; + reg = readl(SRTC_BASE_ADDR + SRTC_LPGR); + /* After set bit 28 of LPGR register of SRTC to 1, Set bit + * [25:0] to specified value according to format of SBMR, + * after trigger a watchdog reset, ROM will read Bit 28 and + * then copy bit [25:0] of LPGR to SBMR, then ROM can enter + * serial download mode.*/ + reg |= 0x12000000; + writel(reg, SRTC_BASE_ADDR + SRTC_LPGR); + /* this watchdog reset will let chip enter mfgtool download + * mode. */ + do_reset(NULL, 0, 0, NULL); +} + +U_BOOT_CMD( + download_mode, 1, 1, do_switch_mfgmode, + "download_mode - enter i.MX serial/usb download mode\n", + ""); +#endif |