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-rw-r--r--cpu/pxa/cpu.c8
-rw-r--r--cpu/pxa/i2c.c19
-rw-r--r--cpu/pxa/serial.c16
-rw-r--r--cpu/pxa/start.S117
4 files changed, 115 insertions, 45 deletions
diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index d1551dd..0ee8180 100644
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -34,14 +34,16 @@
#include <command.h>
#include <asm/arch/pxa-regs.h>
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
int cpu_init (void)
{
/*
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
- DECLARE_GLOBAL_DATA_PTR;
-
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
@@ -143,6 +145,7 @@ int dcache_status (void)
return 0; /* always off */
}
+#ifndef CONFIG_CPU_MONAHANS
void set_GPIO_mode(int gpio_mode)
{
int gpio = gpio_mode & GPIO_MD_MASK_NR;
@@ -160,3 +163,4 @@ void set_GPIO_mode(int gpio_mode)
gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
}
+#endif /* CONFIG_CPU_MONAHANS */
diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c
index b6155b1..722d949 100644
--- a/cpu/pxa/i2c.c
+++ b/cpu/pxa/i2c.c
@@ -47,7 +47,13 @@
/*#define DEBUG_I2C 1 /###* activate local debugging output */
#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */
-#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+
+#if (CFG_I2C_SPEED == 400000)
+#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+#else
+#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+#endif
+
#define I2C_ISR_INIT 0x7FF
#ifdef DEBUG_I2C
@@ -91,7 +97,11 @@ static void i2c_reset( void )
ICR |= ICR_UR; /* reset the unit */
udelay(100);
ICR &= ~ICR_IUE; /* disable unit */
+#ifdef CONFIG_CPU_MONAHANS
+ CKENB |= (CKENB_4_I2C); /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
+#else /* CONFIG_CPU_MONAHANS */
CKEN |= CKEN14_I2C; /* set the global I2C clock on */
+#endif
ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */
ICR = I2C_ICR_INIT; /* set control register values */
ISR = I2C_ISR_INIT; /* set clear interrupt bits */
@@ -104,9 +114,8 @@ static void i2c_reset( void )
* i2c_isr_set_cleared: - wait until certain bits of the I2C status register
* are set and cleared
*
- * @return: 0 in case of success, 1 means timeout (no match within 10 ms).
+ * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
*/
-
static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask )
{
int timeout = 10000;
@@ -360,9 +369,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
msg.data = 0x00;
if ((ret=i2c_transfer(&msg))) return -1;
- *(buffer++) = msg.data;
-
+ *buffer = msg.data;
PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
+ buffer++;
}
diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c
index cedebfe..cb3a478 100644
--- a/cpu/pxa/serial.c
+++ b/cpu/pxa/serial.c
@@ -32,10 +32,10 @@
#include <watchdog.h>
#include <asm/arch/pxa-regs.h>
+DECLARE_GLOBAL_DATA_PTR;
+
void serial_setbrg (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
unsigned int quot = 0;
if (gd->baudrate == 1200)
@@ -54,7 +54,11 @@ void serial_setbrg (void)
hang ();
#ifdef CONFIG_FFUART
+#ifdef CONFIG_CPU_MONAHANS
+ CKENA |= CKENA_22_FFUART;
+#else
CKEN |= CKEN6_FFUART;
+#endif /* CONFIG_CPU_MONAHANS */
FFIER = 0; /* Disable for now */
FFFCR = 0; /* No fifos enabled */
@@ -68,7 +72,11 @@ void serial_setbrg (void)
FFIER = IER_UUE; /* Enable FFUART */
#elif defined(CONFIG_BTUART)
+#ifdef CONFIG_CPU_MONAHANS
+ CKENA |= CKENA_21_BTUART;
+#else
CKEN |= CKEN7_BTUART;
+#endif /* CONFIG_CPU_MONAHANS */
BTIER = 0;
BTFCR = 0;
@@ -82,7 +90,11 @@ void serial_setbrg (void)
BTIER = IER_UUE; /* Enable BFUART */
#elif defined(CONFIG_STUART)
+#ifdef CONFIG_CPU_MONAHANS
+ CKENA |= CKENA_23_STUART;
+#else
CKEN |= CKEN5_STUART;
+#endif /* CONFIG_CPU_MONAHANS */
STIER = 0;
STFCR = 0;
diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S
index a8cc080..ffaa30f 100644
--- a/cpu/pxa/start.S
+++ b/cpu/pxa/start.S
@@ -6,8 +6,8 @@
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
- * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
+ * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -30,6 +30,7 @@
#include <config.h>
#include <version.h>
+#include <asm/arch/pxa-regs.h>
.globl _start
_start: b reset
@@ -116,13 +117,13 @@ reset:
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
+ sub r2, r3, r2 /* r2 <- size of armboot */
+ add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
@@ -134,19 +135,19 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
+ ldr r0, _bss_start /* find start of bss segment */
+ ldr r1, _bss_end /* stop here */
+ mov r2, #0x00000000 /* clear */
-clbss_l:str r2, [r0] /* clear loop... */
+clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
ble clbss_l
@@ -164,8 +165,16 @@ _start_armboot: .word start_armboot
/* - setup memory timing */
/* */
/****************************************************************************/
+/* mk@tbd: Fix this! */
+#ifdef CONFIG_CPU_MONAHANS
+#undef ICMR
+#undef OSMR3
+#undef OSCR
+#undef OWER
+#undef OIER
+#endif
-/* Interrupt-Controller base address */
+/* Interrupt-Controller base address */
IC_BASE: .word 0x40d00000
#define ICMR 0x04
@@ -180,7 +189,15 @@ OSTIMER_BASE: .word 0x40a00000
#define OWER 0x18
#define OIER 0x1C
-/* Clock Manager Registers */
+/* Clock Manager Registers */
+#ifdef CONFIG_CPU_MONAHANS
+# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
+# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
+# endif
+# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
+# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
+# endif
+#else /* ! CONFIG_CPU_MONAHANS */
#ifdef CFG_CPUSPEED
CC_BASE: .word 0x41300000
#define CCCR 0x00
@@ -188,26 +205,50 @@ cpuspeed: .word CFG_CPUSPEED
#else
#error "You have to define CFG_CPUSPEED!!"
#endif
+#endif /* CONFIG_CPU_MONAHANS */
-
- /* RS: ??? */
- .macro CPWAIT
- mrc p15,0,r0,c2,c0,0
- mov r0,r0
+ /* takes care the CP15 update has taken place */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
sub pc,pc,#4
.endm
-
cpu_init_crit:
/* mask all IRQs */
+#ifndef CONFIG_CPU_MONAHANS
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
-
-#if defined(CFG_CPUSPEED)
+#else
+ /* Step 1 - Enable CP6 permission */
+ mrc p15, 0, r1, c15, c1, 0 @ read CPAR
+ orr r1, r1, #0x40
+ mcr p15, 0, r1, c15, c1, 0
+ CPWAIT r1
+
+ /* Step 2 - Mask ICMR & ICMR2 */
+ mov r1, #0
+ mcr p6, 0, r1, c1, c0, 0 @ ICMR
+ mcr p6, 0, r1, c7, c0, 0 @ ICMR2
+
+ /* turn off all clocks but the ones we will definitly require */
+ ldr r1, =CKENA
+ ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
+ str r2, [r1]
+ ldr r1, =CKENB
+ ldr r2, =(CKENB_6_IRQ)
+ str r2, [r1]
+#endif
/* set clock speed */
+#ifdef CONFIG_CPU_MONAHANS
+ ldr r0, =ACCR
+ ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
+ str r1, [r0]
+#else /* ! CONFIG_CPU_MONAHANS */
+#ifdef CFG_CPUSPEED
ldr r0, CC_BASE
ldr r1, cpuspeed
str r1, [r0, #CCCR]
@@ -215,7 +256,9 @@ cpu_init_crit:
mcr p14, 0, r0, c6, c0, 0
setspeed_done:
-#endif
+
+#endif /* CFG_CPUSPEED */
+#endif /* CONFIG_CPU_MONAHANS */
/*
* before relocating, we have to setup RAM timing
@@ -227,19 +270,21 @@ setspeed_done:
mov lr, ip
/* Memory interfaces are working. Disable MMU and enable I-cache. */
+ /* mk: hmm, this is not in the monahans docs, leave it now but
+ * check here if it doesn't work :-) */
ldr r0, =0x2001 /* enable access to all coproc. */
mcr p15, 0, r0, c15, c1, 0
- CPWAIT
+ CPWAIT r0
mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
- CPWAIT
+ CPWAIT r0
mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
- CPWAIT
+ CPWAIT r0
mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
- CPWAIT
+ CPWAIT r0
/* Enable the Icache */
/*
@@ -292,7 +337,7 @@ setspeed_done:
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
@@ -419,17 +464,17 @@ fiq:
#endif
/****************************************************************************/
-/* */
+/* */
/* Reset function: the PXA250 doesn't have a reset function, so we have to */
-/* perform a watchdog timeout for a soft reset. */
-/* */
+/* perform a watchdog timeout for a soft reset. */
+/* */
/****************************************************************************/
.align 5
.globl reset_cpu
- /* FIXME: this code is PXA250 specific. How is this handled on */
- /* other XScale processors? */
+ /* FIXME: this code is PXA250 specific. How is this handled on */
+ /* other XScale processors? */
reset_cpu:
@@ -437,13 +482,13 @@ reset_cpu:
ldr r0, OSTIMER_BASE
ldr r1, [r0, #OWER]
- orr r1, r1, #0x0001 /* bit0: WME */
+ orr r1, r1, #0x0001 /* bit0: WME */
str r1, [r0, #OWER]
/* OS timer does only wrap every 1165 seconds, so we have to set */
- /* the match register as well. */
+ /* the match register as well. */
- ldr r1, [r0, #OSCR] /* read OS timer */
+ ldr r1, [r0, #OSCR] /* read OS timer */
add r1, r1, #0x800 /* let OSMR3 match after */
add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
str r1, [r0, #OSMR3]
generated by cgit v1.1 at 2024-12-26 05:21:30 +0000