diff options
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/Makefile | 4 | ||||
| -rw-r--r-- | cpu/ppc4xx/cmd_chip_config.c | 142 | ||||
| -rw-r--r-- | cpu/ppc4xx/cpu.c | 31 | ||||
| -rw-r--r-- | cpu/ppc4xx/cpu_init.c | 2 | ||||
| -rw-r--r-- | cpu/ppc4xx/interrupts.c | 18 | ||||
| -rw-r--r-- | cpu/ppc4xx/ndfc.c | 223 | ||||
| -rw-r--r-- | cpu/ppc4xx/speed.c | 5 | ||||
| -rw-r--r-- | cpu/ppc4xx/start.S | 215 |
8 files changed, 296 insertions, 344 deletions
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 96ab5c6..2050b17 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -41,6 +41,9 @@ endif COBJS += 4xx_pci.o COBJS += 4xx_pcie.o COBJS += bedbug_405.o +ifdef CONFIG_CMD_CHIP_CONFIG +COBJS += cmd_chip_config.o +endif COBJS += commproc.o COBJS += cpu.o COBJS += cpu_init.o @@ -51,7 +54,6 @@ COBJS += fdt.o COBJS += i2c.o COBJS += interrupts.o COBJS += iop480_uart.o -COBJS += ndfc.o COBJS += sdram.o COBJS += speed.o COBJS += tlb.o diff --git a/cpu/ppc4xx/cmd_chip_config.c b/cpu/ppc4xx/cmd_chip_config.c new file mode 100644 index 0000000..d360d5b --- /dev/null +++ b/cpu/ppc4xx/cmd_chip_config.c @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2008-2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2009 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <asm/ppc4xx_config.h> +#include <asm/io.h> + +static void print_configs(int cur_config_nr) +{ + int i; + + for (i = 0; i < ppc4xx_config_count; i++) { + printf("%-16s - %s", ppc4xx_config_val[i].label, + ppc4xx_config_val[i].description); + if (i == cur_config_nr) + printf(" ***"); + printf("\n"); + } + +} + +static int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + int ret; + int cur_config_nr = -1; + u8 cur_config[CONFIG_4xx_CONFIG_BLOCKSIZE]; + +#ifdef CONFIG_CMD_EEPROM + ret = eeprom_read(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR, + CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET, + cur_config, CONFIG_4xx_CONFIG_BLOCKSIZE); +#else + ret = i2c_read(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR, + CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET, + 1, cur_config, CONFIG_4xx_CONFIG_BLOCKSIZE); +#endif + if (ret) { + printf("Error reading EEPROM at addr 0x%x\n", + CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR); + return -1; + } + + /* + * Search the current configuration + */ + for (i = 0; i < ppc4xx_config_count; i++) { + if (memcmp(cur_config, ppc4xx_config_val[i].val, + CONFIG_4xx_CONFIG_BLOCKSIZE) == 0) + cur_config_nr = i; + } + + if (cur_config_nr == -1) { + printf("Warning: The I2C bootstrap values don't match any" + " of the available options!\n"); + printf("I2C bootstrap EEPROM values are (I2C address 0x%02x):\n", + CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR); + for (i = 0; i < CONFIG_4xx_CONFIG_BLOCKSIZE; i++) { + printf("%02x ", cur_config[i]); + } + printf("\n"); + } + + if (argc < 2) { + printf("Available configurations (I2C address 0x%02x):\n", + CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR); + print_configs(cur_config_nr); + return 0; + } + + for (i = 0; i < ppc4xx_config_count; i++) { + /* + * Search for configuration name/label + */ + if (strcmp(argv[1], ppc4xx_config_val[i].label) == 0) { + printf("Using configuration:\n%-16s - %s\n", + ppc4xx_config_val[i].label, + ppc4xx_config_val[i].description); + +#ifdef CONFIG_CMD_EEPROM + ret = eeprom_write(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR, + CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET, + ppc4xx_config_val[i].val, + CONFIG_4xx_CONFIG_BLOCKSIZE); +#else + ret = i2c_write(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR, + CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET, + 1, ppc4xx_config_val[i].val, + CONFIG_4xx_CONFIG_BLOCKSIZE); +#endif + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); + if (ret) { + printf("Error updating EEPROM at addr 0x%x\n", + CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR); + return -1; + } + + printf("done (dump via 'i2c md %x 0.1 %x')\n", + CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR, + CONFIG_4xx_CONFIG_BLOCKSIZE); + printf("Reset the board for the changes to" + " take effect\n"); + return 0; + } + } + + printf("Configuration %s not found!\n", argv[1]); + print_configs(cur_config_nr); + return -1; +} + +U_BOOT_CMD( + chip_config, 2, 0, do_chip_config, + "program the I2C bootstrap EEPROM", + "[config-label]" +); diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index fb3837c..e9861ab 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -272,7 +272,7 @@ static int do_chip_reset (unsigned long sys0, unsigned long sys1) mtdcr (cpc0_sys0, sys0); mtdcr (cpc0_sys1, sys1); mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ - mtspr (dbcr0, 0x20000000); /* Reset the chip */ + mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */ return 1; } @@ -285,6 +285,9 @@ int checkcpu (void) uint pvr = get_pvr(); ulong clock = gd->cpu_clk; char buf[32]; +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + u32 reg; +#endif #if !defined(CONFIG_IOP480) char addstr[64] = ""; @@ -526,6 +529,7 @@ int checkcpu (void) strcpy(addstr, "No RAID 6 support"); break; +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) case PVR_460EX_RA: puts("EX Rev. A"); strcpy(addstr, "No Security/Kasumi support"); @@ -536,6 +540,15 @@ int checkcpu (void) strcpy(addstr, "Security/Kasumi support"); break; + case PVR_460EX_RB: + puts("EX Rev. B"); + mfsdr(SDR0_ECID3, reg); + if (reg & 0x00100000) + strcpy(addstr, "No Security/Kasumi support"); + else + strcpy(addstr, "Security/Kasumi support"); + break; + case PVR_460GT_RA: puts("GT Rev. A"); strcpy(addstr, "No Security/Kasumi support"); @@ -546,6 +559,16 @@ int checkcpu (void) strcpy(addstr, "Security/Kasumi support"); break; + case PVR_460GT_RB: + puts("GT Rev. B"); + mfsdr(SDR0_ECID3, reg); + if (reg & 0x00100000) + strcpy(addstr, "No Security/Kasumi support"); + else + strcpy(addstr, "Security/Kasumi support"); + break; +#endif + case PVR_460SX_RA: puts("SX Rev. A"); strcpy(addstr, "Security support"); @@ -654,12 +677,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) board_reset(); #else #if defined(CONFIG_SYS_4xx_RESET_TYPE) - mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28); + mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28); #else /* * Initiate system reset in debug control register DBCR */ - mtspr(dbcr0, 0x30000000); + mtspr(SPRN_DBCR0, 0x30000000); #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */ #endif /* defined(CONFIG_BOARD_RESET) */ @@ -697,7 +720,7 @@ void reset_4xx_watchdog(void) /* * Clear TSR(WIS) bit */ - mtspr(tsr, 0x40000000); + mtspr(SPRN_TSR, 0x40000000); } #endif /* CONFIG_WATCHDOG */ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index bbd795d..65092fb 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -123,7 +123,7 @@ void reconfigure_pll(u32 new_cpu_freq) /* Reset processor if configuration changed */ if (reset_needed) { __asm__ __volatile__ ("sync; isync"); - mtspr(dbcr0, 0x20000000); + mtspr(SPRN_DBCR0, 0x20000000); } #endif } diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 494bd8c..6db8421 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -102,15 +102,15 @@ int interrupt_init_cpu (unsigned *decrementer_count) * Init PIT */ #if defined(CONFIG_440) - val = mfspr( tcr ); + val = mfspr( SPRN_TCR ); val &= (~0x04400000); /* clear DIS & ARE */ - mtspr( tcr, val ); - mtspr( dec, 0 ); /* Prevent exception after TSR clear*/ - mtspr( decar, 0 ); /* clear reload */ - mtspr( tsr, 0x08000000 ); /* clear DEC status */ + mtspr( SPRN_TCR, val ); + mtspr( SPRN_DEC, 0 ); /* Prevent exception after TSR clear*/ + mtspr( SPRN_DECAR, 0 ); /* clear reload */ + mtspr( SPRN_TSR, 0x08000000 ); /* clear DEC status */ val = gd->bd->bi_intfreq/1000; /* 1 msec */ - mtspr( decar, val ); /* Set auto-reload value */ - mtspr( dec, val ); /* Set inital val */ + mtspr( SPRN_DECAR, val ); /* Set auto-reload value */ + mtspr( SPRN_DEC, val ); /* Set inital val */ #else set_pit(gd->bd->bi_intfreq / 1000); #endif @@ -126,9 +126,9 @@ int interrupt_init_cpu (unsigned *decrementer_count) /* * Enable PIT */ - val = mfspr(tcr); + val = mfspr(SPRN_TCR); val |= 0x04400000; - mtspr(tcr, val); + mtspr(SPRN_TCR, val); /* * Set EVPR to 0 diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c deleted file mode 100644 index 971e2ae..0000000 --- a/cpu/ppc4xx/ndfc.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Overview: - * Platform independend driver for NDFC (NanD Flash Controller) - * integrated into IBM/AMCC PPC4xx cores - * - * (C) Copyright 2006-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Based on original work by - * Thomas Gleixner - * Copyright 2006 IBM - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_NAND_LEGACY) && \ - defined(CONFIG_NAND_NDFC) - -#include <nand.h> -#include <linux/mtd/ndfc.h> -#include <linux/mtd/nand_ecc.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <ppc4xx.h> - -/* - * We need to store the info, which chip-select (CS) is used for the - * chip number. For example on Sequoia NAND chip #0 uses - * CS #3. - */ -static int ndfc_cs[NDFC_MAX_BANKS]; - -static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; - - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) - out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF); - else - out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF); -} - -static int ndfc_dev_ready(struct mtd_info *mtdinfo) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; - - return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY); -} - -static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; - u32 ccr; - - ccr = in_be32((u32 *)(base + NDFC_CCR)); - ccr |= NDFC_CCR_RESET_ECC; - out_be32((u32 *)(base + NDFC_CCR), ccr); -} - -static int ndfc_calculate_ecc(struct mtd_info *mtdinfo, - const u_char *dat, u_char *ecc_code) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; - u32 ecc; - u8 *p = (u8 *)&ecc; - - ecc = in_be32((u32 *)(base + NDFC_ECC)); - - /* The NDFC uses Smart Media (SMC) bytes order - */ - ecc_code[0] = p[2]; - ecc_code[1] = p[1]; - ecc_code[2] = p[3]; - - return 0; -} - -/* - * Speedups for buffer read/write/verify - * - * NDFC allows 32bit read/write of data. So we can speed up the buffer - * functions. No further checking, as nand_base will always read/write - * page aligned. - */ -static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; - uint32_t *p = (uint32_t *) buf; - - for (;len > 0; len -= 4) - *p++ = in_be32((u32 *)(base + NDFC_DATA)); -} - -#ifndef CONFIG_NAND_SPL -/* - * Don't use these speedup functions in NAND boot image, since the image - * has to fit into 4kByte. - */ -static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; - uint32_t *p = (uint32_t *) buf; - - for (; len > 0; len -= 4) - out_be32((u32 *)(base + NDFC_DATA), *p++); -} - -static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; - uint32_t *p = (uint32_t *) buf; - - for (; len > 0; len -= 4) - if (*p++ != in_be32((u32 *)(base + NDFC_DATA))) - return -1; - - return 0; -} -#endif /* #ifndef CONFIG_NAND_SPL */ - -#ifndef CONFIG_SYS_NAND_BCR -#define CONFIG_SYS_NAND_BCR 0x80002222 -#endif - -void board_nand_select_device(struct nand_chip *nand, int chip) -{ - /* - * Don't use "chip" to address the NAND device, - * generate the cs from the address where it is encoded. - */ - ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00; - int cs = ndfc_cs[chip]; - - /* Set NandFlash Core Configuration Register */ - /* 1 col x 2 rows */ - out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24)); - out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR); -} - -static void ndfc_select_chip(struct mtd_info *mtd, int chip) -{ - /* - * Nothing to do here! - */ -} - -int board_nand_init(struct nand_chip *nand) -{ - int cs = (ulong)nand->IO_ADDR_W & 0x00000003; - ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00; - static int chip = 0; - - /* - * Save chip-select for this chip # - */ - ndfc_cs[chip] = cs; - - /* - * Select required NAND chip in NDFC - */ - board_nand_select_device(nand, chip); - - nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA); - nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA); - nand->cmd_ctrl = ndfc_hwcontrol; - nand->chip_delay = 50; - nand->read_buf = ndfc_read_buf; - nand->dev_ready = ndfc_dev_ready; - nand->ecc.correct = nand_correct_data; - nand->ecc.hwctl = ndfc_enable_hwecc; - nand->ecc.calculate = ndfc_calculate_ecc; - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.size = 256; - nand->ecc.bytes = 3; - nand->select_chip = ndfc_select_chip; - -#ifndef CONFIG_NAND_SPL - nand->write_buf = ndfc_write_buf; - nand->verify_buf = ndfc_verify_buf; -#else - /* - * Setup EBC (CS0 only right now) - */ - mtebc(EBC0_CFG, 0xb8400000); - - mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR); - mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP); -#endif - - chip++; - - return 0; -} - -#endif diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index ed6e55b..c0a5824 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -394,7 +394,8 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->freqUART = sysInfo->freqPLB; /* Figure which timer source to use */ - if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */ + if (mfspr(SPRN_CCR1) & 0x0080) { + /* External Clock, assume same as SYS_CLK */ temp = sysInfo->freqProcessor / 2; /* Max extern clock speed */ if (CONFIG_SYS_CLK_FREQ > temp) sysInfo->freqTmrClk = temp; @@ -867,6 +868,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv; + sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; + sysInfo->freqUART = sysInfo->freqProcessor * pllmr0_ccdv; } diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 582c781..60756c3 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -297,7 +297,7 @@ _start_440: | Core bug fix. Clear the esr +-----------------------------------------------------------------*/ li r0,0 - mtspr esr,r0 + mtspr SPRN_ESR,r0 /*----------------------------------------------------------------*/ /* Clear and set up some registers. */ /*----------------------------------------------------------------*/ @@ -305,16 +305,16 @@ _start_440: dccci r0,r0 /* NOTE: operands not used for 440 */ sync li r0,0 - mtspr srr0,r0 - mtspr srr1,r0 - mtspr csrr0,r0 - mtspr csrr1,r0 + mtspr SPRN_SRR0,r0 + mtspr SPRN_SRR1,r0 + mtspr SPRN_CSRR0,r0 + mtspr SPRN_CSRR1,r0 /* NOTE: 440GX adds machine check status regs */ #if defined(CONFIG_440) && !defined(CONFIG_440GP) - mtspr mcsrr0,r0 - mtspr mcsrr1,r0 - mfspr r1,mcsr - mtspr mcsr,r1 + mtspr SPRN_MCSRR0,r0 + mtspr SPRN_MCSRR1,r0 + mfspr r1,SPRN_MCSR + mtspr SPRN_MCSR,r1 #endif /*----------------------------------------------------------------*/ @@ -326,27 +326,27 @@ _start_440: */ lis r1,0x0030 /* store gathering & broadcast disable */ ori r1,r1,0x6000 /* cache touch */ - mtspr ccr0,r1 + mtspr SPRN_CCR0,r1 /*----------------------------------------------------------------*/ /* Initialize debug */ /*----------------------------------------------------------------*/ - mfspr r1,dbcr0 + mfspr r1,SPRN_DBCR0 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ bne skip_debug_init /* if set, don't clear debug register */ - mtspr dbcr0,r0 - mtspr dbcr1,r0 - mtspr dbcr2,r0 - mtspr iac1,r0 - mtspr iac2,r0 - mtspr iac3,r0 - mtspr dac1,r0 - mtspr dac2,r0 - mtspr dvc1,r0 - mtspr dvc2,r0 - - mfspr r1,dbsr - mtspr dbsr,r1 /* Clear all valid bits */ + mtspr SPRN_DBCR0,r0 + mtspr SPRN_DBCR1,r0 + mtspr SPRN_DBCR2,r0 + mtspr SPRN_IAC1,r0 + mtspr SPRN_IAC2,r0 + mtspr SPRN_IAC3,r0 + mtspr SPRN_DAC1,r0 + mtspr SPRN_DAC2,r0 + mtspr SPRN_DVC1,r0 + mtspr SPRN_DVC2,r0 + + mfspr r1,SPRN_DBSR + mtspr SPRN_DBSR,r1 /* Clear all valid bits */ skip_debug_init: #if defined (CONFIG_440SPE) @@ -364,68 +364,68 @@ skip_debug_init: | j. TCS: Timebase increments from CPU clock. +-----------------------------------------------------------------*/ li r0,0 - mtspr ccr1, r0 + mtspr SPRN_CCR1, r0 /*----------------------------------------------------------------+ | Reset the timebase. | The previous write to CCR1 sets the timebase source. +-----------------------------------------------------------------*/ - mtspr tbl, r0 - mtspr tbu, r0 + mtspr SPRN_TBWL, r0 + mtspr SPRN_TBWU, r0 #endif /*----------------------------------------------------------------*/ /* Setup interrupt vectors */ /*----------------------------------------------------------------*/ - mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */ + mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */ li r1,0x0100 - mtspr ivor0,r1 /* Critical input */ + mtspr SPRN_IVOR0,r1 /* Critical input */ li r1,0x0200 - mtspr ivor1,r1 /* Machine check */ + mtspr SPRN_IVOR1,r1 /* Machine check */ li r1,0x0300 - mtspr ivor2,r1 /* Data storage */ + mtspr SPRN_IVOR2,r1 /* Data storage */ li r1,0x0400 - mtspr ivor3,r1 /* Instruction storage */ + mtspr SPRN_IVOR3,r1 /* Instruction storage */ li r1,0x0500 - mtspr ivor4,r1 /* External interrupt */ + mtspr SPRN_IVOR4,r1 /* External interrupt */ li r1,0x0600 - mtspr ivor5,r1 /* Alignment */ + mtspr SPRN_IVOR5,r1 /* Alignment */ li r1,0x0700 - mtspr ivor6,r1 /* Program check */ + mtspr SPRN_IVOR6,r1 /* Program check */ li r1,0x0800 - mtspr ivor7,r1 /* Floating point unavailable */ + mtspr SPRN_IVOR7,r1 /* Floating point unavailable */ li r1,0x0c00 - mtspr ivor8,r1 /* System call */ + mtspr SPRN_IVOR8,r1 /* System call */ li r1,0x0a00 - mtspr ivor9,r1 /* Auxiliary Processor unavailable */ + mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */ li r1,0x0900 - mtspr ivor10,r1 /* Decrementer */ + mtspr SPRN_IVOR10,r1 /* Decrementer */ li r1,0x1300 - mtspr ivor13,r1 /* Data TLB error */ + mtspr SPRN_IVOR13,r1 /* Data TLB error */ li r1,0x1400 - mtspr ivor14,r1 /* Instr TLB error */ + mtspr SPRN_IVOR14,r1 /* Instr TLB error */ li r1,0x2000 - mtspr ivor15,r1 /* Debug */ + mtspr SPRN_IVOR15,r1 /* Debug */ /*----------------------------------------------------------------*/ /* Configure cache regions */ /*----------------------------------------------------------------*/ - mtspr inv0,r0 - mtspr inv1,r0 - mtspr inv2,r0 - mtspr inv3,r0 - mtspr dnv0,r0 - mtspr dnv1,r0 - mtspr dnv2,r0 - mtspr dnv3,r0 - mtspr itv0,r0 - mtspr itv1,r0 - mtspr itv2,r0 - mtspr itv3,r0 - mtspr dtv0,r0 - mtspr dtv1,r0 - mtspr dtv2,r0 - mtspr dtv3,r0 + mtspr SPRN_INV0,r0 + mtspr SPRN_INV1,r0 + mtspr SPRN_INV2,r0 + mtspr SPRN_INV3,r0 + mtspr SPRN_DNV0,r0 + mtspr SPRN_DNV1,r0 + mtspr SPRN_DNV2,r0 + mtspr SPRN_DNV3,r0 + mtspr SPRN_ITV0,r0 + mtspr SPRN_ITV1,r0 + mtspr SPRN_ITV2,r0 + mtspr SPRN_ITV3,r0 + mtspr SPRN_DTV0,r0 + mtspr SPRN_DTV1,r0 + mtspr SPRN_DTV2,r0 + mtspr SPRN_DTV3,r0 /*----------------------------------------------------------------*/ /* Cache victim limits */ @@ -434,25 +434,30 @@ skip_debug_init: */ lis r1,0x0001 ori r1,r1,0xf800 - mtspr ivlim,r1 - mtspr dvlim,r1 + mtspr SPRN_IVLIM,r1 + mtspr SPRN_DVLIM,r1 /*----------------------------------------------------------------+ |Initialize MMUCR[STID] = 0. +-----------------------------------------------------------------*/ - mfspr r0,mmucr + mfspr r0,SPRN_MMUCR addis r1,0,0xFFFF ori r1,r1,0xFF00 and r0,r0,r1 - mtspr mmucr,r0 + mtspr SPRN_MMUCR,r0 /*----------------------------------------------------------------*/ /* Clear all TLB entries -- TID = 0, TS = 0 */ /*----------------------------------------------------------------*/ addis r0,0,0x0000 - li r1,0x003f /* 64 TLB entries */ - mtctr r1 +#ifdef CONFIG_SYS_RAMBOOT li r4,0 /* Start with TLB #0 */ +#else + li r4,1 /* Start with TLB #1 */ +#endif + li r1,64 /* 64 TLB entries */ + sub r1,r1,r4 /* calculate last TLB # */ + mtctr r1 rsttlb: #ifdef CONFIG_SYS_RAMBOOT tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */ @@ -516,9 +521,9 @@ tlbnx2: addi r4,r4,1 /* Next TLB */ b _start 3: li r0,0 - mtspr srr1,r0 /* Keep things disabled for now */ + mtspr SPRN_SRR1,r0 /* Keep things disabled for now */ mflr r1 - mtspr srr0,r1 + mtspr SPRN_SRR0,r1 rfi #endif /* CONFIG_440 */ @@ -622,12 +627,12 @@ _start: /*----------------------------------------------------------------*/ li r0,0x0000 lis r1,0xffff - mtspr dec,r0 /* prevent dec exceptions */ - mtspr tbl,r0 /* prevent fit & wdt exceptions */ - mtspr tbu,r0 - mtspr tsr,r1 /* clear all timer exception status */ - mtspr tcr,r0 /* disable all */ - mtspr esr,r0 /* clear exception syndrome register */ + mtspr SPRN_DEC,r0 /* prevent dec exceptions */ + mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */ + mtspr SPRN_TBWU,r0 + mtspr SPRN_TSR,r1 /* clear all timer exception status */ + mtspr SPRN_TCR,r0 /* disable all */ + mtspr SPRN_ESR,r0 /* clear exception syndrome register */ mtxer r0 /* clear integer exception register */ /*----------------------------------------------------------------*/ @@ -638,10 +643,10 @@ _start: #if defined(CONFIG_SYS_INIT_DBCR) lis r1,0xffff ori r1,r1,0xffff - mtspr dbsr,r1 /* Clear all status bits */ + mtspr SPRN_DBSR,r1 /* Clear all status bits */ lis r0,CONFIG_SYS_INIT_DBCR@h ori r0,r0,CONFIG_SYS_INIT_DBCR@l - mtspr dbcr0,r0 + mtspr SPRN_DBCR0,r0 isync #endif @@ -680,17 +685,17 @@ _start: /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ lis r1,0x0201 ori r1,r1,0xf808 - mtspr dvlim,r1 + mtspr SPRN_DVLIM,r1 lis r1,0x0808 ori r1,r1,0x0808 - mtspr dnv0,r1 - mtspr dnv1,r1 - mtspr dnv2,r1 - mtspr dnv3,r1 - mtspr dtv0,r1 - mtspr dtv1,r1 - mtspr dtv2,r1 - mtspr dtv3,r1 + mtspr SPRN_DNV0,r1 + mtspr SPRN_DNV1,r1 + mtspr SPRN_DNV2,r1 + mtspr SPRN_DNV3,r1 + mtspr SPRN_DTV0,r1 + mtspr SPRN_DTV1,r1 + mtspr SPRN_DTV2,r1 + mtspr SPRN_DTV3,r1 msync isync #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ @@ -809,7 +814,7 @@ _start: /* Set up some machine state registers. */ /*----------------------------------------------------------------------- */ addi r0,r0,0x0000 /* initialize r0 to zero */ - mtspr esr,r0 /* clear Exception Syndrome Reg */ + mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */ mttcr r0 /* timer control register */ mtexier r0 /* disable all interrupts */ addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ @@ -919,7 +924,7 @@ _start: /*----------------------------------------------------------------------- */ addi r4,r0,0x0000 #if !defined(CONFIG_405EX) - mtspr sgr,r4 + mtspr SPRN_SGR,r4 #else /* * On 405EX, completely clearing the SGR leads to PPC hangup @@ -928,9 +933,9 @@ _start: */ lis r3,0x0000 ori r3,r3,0x7FFC - mtspr sgr,r3 + mtspr SPRN_SGR,r3 #endif - mtspr dcwr,r4 + mtspr SPRN_DCWR,r4 mtesr r4 /* clear Exception Syndrome Reg */ mttcr r4 /* clear Timer Control Reg */ mtxer r4 /* clear Fixed-Point Exception Reg */ @@ -1266,8 +1271,8 @@ crit_return: REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) - mtspr csrr0,r2 - mtspr csrr1,r0 + mtspr SPRN_CSRR0,r2 + mtspr SPRN_CSRR1,r0 lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) @@ -1297,8 +1302,8 @@ mck_return: REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) - mtspr mcsrr0,r2 - mtspr mcsrr1,r0 + mtspr SPRN_MCSRR0,r2 + mtspr SPRN_MCSRR1,r0 lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) @@ -1448,17 +1453,17 @@ relocate_code: /* set TFLOOR/NFLOOR to 0 again */ lis r6,0x0001 ori r6,r6,0xf800 - mtspr dvlim,r6 + mtspr SPRN_DVLIM,r6 lis r6,0x0000 ori r6,r6,0x0000 - mtspr dnv0,r6 - mtspr dnv1,r6 - mtspr dnv2,r6 - mtspr dnv3,r6 - mtspr dtv0,r6 - mtspr dtv1,r6 - mtspr dtv2,r6 - mtspr dtv3,r6 + mtspr SPRN_DNV0,r6 + mtspr SPRN_DNV1,r6 + mtspr SPRN_DNV2,r6 + mtspr SPRN_DNV3,r6 + mtspr SPRN_DTV0,r6 + mtspr SPRN_DTV1,r6 + mtspr SPRN_DTV2,r6 + mtspr SPRN_DTV3,r6 msync isync #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ @@ -1478,8 +1483,8 @@ relocate_code: isync /* Clear all potential pending exceptions */ - mfspr r1,mcsr - mtspr mcsr,r1 + mfspr r1,SPRN_MCSR + mtspr SPRN_MCSR,r1 #ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ #else @@ -1723,9 +1728,9 @@ trap_init: __440_msr_set: addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ - mtspr srr1,r7 + mtspr SPRN_SRR1,r7 mflr r7 - mtspr srr0,r7 + mtspr SPRN_SRR0,r7 rfi __440_msr_continue: #endif @@ -2059,7 +2064,7 @@ pll_wait: * Not sure if this is needed... */ addis r3,0,0x1000 - mtspr dbcr0,r3 /* This will cause a CPU core reset, and */ + mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */ /* execution will continue from the poweron */ /* vector of 0xfffffffc */ #endif /* CONFIG_405EP */ |