summaryrefslogtreecommitdiff
path: root/cpu/ppc4xx
diff options
context:
space:
mode:
Diffstat (limited to 'cpu/ppc4xx')
-rw-r--r--cpu/ppc4xx/sdram.c2
-rw-r--r--cpu/ppc4xx/serial.c4
-rw-r--r--cpu/ppc4xx/spd_sdram.c4
-rw-r--r--cpu/ppc4xx/start.S2
4 files changed, 6 insertions, 6 deletions
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index e31d59d..faeea5c 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -379,7 +379,7 @@ long int initdram(int board_type)
/*
* Enable the controller, then wait for DCEN to complete
*/
- mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index 3749811..ad3ca6e 100644
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -635,7 +635,7 @@ void serial_setbrg (void)
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
-#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
+#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
#if defined(CONFIG_SERIAL_MULTI)
out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
index c0a6933..c24456b 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -1007,9 +1007,9 @@ void program_cfg0(unsigned long* dimm_populated,
}
/*
- * program Page Management Unit
+ * program Page Management Unit (0 == enabled)
*/
- cfg0 |= SDRAM_CFG0_PMUD;
+ cfg0 &= ~SDRAM_CFG0_PMUD;
/*
* program Memory Controller Options 0
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 0a6f81d..699fa7f 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -159,7 +159,7 @@ _start_440:
| Core bug fix. Clear the esr
+-----------------------------------------------------------------*/
li r0,0
- mtspr esr,r0
+ mtspr esr,r0
/*----------------------------------------------------------------*/
/* Clear and set up some registers. */
/*----------------------------------------------------------------*/