diff options
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/44x_spd_ddr2.c | 2 | ||||
| -rw-r--r-- | cpu/ppc4xx/cpu.c | 30 | ||||
| -rw-r--r-- | cpu/ppc4xx/i2c.c | 4 | ||||
| -rw-r--r-- | cpu/ppc4xx/start.S | 54 |
4 files changed, 55 insertions, 35 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index b56629b..2ecd3e4 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -1124,7 +1124,7 @@ static void program_codt(unsigned long *dimm_populated, modt3 = 0x00000000; } } - } else { + } else { codt |= SDRAM_CODT_DQS_2_5_V_DDR1; modt0 = 0x00000000; modt1 = 0x00000000; diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 2d8740c..8e6bc84 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -125,6 +125,7 @@ int i2c_bootrom_enabled(void) return (val & SDR0_SDCS_SDD); #endif } +#endif #if defined(CONFIG_440GX) #define SDR0_PINSTP_SHIFT 29 @@ -178,16 +179,37 @@ static char *bootstrap_str[] = { }; #endif +#if defined(CONFIG_405EZ) +#define SDR0_PINSTP_SHIFT 28 +static char *bootstrap_str[] = { + "EBC (8 bits)", + "SPI (fast)", + "NAND (512 page, 4 addr cycle)", + "I2C (Addr 0x50)", + "EBC (32 bits)", + "I2C (Addr 0x50)", + "NAND (2K page, 5 addr cycle)", + "I2C (Addr 0x50)", + "EBC (16 bits)", + "Reserved", + "NAND (2K page, 4 addr cycle)", + "I2C (Addr 0x50)", + "NAND (512 page, 3 addr cycle)", + "I2C (Addr 0x50)", + "SPI (slow)", + "I2C (Addr 0x50)", +}; +#endif + #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) { unsigned long val; - mfsdr(sdr_pinstp, val); - return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT); + mfsdr(SDR_PINSTP, val); + return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT); } #endif /* SDR0_PINSTP_SHIFT */ -#endif #if defined(CONFIG_440) @@ -403,11 +425,11 @@ int checkcpu (void) #if defined(I2C_BOOTROM) printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); +#endif /* I2C_BOOTROM */ #if defined(SDR0_PINSTP_SHIFT) printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A'); printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); #endif /* SDR0_PINSTP_SHIFT */ -#endif /* I2C_BOOTROM */ #if defined(CONFIG_PCI) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c index 8f4da86..47c264e 100644 --- a/cpu/ppc4xx/i2c.c +++ b/cpu/ppc4xx/i2c.c @@ -91,7 +91,6 @@ static void _i2c_bus_reset(void) void i2c_init(int speed, int slaveadd) { - sys_info_t sysInfo; unsigned long freqOPB; int val, divisor; int bus; @@ -124,8 +123,7 @@ void i2c_init(int speed, int slaveadd) /* Clock divide Register */ /* get OPB frequency */ - get_sys_info(&sysInfo); - freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv; + freqOPB = get_OPB_freq(); /* set divisor according to freqOPB */ divisor = (freqOPB - 1) / 10000000; if (divisor == 0) diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 3b1586c..a96083c 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1892,11 +1892,11 @@ pll_wait: #endif /* CONFIG_405EP */ #if defined(CONFIG_440) -#define function_prolog(func_name) .text; \ +#define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ func_name: -#define function_epilog(func_name) .type func_name,@function; \ +#define function_epilog(func_name) .type func_name,@function; \ .size func_name,.-func_name /*----------------------------------------------------------------------------+ @@ -1952,13 +1952,13 @@ pll_wait: +----------------------------------------------------------------------------*/ function_prolog(dcbz_area) rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ra2 - addi r5,r5,0x0001 -..d_ra2:mtctr r5 -..d_ag2:dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag2 + rlwinm r5,r4,27,5,31 + beq ..d_ra2 + addi r5,r5,0x0001 +..d_ra2:mtctr r5 +..d_ag2:dcbz r0,r3 + addi r3,r3,32 + bdnz ..d_ag2 sync blr function_epilog(dcbz_area) @@ -1967,26 +1967,26 @@ pll_wait: | dflush. Assume 32K at vector address is cachable. +----------------------------------------------------------------------------*/ function_prolog(dflush) - mfmsr r9 - rlwinm r8,r9,0,15,13 - rlwinm r8,r8,0,17,15 - mtmsr r8 - addi r3,r0,0x0000 - mtspr dvlim,r3 - mfspr r3,ivpr - addi r4,r0,1024 - mtctr r4 + mfmsr r9 + rlwinm r8,r9,0,15,13 + rlwinm r8,r8,0,17,15 + mtmsr r8 + addi r3,r0,0x0000 + mtspr dvlim,r3 + mfspr r3,ivpr + addi r4,r0,1024 + mtctr r4 ..dflush_loop: - lwz r6,0x0(r3) - addi r3,r3,32 - bdnz ..dflush_loop - addi r3,r3,-32 - mtctr r4 -..ag: dcbf r0,r3 - addi r3,r3,-32 - bdnz ..ag + lwz r6,0x0(r3) + addi r3,r3,32 + bdnz ..dflush_loop + addi r3,r3,-32 + mtctr r4 +..ag: dcbf r0,r3 + addi r3,r3,-32 + bdnz ..ag sync - mtmsr r9 + mtmsr r9 blr function_epilog(dflush) #endif /* CONFIG_440 */ |