diff options
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/405gp_pci.c | 33 | ||||
| -rw-r--r-- | cpu/ppc4xx/440gx_enet.c | 46 |
2 files changed, 53 insertions, 26 deletions
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index d3f6b23..c9e2e9c 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -411,15 +411,23 @@ void pci_440_init (struct pci_controller *hose) /*--------------------------------------------------------------------------+ * The PCI initialization sequence enable bit must be set ... if not abort - * pci setup since updating the bit requires chip reset. + * pci setup since updating the bit requires chip reset. *--------------------------------------------------------------------------*/ - strap = mfdcr(cpc0_strp1); - if( (strap & 0x00040000) == 0 ){ - printf("PCI: CPC0_STRP1[PISE] not set.\n"); - printf("PCI: Configuration aborted.\n"); - return; - } - +#if defined (CONFIG_440_GX) + mfsdr(sdr_sdstp1,strap); + if ( (strap & 0x00010000) == 0 ){ + printf("PCI: SDR0_STRP1[PISE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } +#else + strap = mfdcr(cpc0_strp1); + if( (strap & 0x00040000) == 0 ){ + printf("PCI: CPC0_STRP1[PISE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } +#endif /*--------------------------------------------------------------------------+ * PCI controller init *--------------------------------------------------------------------------*/ @@ -463,8 +471,13 @@ void pci_440_init (struct pci_controller *hose) out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif - out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ - out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ +#if defined(CONFIG_440_GX) + out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ + out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ +#else + out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ + out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ +#endif /*--------------------------------------------------------------------------+ * PCI master init: default is one 256MB region for PCI memory: diff --git a/cpu/ppc4xx/440gx_enet.c b/cpu/ppc4xx/440gx_enet.c index 617a174..4502085 100644 --- a/cpu/ppc4xx/440gx_enet.c +++ b/cpu/ppc4xx/440gx_enet.c @@ -116,6 +116,10 @@ #undef INFO_440_ENET +#define BI_PHYMODE_NONE 0 +#define BI_PHYMODE_ZMII 1 +#define BI_PHYMODE_RGMII 2 + /*-----------------------------------------------------------------------------+ * Global variables. TX and RX descriptors and buffers. *-----------------------------------------------------------------------------*/ @@ -316,11 +320,12 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis) break; } + bis->bi_phynum[devnum] = reg; + /* Reset the phy */ miiphy_reset (reg); /* Start/Restart autonegotiation */ -/* miiphy_write(reg, PHY_BMCR, 0x9340); */ phy_setup_aneg (reg); udelay (1000); @@ -579,13 +584,6 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis) irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2), (interrupt_handler_t *) enetInt, dev); } -#if 0 /* done by irq_install_handler */ - /* set up interrupt handler */ - /* setup interrupt controller to take interrupts from the MAL & - EMAC */ - mtdcr (uicsr, 0xffffffff); /* clear pending interrupts */ - mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF); -#endif mtmsr (msr); /* enable interrupts again */ @@ -1027,33 +1025,49 @@ int ppc_440x_eth_initialize (bd_t * bis) pfc1 &= ~(0x01e00000); pfc1 |= 0x01200000; mtsdr (sdr_pfc1, pfc1); + /* set phy num and mode */ + bis->bi_phynum[0] = CONFIG_PHY_ADDR; + bis->bi_phynum[1] = CONFIG_PHY1_ADDR; + bis->bi_phynum[2] = CONFIG_PHY2_ADDR; + bis->bi_phynum[3] = CONFIG_PHY3_ADDR; + bis->bi_phymode[0] = 0; + bis->bi_phymode[1] = 0; + bis->bi_phymode[2] = 2; + bis->bi_phymode[3] = 2; for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) { /* See if we can actually bring up the interface, otherwise, skip it */ switch (eth_num) { case 0: - if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) + if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; continue; + } break; case 1: - if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == - 0) + if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; continue; + } break; case 2: - if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == - 0) + if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; continue; + } break; case 3: - if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == - 0) + if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; continue; + } break; default: - if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) + if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; continue; + } break; } |