diff options
Diffstat (limited to 'cpu/ppc4xx/cpu.c')
| -rw-r--r-- | cpu/ppc4xx/cpu.c | 104 |
1 files changed, 72 insertions, 32 deletions
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index f4a7208..2d8740c 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -41,8 +41,15 @@ DECLARE_GLOBAL_DATA_PTR; #endif +#if defined(CONFIG_BOARD_RESET) +void board_reset(void); +#endif + #if defined(CONFIG_440) #define FREQ_EBC (sys_info.freqEPB) +#elif defined(CONFIG_405EZ) +#define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \ + sys_info.pllExtBusDiv) #else #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv) #endif @@ -84,14 +91,18 @@ int pci_arbiter_enabled(void) return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); #endif -#if defined(CONFIG_440GX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long val; - mfsdr(sdr_sdstp1, val); - return (val & SDR0_SDSTP1_PAE_MASK); + mfsdr(sdr_xcr, val); + return (val & 0x80000000); +#endif +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + unsigned long val; + + mfsdr(sdr_pci0, val); + return (val & 0x80000000); #endif } #endif @@ -201,7 +212,8 @@ int checkcpu (void) puts("AMCC PowerPC 4"); -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) puts("05"); #endif #if defined(CONFIG_440) @@ -249,6 +261,10 @@ int checkcpu (void) puts("EP Rev. B"); break; + case PVR_405EZ_RA: + puts("EZ Rev. A"); + break; + #if defined(CONFIG_440) case PVR_440GP_RB: puts("GP Rev. B"); @@ -308,40 +324,68 @@ int checkcpu (void) #endif /* CONFIG_440GR */ #endif /* CONFIG_440 */ - case PVR_440EPX1_RA: +#ifdef CONFIG_440EPX + case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("EPx Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; - case PVR_440EPX2_RA: + case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("EPx Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; +#endif /* CONFIG_440EPX */ - case PVR_440GRX1_RA: +#ifdef CONFIG_440GRX + case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("GRx Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; - case PVR_440GRX2_RA: + case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("GRx Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; +#endif /* CONFIG_440GRX */ + + case PVR_440SP_6_RAB: + puts("SP Rev. A/B"); + strcpy(addstr, "RAID 6 support"); + break; - case PVR_440SP_RA: - puts("SP Rev. A"); + case PVR_440SP_RAB: + puts("SP Rev. A/B"); + strcpy(addstr, "No RAID 6 support"); break; - case PVR_440SP_RB: - puts("SP Rev. B"); + case PVR_440SP_6_RC: + puts("SP Rev. C"); + strcpy(addstr, "RAID 6 support"); + break; + + case PVR_440SP_RC: + puts("SP Rev. C"); + strcpy(addstr, "No RAID 6 support"); + break; + + case PVR_440SPe_6_RA: + puts("SPe Rev. A"); + strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RA: puts("SPe Rev. A"); + strcpy(addstr, "No RAID 6 support"); + break; + + case PVR_440SPe_6_RB: + puts("SPe Rev. B"); + strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RB: puts("SPe Rev. B"); + strcpy(addstr, "No RAID 6 support"); break; default: @@ -350,9 +394,9 @@ int checkcpu (void) } printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), - sys_info.freqPLB / 1000000, - sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, - FREQ_EBC / 1000000); + sys_info.freqPLB / 1000000, + get_OPB_freq() / 1000000, + FREQ_EBC / 1000000); if (addstr[0] != 0) printf(" %s\n", addstr); @@ -382,7 +426,7 @@ int checkcpu (void) putc('\n'); #endif -#if defined(CONFIG_405EP) +#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) printf (" 16 kB I-Cache 16 kB D-Cache"); #elif defined(CONFIG_440) printf (" 32 kB I-Cache 32 kB D-Cache"); @@ -411,7 +455,7 @@ int ppc440spe_revB() { unsigned int pvr; pvr = get_pvr(); - if (pvr == PVR_440SPe_RB) + if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB)) return 1; else return 0; @@ -422,23 +466,19 @@ int ppc440spe_revB() { int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE) - /*give reset to BCSR*/ - *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09; - +#if defined(CONFIG_BOARD_RESET) + board_reset(); +#else +#if defined(CFG_4xx_RESET_TYPE) + mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28); #else - /* * Initiate system reset in debug control register DBCR */ - __asm__ __volatile__("lis 3, 0x3000" ::: "r3"); -#if defined(CONFIG_440) - __asm__ __volatile__("mtspr 0x134, 3"); -#else - __asm__ __volatile__("mtspr 0x3f2, 3"); -#endif + mtspr(dbcr0, 0x30000000); +#endif /* defined(CFG_4xx_RESET_TYPE) */ +#endif /* defined(CONFIG_BOARD_RESET) */ -#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/ return 1; } |