diff options
Diffstat (limited to 'cpu/mpc8xx')
| -rw-r--r-- | cpu/mpc8xx/cpu_init.c | 1 | ||||
| -rw-r--r-- | cpu/mpc8xx/fec.c | 10 | ||||
| -rw-r--r-- | cpu/mpc8xx/serial.c | 7 | ||||
| -rw-r--r-- | cpu/mpc8xx/speed.c | 9 |
4 files changed, 20 insertions, 7 deletions
diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c index 1a7111f..c79e578 100644 --- a/cpu/mpc8xx/cpu_init.c +++ b/cpu/mpc8xx/cpu_init.c @@ -161,6 +161,7 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_RMU) || \ defined(CONFIG_RPXCLASSIC) || \ defined(CONFIG_RPXLITE) || \ + defined(CONFIG_SPC1920) || \ defined(CONFIG_SPD823TS) memctl->memc_br0 = CFG_BR0_PRELIM; diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 6006478..6d2755e 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -396,8 +396,10 @@ static void fec_pin_init(int fecidx) * * to 2.5 MHz. * * This MDC frequency is equal to system clock / (2 * MII_SPEED). * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz. + * + * All MII configuration is done via FEC1 registers: */ - fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; + immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; #if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2) /* our PHYs are the limit at 2.5 MHz */ @@ -508,8 +510,6 @@ static void fec_pin_init(int fecidx) #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ #if !defined(CONFIG_RMII) - -#warning this configuration is not tested; please report if it works immr->im_cpm.cp_pepar |= 0x0003fffc; immr->im_cpm.cp_pedir |= 0x0003fffc; immr->im_cpm.cp_peso &= ~0x000087fc; @@ -822,6 +822,7 @@ static void fec_halt(struct eth_device* dev) #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */ +#define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */ /* send command to phy using mii, wait for result */ static uint @@ -907,6 +908,9 @@ static int mii_discover_phy(struct eth_device *dev) case PHY_ID_DM9161: printf("Davicom DM9161\n"); break; + case PHY_ID_KSM8995M: + printf("MICREL KS8995M\n"); + break; default: printf("0x%08x\n", phytype); break; diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index 26a82cc..8ae584f 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -227,9 +227,12 @@ static int smc_init (void) sp->smc_smcm = 0; sp->smc_smce = 0xff; - /* Set up the baud rate generator. - */ +#ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */ + *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff; +#else + /* Set up the baud rate generator */ smc_setbrg (); +#endif /* Make the first buffer the only buffer. */ diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 57f91c0..101d5f9 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -259,7 +259,11 @@ int get_clocks_866 (void) */ sccr_reg = immr->im_clkrst.car_sccr; sccr_reg &= ~SCCR_EBDF11; +#if defined(CONFIG_TQM885D) + if (gd->cpu_clk <= 80000000) { +#else if (gd->cpu_clk <= 66000000) { +#endif sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ gd->bus_clk = gd->cpu_clk; } else { @@ -360,7 +364,8 @@ static long init_pll_866 (long clk) #endif /* CONFIG_8xx_CPUCLK_DEFAULT */ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ + && !defined(CONFIG_TQM885D) /* * Adjust sdram refresh rate to actual CPU clock * and set timebase source according to actual CPU clock @@ -384,6 +389,6 @@ int adjust_sdram_tbs_8xx (void) return (0); } -#endif /* CONFIG_TQM8xxL/M, !TQM866M */ +#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ /* ------------------------------------------------------------------------- */ |