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-rw-r--r--cpu/mpc8xx/commproc.c12
-rw-r--r--cpu/mpc8xx/cpu.c32
-rw-r--r--cpu/mpc8xx/cpu_init.c126
-rw-r--r--cpu/mpc8xx/fec.c40
-rw-r--r--cpu/mpc8xx/i2c.c44
-rw-r--r--cpu/mpc8xx/interrupts.c16
-rw-r--r--cpu/mpc8xx/kgdb.S8
-rw-r--r--cpu/mpc8xx/lcd.c50
-rw-r--r--cpu/mpc8xx/scc.c18
-rw-r--r--cpu/mpc8xx/serial.c50
-rw-r--r--cpu/mpc8xx/speed.c28
-rw-r--r--cpu/mpc8xx/spi.c40
-rw-r--r--cpu/mpc8xx/start.S22
-rw-r--r--cpu/mpc8xx/upatch.c22
-rw-r--r--cpu/mpc8xx/video.c10
15 files changed, 260 insertions, 258 deletions
diff --git a/cpu/mpc8xx/commproc.c b/cpu/mpc8xx/commproc.c
index 07c763c..a87a0dc 100644
--- a/cpu/mpc8xx/commproc.c
+++ b/cpu/mpc8xx/commproc.c
@@ -26,7 +26,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
int dpram_init (void)
{
@@ -82,14 +82,14 @@ uint dpram_base_align (uint align)
return (gd->dp_alloc_base + mask) & ~mask;
}
-#endif /* CFG_ALLOC_DPRAM */
+#endif /* CONFIG_SYS_ALLOC_DPRAM */
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
void post_word_store (ulong a)
{
volatile void *save_addr =
- ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR;
+ ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR;
*(volatile ulong *) save_addr = a;
}
@@ -97,7 +97,7 @@ void post_word_store (ulong a)
ulong post_word_load (void)
{
volatile void *save_addr =
- ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR;
+ ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR;
return *(volatile ulong *) save_addr;
}
@@ -109,7 +109,7 @@ ulong post_word_load (void)
void bootcount_store (ulong a)
{
volatile ulong *save_addr =
- (volatile ulong *)( ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem +
+ (volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem +
CPM_BOOTCOUNT_ADDR );
save_addr[0] = a;
@@ -119,7 +119,7 @@ void bootcount_store (ulong a)
ulong bootcount_load (void)
{
volatile ulong *save_addr =
- (volatile ulong *)( ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem +
+ (volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem +
CPM_BOOTCOUNT_ADDR );
if (save_addr[1] != BOOTCOUNT_MAGIC)
diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c
index ec6a3fd..420eaed 100644
--- a/cpu/mpc8xx/cpu.c
+++ b/cpu/mpc8xx/cpu.c
@@ -137,13 +137,13 @@ static int check_CPU (long clock, uint pvr, uint immr)
printf ("unknown M%s (0x%08x)", id_str, k);
-#if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX)
+#if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
strmhz (buf, clock),
- CFG_8xx_CPUCLK_MIN / 1000000,
- ((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
- CFG_8xx_CPUCLK_MAX / 1000000,
- ((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
+ CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
+ ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
+ CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
+ ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
);
#else
printf (" at %s MHz: ", strmhz (buf, clock));
@@ -375,7 +375,7 @@ int checkcpu (void)
int checkicache (void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
u32 cacheon = rd_ic_cst () & IDC_ENABLED;
@@ -422,7 +422,7 @@ int checkicache (void)
int checkdcache (void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
u32 cacheon = rd_dc_cst () & IDC_ENABLED;
@@ -462,7 +462,7 @@ void upmconfig (uint upm, uint * table, uint size)
{
uint i;
uint addr = 0;
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
for (i = 0; i < size; i++) {
@@ -480,7 +480,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong msr, addr;
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
@@ -495,16 +495,16 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
-#ifdef CFG_RESET_ADDRESS
- addr = CFG_RESET_ADDRESS;
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
- * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
+ * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
* - sizeof (ulong) is usually a valid address. Better pick an address
- * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
+ * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
* "(ulong)-1" used to be a good choice for many systems...
*/
- addr = CFG_MONITOR_BASE - sizeof (ulong);
+ addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
#endif
((void (*)(void)) addr) ();
return 1;
@@ -525,7 +525,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
disable_interrupts ();
/* make sure the watchdog is running */
- reset_8xx_watchdog ((immap_t *) CFG_IMMR);
+ reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
/* wait for watchdog reset */
while (1) {};
@@ -591,7 +591,7 @@ void watchdog_reset (void)
{
int re_enable = disable_interrupts ();
- reset_8xx_watchdog ((immap_t *) CFG_IMMR);
+ reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
if (re_enable)
enable_interrupts ();
}
diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c
index 5c43eca..eb0091b 100644
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -27,12 +27,12 @@
#include <mpc8xx.h>
#include <commproc.h>
-#if defined(CFG_RTCSC) || defined(CFG_RMDS)
+#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
DECLARE_GLOBAL_DATA_PTR;
#endif
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \
- defined(CFG_SMC_UCODE_PATCH)
+#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
+ defined(CONFIG_SYS_SMC_UCODE_PATCH)
void cpm_load_patch (volatile immap_t * immr);
#endif
@@ -47,7 +47,7 @@ void cpu_init_f (volatile immap_t * immr)
{
#ifndef CONFIG_MBX
volatile memctl8xx_t *memctl = &immr->im_memctl;
-# ifdef CFG_PLPRCR
+# ifdef CONFIG_SYS_PLPRCR
ulong mfmask;
# endif
#endif
@@ -55,7 +55,7 @@ void cpu_init_f (volatile immap_t * immr)
/* SYPCR - contains watchdog control (11-9) */
- immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
+ immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
#if defined(CONFIG_WATCHDOG)
reset_8xx_watchdog (immr);
@@ -63,27 +63,27 @@ void cpu_init_f (volatile immap_t * immr)
/* SIUMCR - contains debug pin configuration (11-6) */
#ifndef CONFIG_SVM_SC8xx
- immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
+ immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
#else
- immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
+ immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
#endif
/* initialize timebase status and control register (11-26) */
/* unlock TBSCRK */
immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
- immr->im_sit.sit_tbscr = CFG_TBSCR;
+ immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
/* initialize the PIT (11-31) */
immr->im_sitk.sitk_piscrk = KAPWR_KEY;
- immr->im_sit.sit_piscr = CFG_PISCR;
+ immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
/* System integration timers. Don't change EBDF! (15-27) */
immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
reg = immr->im_clkrst.car_sccr;
reg &= SCCR_MASK;
- reg |= CFG_SCCR;
+ reg |= CONFIG_SYS_SCCR;
immr->im_clkrst.car_sccr = reg;
/* PLL (CPU clock) settings (15-30) */
@@ -92,25 +92,25 @@ void cpu_init_f (volatile immap_t * immr)
#ifndef CONFIG_MBX /* MBX board does things different */
- /* If CFG_PLPRCR (set in the various *_config.h files) tries to
- * set the MF field, then just copy CFG_PLPRCR over car_plprcr,
- * otherwise OR in CFG_PLPRCR so we do not change the current MF
+ /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
+ * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
+ * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
* field value.
*
* For newer (starting MPC866) chips PLPRCR layout is different.
*/
-#ifdef CFG_PLPRCR
+#ifdef CONFIG_SYS_PLPRCR
if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
mfmask = PLPRCR_MFACT_MSK;
else
mfmask = PLPRCR_MF_MSK;
- if ((CFG_PLPRCR & mfmask) != 0)
- reg = CFG_PLPRCR; /* reset control bits */
+ if ((CONFIG_SYS_PLPRCR & mfmask) != 0)
+ reg = CONFIG_SYS_PLPRCR; /* reset control bits */
else {
reg = immr->im_clkrst.car_plprcr;
reg &= mfmask; /* isolate MF-related fields */
- reg |= CFG_PLPRCR; /* reset control bits */
+ reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
}
immr->im_clkrst.car_plprcr = reg;
#endif
@@ -130,20 +130,20 @@ void cpu_init_f (volatile immap_t * immr)
* when FLASH size has been determined
*
* Depending on the size of the memory region defined by
- * CFG_OR0_REMAP some boards (wide address mask) allow to map the
- * CFG_MONITOR_BASE, while others (narrower address mask) can't
- * map CFG_MONITOR_BASE.
+ * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
+ * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
+ * map CONFIG_SYS_MONITOR_BASE.
*
- * For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is
- * 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000.
+ * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
+ * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
*
* If BR0 wasn't loaded with address base 0xff000000, then BR0's
* base address remains as 0x00000000. However, the address mask
- * have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped
+ * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
* into the Bank0.
*
* This is why CONFIG_IVMS8 and similar boards must load BR0 with
- * CFG_BR0_PRELIM in advance.
+ * CONFIG_SYS_BR0_PRELIM in advance.
*
* [Thanks to Michael Liao for this explanation.
* I owe him a free beer. - wd]
@@ -165,60 +165,60 @@ void cpu_init_f (volatile immap_t * immr)
defined(CONFIG_SPC1920) || \
defined(CONFIG_SPD823TS)
- memctl->memc_br0 = CFG_BR0_PRELIM;
+ memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
#endif
-#if defined(CFG_OR0_REMAP)
- memctl->memc_or0 = CFG_OR0_REMAP;
+#if defined(CONFIG_SYS_OR0_REMAP)
+ memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
#endif
-#if defined(CFG_OR1_REMAP)
- memctl->memc_or1 = CFG_OR1_REMAP;
+#if defined(CONFIG_SYS_OR1_REMAP)
+ memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
#endif
-#if defined(CFG_OR5_REMAP)
- memctl->memc_or5 = CFG_OR5_REMAP;
+#if defined(CONFIG_SYS_OR5_REMAP)
+ memctl->memc_or5 = CONFIG_SYS_OR5_REMAP;
#endif
/* now restrict to preliminary range */
- memctl->memc_br0 = CFG_BR0_PRELIM;
- memctl->memc_or0 = CFG_OR0_PRELIM;
+ memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
+ memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
-#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
- memctl->memc_or1 = CFG_OR1_PRELIM;
- memctl->memc_br1 = CFG_BR1_PRELIM;
+#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
+ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+ memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
#endif
#if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
memctl->memc_br0 = 0;
#endif
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
- memctl->memc_or2 = CFG_OR2_PRELIM;
- memctl->memc_br2 = CFG_BR2_PRELIM;
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+ memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+ memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
#endif
-#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
- memctl->memc_or3 = CFG_OR3_PRELIM;
- memctl->memc_br3 = CFG_BR3_PRELIM;
+#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+ memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
#endif
-#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
- memctl->memc_or4 = CFG_OR4_PRELIM;
- memctl->memc_br4 = CFG_BR4_PRELIM;
+#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
+ memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+ memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
#endif
-#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
- memctl->memc_or5 = CFG_OR5_PRELIM;
- memctl->memc_br5 = CFG_BR5_PRELIM;
+#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
+ memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
+ memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
#endif
-#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
- memctl->memc_or6 = CFG_OR6_PRELIM;
- memctl->memc_br6 = CFG_BR6_PRELIM;
+#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
+ memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
+ memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
#endif
-#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
- memctl->memc_or7 = CFG_OR7_PRELIM;
- memctl->memc_br7 = CFG_BR7_PRELIM;
+#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
+ memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
+ memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
#endif
#endif /* ! CONFIG_MBX */
@@ -249,13 +249,13 @@ void cpu_init_f (volatile immap_t * immr)
rpxlite_init ();
#endif
-#ifdef CFG_RCCR /* must be done before cpm_load_patch() */
+#ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */
/* write config value */
- immr->im_cpm.cp_rccr = CFG_RCCR;
+ immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
#endif
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \
- defined(CFG_SMC_UCODE_PATCH)
+#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
+ defined(CONFIG_SYS_SMC_UCODE_PATCH)
cpm_load_patch (immr); /* load mpc8xx microcode patch */
#endif
}
@@ -265,21 +265,21 @@ void cpu_init_f (volatile immap_t * immr)
*/
int cpu_init_r (void)
{
-#if defined(CFG_RTCSC) || defined(CFG_RMDS)
+#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
bd_t *bd = gd->bd;
volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
#endif
-#ifdef CFG_RTCSC
+#ifdef CONFIG_SYS_RTCSC
/* Unlock RTSC register */
immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
/* write config value */
- immr->im_sit.sit_rtcsc = CFG_RTCSC;
+ immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC;
#endif
-#ifdef CFG_RMDS
+#ifdef CONFIG_SYS_RMDS
/* write config value */
- immr->im_cpm.cp_rmds = CFG_RMDS;
+ immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS;
#endif
return (0);
}
diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index 37eb481..141425d 100644
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
/* define WANT_MII when MII support is required */
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
#define WANT_MII
#else
#undef WANT_MII
@@ -59,7 +59,7 @@ DECLARE_GLOBAL_DATA_PTR;
#error RMII support is unusable without a working PHY.
#endif
-#ifdef CFG_DISCOVER_PHY
+#ifdef CONFIG_SYS_DISCOVER_PHY
static int mii_discover_phy(struct eth_device *dev);
#endif
@@ -197,7 +197,7 @@ static int fec_send(struct eth_device* dev, volatile void *packet, int length)
{
int j, rc;
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
+ volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
/* section 16.9.23.3
* Wait for ready
@@ -248,7 +248,7 @@ static int fec_recv (struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
volatile fec_t *fecp =
- (volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
+ (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
int length;
for (;;) {
@@ -339,7 +339,7 @@ static inline void fec_10Mbps(struct eth_device *dev)
if ((unsigned int)fecidx >= 2)
hang();
- ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |= mask;
+ ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask;
}
static inline void fec_100Mbps(struct eth_device *dev)
@@ -351,7 +351,7 @@ static inline void fec_100Mbps(struct eth_device *dev)
if ((unsigned int)fecidx >= 2)
hang();
- ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~mask;
+ ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
}
#endif
@@ -359,7 +359,7 @@ static inline void fec_100Mbps(struct eth_device *dev)
static inline void fec_full_duplex(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
+ volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
@@ -368,7 +368,7 @@ static inline void fec_full_duplex(struct eth_device *dev)
static inline void fec_half_duplex(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
+ volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
@@ -377,7 +377,7 @@ static inline void fec_half_duplex(struct eth_device *dev)
static void fec_pin_init(int fecidx)
{
bd_t *bd = gd->bd;
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile fec_t *fecp;
/*
@@ -474,7 +474,7 @@ static void fec_pin_init(int fecidx)
* Configure port A for MII.
*/
-#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY)
/*
* On the ICU862 board the MII-MDC pin is routed to PD8 pin
@@ -569,9 +569,9 @@ static int fec_reset(volatile fec_t *fecp)
static int fec_init (struct eth_device *dev, bd_t * bd)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile fec_t *fecp =
- (volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
+ (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
int i;
if (efis->ether_index == 0) {
@@ -657,7 +657,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
txIdx = 0;
if (!rtx) {
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
dpram_alloc_align (sizeof (RTXBD), 8));
#else
@@ -721,7 +721,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
if (efis->phy_addr == -1) {
-#ifdef CFG_DISCOVER_PHY
+#ifdef CONFIG_SYS_DISCOVER_PHY
/*
* wait for the PHY to wake up after reset
*/
@@ -772,7 +772,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
static void fec_halt(struct eth_device* dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
+ volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
int i;
/* avoid halt if initialized; mii gets stuck otherwise */
@@ -801,7 +801,7 @@ static void fec_halt(struct eth_device* dev)
efis->initialized = 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/* Make MII read/write commands for the FEC.
*/
@@ -846,7 +846,7 @@ mii_send(uint mii_cmd)
volatile fec_t *ep;
int cnt;
- ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec);
+ ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec);
ep->fec_mii_data = mii_cmd; /* command to phy */
@@ -868,7 +868,7 @@ mii_send(uint mii_cmd)
}
#endif
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
static int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -937,7 +937,7 @@ static int mii_discover_phy(struct eth_device *dev)
}
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
@@ -948,7 +948,7 @@ static int mii_discover_phy(struct eth_device *dev)
*/
static void __mii_init(void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
if (fec_reset(fecp) < 0)
diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c
index f05b666..29c7c71 100644
--- a/cpu/mpc8xx/i2c.c
+++ b/cpu/mpc8xx/i2c.c
@@ -45,12 +45,12 @@ DECLARE_GLOBAL_DATA_PTR;
/*-----------------------------------------------------------------------
* Set default values
*/
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED 50000
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED 50000
#endif
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE 0xFE
+#ifndef CONFIG_SYS_I2C_SLAVE
+#define CONFIG_SYS_I2C_SLAVE 0xFE
#endif
/*-----------------------------------------------------------------------
*/
@@ -162,7 +162,7 @@ i2c_roundrate(int hz, int speed, int filter, int modval,
static int
i2c_setrate (int hz, int speed)
{
- immap_t *immap = (immap_t *) CFG_IMMR;
+ immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
int brgval,
modval, /* 0-3 */
@@ -207,7 +207,7 @@ i2c_setrate (int hz, int speed)
void
i2c_init(int speed, int slaveaddr)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
@@ -215,21 +215,21 @@ i2c_init(int speed, int slaveaddr)
volatile I2C_BD *rxbd, *txbd;
uint dpaddr;
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
/* call board specific i2c bus reset routine before accessing the */
/* environment, which might be in a chip on that bus. For details */
/* about this problem see doc/I2C_Edge_Conditions. */
i2c_init_board();
#endif
-#ifdef CFG_I2C_UCODE_PATCH
+#ifdef CONFIG_SYS_I2C_UCODE_PATCH
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
#else
/* Disable relocation */
iip->iic_rpbase = 0;
#endif
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = iip->iic_rbase;
if (dpaddr == 0) {
/* need to allocate dual port ram */
@@ -269,7 +269,7 @@ i2c_init(int speed, int slaveaddr)
* divide BRGCLK by 1)
*/
PRINTD(("[I2C] Setting rate...\n"));
- i2c_setrate (gd->cpu_clk, CFG_I2C_SPEED) ;
+ i2c_setrate (gd->cpu_clk, CONFIG_SYS_I2C_SPEED) ;
/* Set I2C controller in master mode */
i2c->i2c_i2com = 0x01;
@@ -295,7 +295,7 @@ i2c_init(int speed, int slaveaddr)
/* Set maximum receive size. */
iip->iic_mrblr = I2C_RXTX_LEN;
-#ifdef CFG_I2C_UCODE_PATCH
+#ifdef CONFIG_SYS_I2C_UCODE_PATCH
/*
* Initialize required parameters if using microcode patch.
*/
@@ -318,13 +318,13 @@ i2c_init(int speed, int slaveaddr)
static void
i2c_newio(i2c_state_t *state)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
PRINTD(("[I2C] i2c_newio\n"));
-#ifdef CFG_I2C_UCODE_PATCH
+#ifdef CONFIG_SYS_I2C_UCODE_PATCH
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
#endif
state->rx_idx = 0;
@@ -492,7 +492,7 @@ i2c_receive(i2c_state_t *state,
static int i2c_doio(i2c_state_t *state)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
@@ -501,7 +501,7 @@ static int i2c_doio(i2c_state_t *state)
PRINTD(("[I2C] i2c_doio\n"));
-#ifdef CFG_I2C_UCODE_PATCH
+#ifdef CONFIG_SYS_I2C_UCODE_PATCH
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
#endif
@@ -593,7 +593,7 @@ int i2c_probe(uchar chip)
int rc;
uchar buf[1];
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
i2c_newio(&state);
@@ -628,7 +628,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones like
* Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
@@ -639,7 +639,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
* be one byte because the extra address bits are hidden in the
* chip address.
*/
- chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
i2c_newio(&state);
@@ -678,7 +678,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
/*
* EEPROM chips that implement "address overflow" are ones like
* Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
@@ -689,7 +689,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
* be one byte because the extra address bits are hidden in the
* chip address.
*/
- chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
i2c_newio(&state);
@@ -722,7 +722,7 @@ i2c_reg_read(uchar i2c_addr, uchar reg)
{
uchar buf;
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
i2c_read(i2c_addr, reg, 1, &buf, 1);
@@ -732,7 +732,7 @@ i2c_reg_read(uchar i2c_addr, uchar reg)
void
i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
{
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
i2c_write(i2c_addr, reg, 1, &val, 1);
}
diff --git a/cpu/mpc8xx/interrupts.c b/cpu/mpc8xx/interrupts.c
index 20e7012..5daa6b2 100644
--- a/cpu/mpc8xx/interrupts.c
+++ b/cpu/mpc8xx/interrupts.c
@@ -47,9 +47,9 @@ static void cpm_interrupt (void *regs);
int interrupt_init_cpu (unsigned *decrementer_count)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- *decrementer_count = get_tbclk () / CFG_HZ;
+ *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
/* disable all interrupts */
immr->im_siu_conf.sc_simask = 0;
@@ -67,7 +67,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
*/
void external_interrupt (struct pt_regs *regs)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
int irq;
ulong simask, newmask;
ulong vec, v_bit;
@@ -124,7 +124,7 @@ void external_interrupt (struct pt_regs *regs)
*/
static void cpm_interrupt (void *regs)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
uint vec;
/*
@@ -165,7 +165,7 @@ static void cpm_error_interrupt (void *dummy)
void irq_install_handler (int vec, interrupt_handler_t * handler,
void *arg)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
if ((vec & CPMVEC_OFFSET) != 0) {
/* CPM interrupt */
@@ -202,7 +202,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler,
void irq_free_handler (int vec)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
if ((vec & CPMVEC_OFFSET) != 0) {
/* CPM interrupt */
@@ -230,7 +230,7 @@ void irq_free_handler (int vec)
static void cpm_interrupt_init (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
/*
* Initialize the CPM interrupt controller.
@@ -266,7 +266,7 @@ static void cpm_interrupt_init (void)
*/
void timer_interrupt_cpu (struct pt_regs *regs)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
#if 0
printf ("*** Timer Interrupt *** ");
diff --git a/cpu/mpc8xx/kgdb.S b/cpu/mpc8xx/kgdb.S
index 812baa3..2cc8fe6 100644
--- a/cpu/mpc8xx/kgdb.S
+++ b/cpu/mpc8xx/kgdb.S
@@ -52,21 +52,21 @@ kgdb_flush_cache_all:
.globl kgdb_flush_cache_range
kgdb_flush_cache_range:
- li r5,CFG_CACHELINE_SIZE-1
+ li r5,CONFIG_SYS_CACHELINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
- srwi. r4,r4,CFG_CACHELINE_SHIFT
+ srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
beqlr
mtctr r4
mr r6,r3
1: dcbst 0,r3
- addi r3,r3,CFG_CACHELINE_SIZE
+ addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
sync /* wait for dcbst's to get to ram */
mtctr r4
2: icbi 0,r6
- addi r6,r6,CFG_CACHELINE_SIZE
+ addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
bdnz 2b
SYNC
blr
diff --git a/cpu/mpc8xx/lcd.c b/cpu/mpc8xx/lcd.c
index 3c64a9b..4474e24 100644
--- a/cpu/mpc8xx/lcd.c
+++ b/cpu/mpc8xx/lcd.c
@@ -63,7 +63,7 @@
#define LCD_BPP LCD_COLOR4
vidinfo_t panel_info = {
- 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
+ 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0
/* wbl, vpw, lcdac, wbf */
};
@@ -76,7 +76,7 @@ vidinfo_t panel_info = {
* Hitachi SP19X001-. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 154, 116, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
+ 640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
/* wbl, vpw, lcdac, wbf */
};
@@ -89,7 +89,7 @@ vidinfo_t panel_info = {
* NEC NL6448AC33-18. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 144, 2, 0, 33
/* wbl, vpw, lcdac, wbf */
};
@@ -101,7 +101,7 @@ vidinfo_t panel_info = {
* NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 144, 2, 0, 33
/* wbl, vpw, lcdac, wbf */
};
@@ -113,7 +113,7 @@ vidinfo_t panel_info = {
* NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 212, 158, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 144, 2, 0, 33
/* wbl, vpw, lcdac, wbf */
};
@@ -125,7 +125,7 @@ vidinfo_t panel_info = {
* SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW,
+ 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
3, 0, 0, 1, 1, 25, 1, 0, 33
/* wbl, vpw, lcdac, wbf */
};
@@ -138,7 +138,7 @@ vidinfo_t panel_info = {
* not sure what it is.......
*/
vidinfo_t panel_info = {
- 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
+ 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 15, 4, 0, 3
};
#endif /* CONFIG_SHARP_16x9 */
@@ -152,7 +152,7 @@ vidinfo_t panel_info = {
#define LCD_DF 12
vidinfo_t panel_info = {
- 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 15, 4, 0, 3
/* wbl, vpw, lcdac, wbf */
};
@@ -165,7 +165,7 @@ vidinfo_t panel_info = {
* Sharp LQ64D341 display, 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 128, 16, 0, 32
/* wbl, vpw, lcdac, wbf */
};
@@ -176,7 +176,7 @@ vidinfo_t panel_info = {
* Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 400, 240, 143, 79, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
+ 400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 248, 4, 0, 35
/* wbl, vpw, lcdac, wbf */
};
@@ -188,7 +188,7 @@ vidinfo_t panel_info = {
* Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 171, 129, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW,
+ 640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
3, 0, 0, 1, 1, 160, 3, 0, 48
/* wbl, vpw, lcdac, wbf */
};
@@ -201,7 +201,7 @@ vidinfo_t panel_info = {
* HLD1045 display, 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 160, 3, 0, 48
/* wbl, vpw, lcdac, wbf */
};
@@ -213,7 +213,7 @@ vidinfo_t panel_info = {
* Prime View V16C6448AC
*/
vidinfo_t panel_info = {
- 640, 480, 130, 98, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
3, 0, 0, 1, 1, 144, 2, 0, 35
/* wbl, vpw, lcdac, wbf */
};
@@ -235,7 +235,7 @@ vidinfo_t panel_info = {
/* 1 - 4 grey levels, 2 bpp */
/* 2 - 16 grey levels, 4 bpp */
vidinfo_t panel_info = {
- 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW,
+ 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
};
#endif /* CONFIG_OPTREX_BW */
@@ -249,7 +249,7 @@ vidinfo_t panel_info = {
#define LCD_DF 10
vidinfo_t panel_info = {
- 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW,
+ 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0
};
#endif
@@ -307,7 +307,7 @@ ulong calc_fbsize (void)
void lcd_ctrl_init (void *lcdbase)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile lcd823_t *lcdp = &immr->im_lcd;
uint lccrtmp;
@@ -320,7 +320,7 @@ void lcd_ctrl_init (void *lcdbase)
#ifdef CONFIG_RPXLITE
/* This is special for RPXlite_DW Software Development Platform **[Sam]** */
- panel_info.vl_dp = CFG_LOW;
+ panel_info.vl_dp = CONFIG_SYS_LOW;
#endif
lccrtmp = LCDBIT (LCCR_BNUM_BIT,
@@ -436,14 +436,14 @@ void lcd_ctrl_init (void *lcdbase)
static void
lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(immr->im_cpm);
unsigned short colreg, *cmap_ptr;
cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
colreg = *cmap_ptr;
-#ifdef CFG_INVERT_COLORS
+#ifdef CONFIG_SYS_INVERT_COLORS
colreg ^= 0x0FFF;
#endif
@@ -459,7 +459,7 @@ lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
void
lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(immr->im_cpm);
unsigned short colreg, *cmap_ptr;
@@ -468,7 +468,7 @@ lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
colreg = ((red & 0x0F) << 8) |
((green & 0x0F) << 4) |
(blue & 0x0F) ;
-#ifdef CFG_INVERT_COLORS
+#ifdef CONFIG_SYS_INVERT_COLORS
colreg ^= 0x0FFF;
#endif
*cmap_ptr = colreg;
@@ -486,7 +486,7 @@ lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
static
void lcd_initcolregs (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(immr->im_cpm);
ushort regno;
@@ -501,7 +501,7 @@ void lcd_initcolregs (void)
void lcd_enable (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile lcd823_t *lcdp = &immr->im_lcd;
/* Enable the LCD panel */
@@ -521,7 +521,7 @@ void lcd_enable (void)
#if defined(CONFIG_LWMON)
{ uchar c = pic_read (0x60);
-#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CFG_POST_SYSMON)
+#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
/* Enable LCD later in sysmon test, only if temperature is OK */
#else
c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */
@@ -586,7 +586,7 @@ void lcd_enable (void)
#if defined (CONFIG_RBC823)
void lcd_disable (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile lcd823_t *lcdp = &immr->im_lcd;
#if defined(CONFIG_LWMON)
diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c
index 09a3db1..effb967 100644
--- a/cpu/mpc8xx/scc.c
+++ b/cpu/mpc8xx/scc.c
@@ -191,7 +191,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
int i;
scc_enet_t *pram_ptr;
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
#if defined(CONFIG_LWMON)
reset_phy();
@@ -215,12 +215,14 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
rxIdx = 0;
txIdx = 0;
-#ifdef CFG_ALLOC_DPRAM
- rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
- dpram_alloc_align (sizeof (RTXBD), 8));
+ if (!rtx) {
+#ifdef CONFIG_SYS_ALLOC_DPRAM
+ rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
+ dpram_alloc_align (sizeof (RTXBD), 8));
#else
- rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
-#endif /* 0 */
+ rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
+#endif
+ }
#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
/* Configure port A pins for Txd and Rxd.
@@ -550,7 +552,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
static void scc_halt (struct eth_device *dev)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &=
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
@@ -561,7 +563,7 @@ static void scc_halt (struct eth_device *dev)
#if 0
void restart (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c
index ad02299..cae90dd 100644
--- a/cpu/mpc8xx/serial.c
+++ b/cpu/mpc8xx/serial.c
@@ -74,8 +74,8 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
divisor=(50*1000*1000 + 8*9600)/16/9600;
}
-#ifdef CFG_BRGCLK_PRESCALE
- divisor /= CFG_BRGCLK_PRESCALE;
+#ifdef CONFIG_SYS_BRGCLK_PRESCALE
+ divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
#endif
if(divisor<=0x1000) {
@@ -94,7 +94,7 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
static void smc_setbrg (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
/* Set up the baud rate generator.
@@ -110,7 +110,7 @@ static void smc_setbrg (void)
static int smc_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile smc_t *sp;
volatile smc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -124,7 +124,7 @@ static int smc_init (void)
sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
-#ifdef CFG_SMC_UCODE_PATCH
+#ifdef CONFIG_SYS_SMC_UCODE_PATCH
up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
#else
/* Disable relocation */
@@ -140,15 +140,15 @@ static int smc_init (void)
im->im_siu_conf.sc_sdcr = 1;
/* clear error conditions */
-#ifdef CFG_SDSR
- im->im_sdma.sdma_sdsr = CFG_SDSR;
+#ifdef CONFIG_SYS_SDSR
+ im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
#else
im->im_sdma.sdma_sdsr = 0x83;
#endif
/* clear SDMA interrupt mask */
-#ifdef CFG_SDMR
- im->im_sdma.sdma_sdmr = CFG_SDMR;
+#ifdef CONFIG_SYS_SDMR
+ im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
#else
im->im_sdma.sdma_sdmr = 0x00;
#endif
@@ -193,7 +193,7 @@ static int smc_init (void)
* the buffer descriptors.
*/
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
#else
dpaddr = CPM_SERIAL_BASE ;
@@ -218,7 +218,7 @@ static int smc_init (void)
up->smc_tbase = dpaddr+sizeof(cbd_t);
up->smc_rfcr = SMC_EB;
up->smc_tfcr = SMC_EB;
-#if defined (CFG_SMC_UCODE_PATCH)
+#if defined (CONFIG_SYS_SMC_UCODE_PATCH)
up->smc_rbptr = up->smc_rbase;
up->smc_tbptr = up->smc_tbase;
up->smc_rstate = 0;
@@ -239,11 +239,11 @@ static int smc_init (void)
sp->smc_smcm = 0;
sp->smc_smce = 0xff;
-#ifdef CFG_SPC1920_SMC1_CLK4
+#ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
/* clock source is PLD */
/* set freq to 19200 Baud */
- *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0x3;
+ *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3;
/* configure clk4 as input */
im->im_ioport.iop_pdpar |= 0x800;
im->im_ioport.iop_pddir &= ~0x800;
@@ -288,7 +288,7 @@ smc_putc(const char c)
volatile cbd_t *tbdf;
volatile char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
#ifdef CONFIG_MODEM_SUPPORT
@@ -300,7 +300,7 @@ smc_putc(const char c)
smc_putc ('\r');
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-#ifdef CFG_SMC_UCODE_PATCH
+#ifdef CONFIG_SYS_SMC_UCODE_PATCH
up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
@@ -336,12 +336,12 @@ smc_getc(void)
volatile cbd_t *rbdf;
volatile unsigned char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
unsigned char c;
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-#ifdef CFG_SMC_UCODE_PATCH
+#ifdef CONFIG_SYS_SMC_UCODE_PATCH
up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
@@ -365,11 +365,11 @@ smc_tstc(void)
{
volatile cbd_t *rbdf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-#ifdef CFG_SMC_UCODE_PATCH
+#ifdef CONFIG_SYS_SMC_UCODE_PATCH
up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
@@ -398,7 +398,7 @@ struct serial_device serial_smc_device =
static void
scc_setbrg (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
/* Set up the baud rate generator.
@@ -414,7 +414,7 @@ scc_setbrg (void)
static int scc_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -474,7 +474,7 @@ static int scc_init (void)
/* Allocate space for two buffer descriptors in the DP ram.
*/
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
#else
dpaddr = CPM_SERIAL2_BASE ;
@@ -580,7 +580,7 @@ scc_putc(const char c)
volatile cbd_t *tbdf;
volatile char *buf;
volatile scc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
#ifdef CONFIG_MODEM_SUPPORT
@@ -625,7 +625,7 @@ scc_getc(void)
volatile cbd_t *rbdf;
volatile unsigned char *buf;
volatile scc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
unsigned char c;
@@ -651,7 +651,7 @@ scc_tstc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index 070babc..f309f29 100644
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG)
+#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CONFIG_SYS_MEASURE_CPUCLK) || defined(DEBUG)
#define PITC_SHIFT 16
#define PITR_SHIFT 16
@@ -87,12 +87,12 @@ static __inline__ void set_msr(unsigned long msr)
unsigned long measure_gclk(void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
ulong timer2_val;
ulong msr_val;
-#ifdef CFG_8XX_XIN
+#ifdef CONFIG_SYS_8XX_XIN
/* dont use OSCM, only use EXTCLK/512 */
immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
#else
@@ -137,7 +137,7 @@ unsigned long measure_gclk(void)
immr->im_sit.sit_pitc = SPEED_PITC_INIT;
immr->im_sitk.sitk_piscrk = KAPWR_KEY;
- immr->im_sit.sit_piscr = CFG_PISCR;
+ immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
/*
* Start measurement - disable interrupts, just in case
@@ -164,9 +164,9 @@ unsigned long measure_gclk(void)
timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
immr->im_sit.sit_piscr &= ~PISCR_PTE;
-#if defined(CFG_8XX_XIN)
+#if defined(CONFIG_SYS_8XX_XIN)
/* not using OSCM, using XIN, so scale appropriately */
- return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
+ return (((timer2_val + 2) / 4) * (CONFIG_SYS_8XX_XIN/512))/8192 * 100000L;
#else
return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
#endif
@@ -261,7 +261,7 @@ static long init_pll_866 (long clk);
*/
int get_clocks_866 (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
char tmp[64];
long cpuclk = 0;
long sccr_reg;
@@ -269,11 +269,11 @@ int get_clocks_866 (void)
if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
- if ((CFG_8xx_CPUCLK_MIN > cpuclk) || (CFG_8xx_CPUCLK_MAX < cpuclk))
+ if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk))
cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
gd->cpu_clk = init_pll_866 (cpuclk);
-#if defined(CFG_MEASURE_CPUCLK)
+#if defined(CONFIG_SYS_MEASURE_CPUCLK)
gd->cpu_clk = measure_gclk ();
#endif
@@ -301,12 +301,12 @@ int get_clocks_866 (void)
*/
int sdram_adjust_866 (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
long mamr;
mamr = immr->im_memctl.memc_mamr;
mamr &= ~MAMR_PTA_MSK;
- mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+ mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
immr->im_memctl.memc_mamr = mamr;
return (0);
@@ -320,7 +320,7 @@ static long init_pll_866 (long clk)
{
extern void plprcr_write_866 (long);
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
long n, plprcr;
char mfi, mfn, mfd, s, pdf;
long step_mfi, step_mfn;
@@ -394,13 +394,13 @@ static long init_pll_866 (long clk)
*/
int adjust_sdram_tbs_8xx (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
long mamr;
long sccr;
mamr = immr->im_memctl.memc_mamr;
mamr &= ~MAMR_PTA_MSK;
- mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+ mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
immr->im_memctl.memc_mamr = mamr;
if (gd->cpu_clk < 67000000) {
diff --git a/cpu/mpc8xx/spi.c b/cpu/mpc8xx/spi.c
index e318ed0..b2ac23e 100644
--- a/cpu/mpc8xx/spi.c
+++ b/cpu/mpc8xx/spi.c
@@ -41,7 +41,7 @@
#include <post.h>
#include <serial.h>
-#if (defined(CONFIG_SPI)) || (CONFIG_POST & CFG_POST_SPI)
+#if (defined(CONFIG_SPI)) || (CONFIG_POST & CONFIG_SYS_POST_SPI)
/* Warning:
* You cannot enable DEBUG for early system initalization, i. e. when
@@ -64,8 +64,8 @@
* The value 0xb00 makes it far enough from the start of the data
* area (as well as from the stack pointer).
* --------------------------------------------------------------- */
-#ifndef CFG_SPI_INIT_OFFSET
-#define CFG_SPI_INIT_OFFSET 0xB00
+#ifndef CONFIG_SYS_SPI_INIT_OFFSET
+#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
#endif
#ifdef DEBUG
@@ -118,11 +118,11 @@ ssize_t spi_xfer (size_t);
* Initially we place the RX and TX buffers at a fixed location in DPRAM!
* ---------------------------------------------------------------------- */
static uchar *rxbuf =
- (uchar *)&((cpm8xx_t *)&((immap_t *)CFG_IMMR)->im_cpm)->cp_dpmem
- [CFG_SPI_INIT_OFFSET];
+ (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
+ [CONFIG_SYS_SPI_INIT_OFFSET];
static uchar *txbuf =
- (uchar *)&((cpm8xx_t *)&((immap_t *)CFG_IMMR)->im_cpm)->cp_dpmem
- [CFG_SPI_INIT_OFFSET+MAX_BUFFER];
+ (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
+ [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
/* **************************************************************************
*
@@ -144,12 +144,12 @@ void spi_init_f (void)
volatile iop8xx_t *iop;
volatile cbd_t *tbdf, *rbdf;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
cpi = (cpic8xx_t *)&immr->im_cpic;
iop = (iop8xx_t *) &immr->im_ioport;
cp = (cpm8xx_t *) &immr->im_cpm;
-#ifdef CFG_SPI_UCODE_PATCH
+#ifdef CONFIG_SYS_SPI_UCODE_PATCH
spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
#else
spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
@@ -210,7 +210,7 @@ void spi_init_f (void)
/* Allocate space for one transmit and one receive buffer
* descriptor in the DP ram
*/
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2, 8);
#else
dpaddr = CPM_SPI_BASE;
@@ -234,7 +234,7 @@ void spi_init_f (void)
spi->spi_tbptr = spi->spi_tbase;
/* 4 */
-#ifdef CFG_SPI_UCODE_PATCH
+#ifdef CONFIG_SYS_SPI_UCODE_PATCH
/*
* Initialize required parameters if using microcode patch.
*/
@@ -247,7 +247,7 @@ void spi_init_f (void)
cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG;
while (cp->cp_cpcr & CPM_CR_FLG)
;
-#endif /* CFG_SPI_UCODE_PATCH */
+#endif /* CONFIG_SYS_SPI_UCODE_PATCH */
/* 5 */
/* Set SDMA configuration register */
@@ -299,10 +299,10 @@ void spi_init_r (void)
volatile immap_t *immr;
volatile cbd_t *tbdf, *rbdf;
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
cp = (cpm8xx_t *) &immr->im_cpm;
-#ifdef CFG_SPI_UCODE_PATCH
+#ifdef CONFIG_SYS_SPI_UCODE_PATCH
spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
#else
spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
@@ -392,10 +392,10 @@ ssize_t spi_xfer (size_t count)
DPRINT (("*** spi_xfer entered ***\n"));
- immr = (immap_t *) CFG_IMMR;
+ immr = (immap_t *) CONFIG_SYS_IMMR;
cp = (cpm8xx_t *) &immr->im_cpm;
-#ifdef CFG_SPI_UCODE_PATCH
+#ifdef CONFIG_SYS_SPI_UCODE_PATCH
spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
#else
spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
@@ -468,7 +468,7 @@ ssize_t spi_xfer (size_t count)
return count;
}
-#endif /* CONFIG_SPI || (CONFIG_POST & CFG_POST_SPI) */
+#endif /* CONFIG_SPI || (CONFIG_POST & CONFIG_SYS_POST_SPI) */
/*
* SPI test
@@ -481,7 +481,7 @@ ssize_t spi_xfer (size_t count)
* TEST_NUM - number of tests
*/
-#if CONFIG_POST & CFG_POST_SPI
+#if CONFIG_POST & CONFIG_SYS_POST_SPI
#define TEST_MIN_LENGTH 1
#define TEST_MAX_LENGTH MAX_BUFFER
@@ -513,7 +513,7 @@ static int packet_check (char * packet, int length)
int spi_post_test (int flags)
{
int res = -1;
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = (cpm8xx_t *) & immr->im_cpm;
int i;
int l;
@@ -557,4 +557,4 @@ int spi_post_test (int flags)
return res;
}
-#endif /* CONFIG_POST & CFG_POST_SPI */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_SPI */
diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S
index eca4b50..7b75660 100644
--- a/cpu/mpc8xx/start.S
+++ b/cpu/mpc8xx/start.S
@@ -93,7 +93,7 @@ version_string:
. = EXC_OFF_SYS_RESET
.globl _start
_start:
- lis r3, CFG_IMMR@h /* position IMMR */
+ lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
mtspr 638, r3
li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
b boot_cold
@@ -159,8 +159,8 @@ boot_warm:
* Calculate absolute address in FLASH and jump there
*----------------------------------------------------------------------*/
- lis r3, CFG_MONITOR_BASE@h
- ori r3, r3, CFG_MONITOR_BASE@l
+ lis r3, CONFIG_SYS_MONITOR_BASE@h
+ ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
@@ -170,8 +170,8 @@ in_flash:
/* initialize some SPRs that are hard to access from C */
/*----------------------------------------------------------------------*/
- lis r3, CFG_IMMR@h /* pass IMMR as arg1 to C routine */
- ori r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
+ lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */
+ ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
/* Note: R0 is still 0 here */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
@@ -187,8 +187,8 @@ in_flash:
/* Set up debug mode entry */
- lis r2, CFG_DER@h
- ori r2, r2, CFG_DER@l
+ lis r2, CONFIG_SYS_DER@h
+ ori r2, r2, CONFIG_SYS_DER@l
mtspr DER, r2
/* let the C-code set up the rest */
@@ -495,16 +495,16 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
diff --git a/cpu/mpc8xx/upatch.c b/cpu/mpc8xx/upatch.c
index 4d6c522..a8cb735 100644
--- a/cpu/mpc8xx/upatch.c
+++ b/cpu/mpc8xx/upatch.c
@@ -1,8 +1,8 @@
#include <common.h>
#include <commproc.h>
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \
- defined(CFG_SMC_UCODE_PATCH)
+#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
+ defined(CONFIG_SYS_SMC_UCODE_PATCH)
static void UcodeCopy (volatile cpm8xx_t *cpm);
@@ -11,36 +11,36 @@ void cpm_load_patch (volatile immap_t *immr)
immr->im_cpm.cp_rccr &= ~0x0003; /* Disable microcode program area */
UcodeCopy ((cpm8xx_t *)&immr->im_cpm); /* Copy ucode patch to DPRAM */
-#ifdef CFG_SPI_UCODE_PATCH
+#ifdef CONFIG_SYS_SPI_UCODE_PATCH
{
volatile spi_t *spi = (spi_t *) & immr->im_cpm.cp_dparam[PROFF_SPI];
/* Activate the microcode per the instructions in the microcode manual */
/* NOTE: We're only relocating the SPI parameters (not I2C). */
immr->im_cpm.cp_cpmcr1 = 0x802a; /* Write Trap register 1 value */
immr->im_cpm.cp_cpmcr2 = 0x8028; /* Write Trap register 2 value */
- spi->spi_rpbase = CFG_SPI_DPMEM_OFFSET; /* Where to relocte SPI params */
+ spi->spi_rpbase = CONFIG_SYS_SPI_DPMEM_OFFSET; /* Where to relocte SPI params */
}
#endif
-#ifdef CFG_I2C_UCODE_PATCH
+#ifdef CONFIG_SYS_I2C_UCODE_PATCH
{
volatile iic_t *iip = (iic_t *) & immr->im_cpm.cp_dparam[PROFF_IIC];
/* Activate the microcode per the instructions in the microcode manual */
/* NOTE: We're only relocating the I2C parameters (not SPI). */
immr->im_cpm.cp_cpmcr3 = 0x802e; /* Write Trap register 3 value */
immr->im_cpm.cp_cpmcr4 = 0x802c; /* Write Trap register 4 value */
- iip->iic_rpbase = CFG_I2C_DPMEM_OFFSET; /* Where to relocte I2C params */
+ iip->iic_rpbase = CONFIG_SYS_I2C_DPMEM_OFFSET; /* Where to relocte I2C params */
}
#endif
-#ifdef CFG_SMC_UCODE_PATCH
+#ifdef CONFIG_SYS_SMC_UCODE_PATCH
{
volatile smc_uart_t *up = (smc_uart_t *) & immr->im_cpm.cp_dparam[PROFF_SMC1];
/* Activate the microcode per the instructions in the microcode manual */
/* NOTE: We're only relocating the SMC parameters. */
immr->im_cpm.cp_cpmcr1 = 0x8080; /* Write Trap register 1 value */
immr->im_cpm.cp_cpmcr2 = 0x8088; /* Write Trap register 2 value */
- up->smc_rpbase = CFG_SMC_DPMEM_OFFSET; /* Where to relocte SMC params */
+ up->smc_rpbase = CONFIG_SYS_SMC_DPMEM_OFFSET; /* Where to relocte SMC params */
}
#endif
@@ -48,14 +48,14 @@ void cpm_load_patch (volatile immap_t *immr)
* Enable DPRAM microcode to execute from the first 512 bytes
* and a 256 byte extension of DPRAM.
*/
-#ifdef CFG_SMC_UCODE_PATCH
+#ifdef CONFIG_SYS_SMC_UCODE_PATCH
immr->im_cpm.cp_rccr |= 0x0002;
#else
immr->im_cpm.cp_rccr |= 0x0001;
#endif
}
-#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCh)
+#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCh)
static ulong patch_2000[] = {
0x7FFFEFD9, 0x3FFD0000, 0x7FFB49F7, 0x7FF90000,
0x5FEFADF7, 0x5F88ADF7, 0x5FEFAFF7, 0x5F88AFF7,
@@ -191,4 +191,4 @@ static void UcodeCopy (volatile cpm8xx_t *cpm)
}
}
-#endif /* CFG_I2C_UCODE_PATCH, CFG_SPI_UCODE_PATCH */
+#endif /* CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_SPI_UCODE_PATCH */
diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c
index ef91165..2e6a22a 100644
--- a/cpu/mpc8xx/video.c
+++ b/cpu/mpc8xx/video.c
@@ -517,7 +517,7 @@ static void inline video_mode_addentry (VRAM * vr,
static int video_mode_generate (void)
{
- immap_t *immap = (immap_t *) CFG_IMMR;
+ immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
VRAM *vr = (VRAM *) (((void *) immap) + 0xb00); /* Pointer to the VRAM table */
int DX, X1, X2, DY, Y1, Y2, entry = 0, fifo;
@@ -808,7 +808,7 @@ static void video_encoder_init (void)
/* Initialize the I2C */
debug ("[VIDEO ENCODER] Initializing I2C bus...\n");
- i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#ifdef CONFIG_FADS
/* Reset ADV7176 chip */
@@ -856,7 +856,7 @@ static void video_encoder_init (void)
static void video_ctrl_init (void *memptr)
{
- immap_t *immap = (immap_t *) CFG_IMMR;
+ immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
video_fb_address = memptr;
@@ -1235,13 +1235,13 @@ static int video_init (void *videobase)
video_setpalette (CONSOLE_COLOR_GREY2, 0xF8, 0xF8, 0xF8);
video_setpalette (CONSOLE_COLOR_WHITE, 0xFF, 0xFF, 0xFF);
-#ifndef CFG_WHITE_ON_BLACK
+#ifndef CONFIG_SYS_WHITE_ON_BLACK
video_setfgcolor (CONSOLE_COLOR_BLACK);
video_setbgcolor (CONSOLE_COLOR_GREY2);
#else
video_setfgcolor (CONSOLE_COLOR_GREY2);
video_setbgcolor (CONSOLE_COLOR_BLACK);
-#endif /* CFG_WHITE_ON_BLACK */
+#endif /* CONFIG_SYS_WHITE_ON_BLACK */
#ifdef CONFIG_VIDEO_LOGO
/* Paint the logo and retrieve tv base address */
generated by cgit v1.1 at 2024-12-12 12:03:23 +0000