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-rw-r--r--cpu/mpc86xx/cpu.c21
-rw-r--r--cpu/mpc86xx/fdt.c7
-rw-r--r--cpu/mpc86xx/release.S2
-rw-r--r--cpu/mpc86xx/speed.c19
-rw-r--r--cpu/mpc86xx/start.S2
5 files changed, 31 insertions, 20 deletions
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 4cace98..dc53bee 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -39,8 +39,6 @@ checkcpu(void)
uint pvr, svr;
uint ver;
uint major, minor;
- uint lcrr; /* local bus clock ratio register */
- uint clkdiv; /* clock divider portion of lcrr */
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
@@ -100,22 +98,11 @@ checkcpu(void)
printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
-#if defined(CONFIG_SYS_LBC_LCRR)
- lcrr = CONFIG_SYS_LBC_LCRR;
-#else
- {
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
- lcrr = lbc->lcrr;
- }
-#endif
- clkdiv = lcrr & 0x0f;
- if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
- printf("LBC:%4lu MHz\n",
- sysinfo.freqSystemBus / 1000000 / clkdiv);
+ if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
+ printf("LBC:%4lu MHz\n", sysinfo.freqLocalBus / 1000000);
} else {
- printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
+ printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
+ sysinfo.freqLocalBus);
}
puts(" L2: ");
diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c
index 3adfad9..383b06b 100644
--- a/cpu/mpc86xx/fdt.c
+++ b/cpu/mpc86xx/fdt.c
@@ -29,6 +29,13 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
+#if defined(CONFIG_MPC8641)
+ do_fixup_by_compat_u32(blob, "fsl,mpc8641-localbus",
+ "bus-frequency", gd->lbc_clk, 1);
+#endif
+ do_fixup_by_compat_u32(blob, "fsl,elbc",
+ "bus-frequency", gd->lbc_clk, 1);
+
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) \
diff --git a/cpu/mpc86xx/release.S b/cpu/mpc86xx/release.S
index b524e50..95efbb4 100644
--- a/cpu/mpc86xx/release.S
+++ b/cpu/mpc86xx/release.S
@@ -125,7 +125,7 @@ invl2:
mtspr HID0, r5 /* enable + invalidate */
mtspr HID0, r3 /* enable */
sync
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
sync
lis r3, L2_ENABLE@h
ori r3, r3, L2_ENABLE@l
diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c
index 415ac9d..64a3479 100644
--- a/cpu/mpc86xx/speed.c
+++ b/cpu/mpc86xx/speed.c
@@ -28,6 +28,7 @@
#include <common.h>
#include <mpc86xx.h>
#include <asm/processor.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,6 +40,7 @@ void get_sys_info(sys_info_t *sysInfo)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint plat_ratio, e600_ratio;
+ uint lcrr_div;
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
@@ -90,6 +92,22 @@ void get_sys_info(sys_info_t *sysInfo)
sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
break;
}
+
+#if defined(CONFIG_SYS_LBC_LCRR)
+ /* We will program LCRR to this value later */
+ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
+#else
+ {
+ volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
+ }
+#endif
+ if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
+ sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);
+ } else {
+ /* In case anyone cares what the unknown value is */
+ sysInfo->freqLocalBus = lcrr_div;
+ }
}
@@ -105,6 +123,7 @@ int get_clocks(void)
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
+ gd->lbc_clk = sys_info.freqLocalBus;
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 6645cb8..63cc8db 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -982,5 +982,3 @@ unlock_ram_in_cache:
blr
#endif
#endif
-
-