diff options
Diffstat (limited to 'cpu/mpc85xx')
| -rw-r--r-- | cpu/mpc85xx/Makefile | 1 | ||||
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 2 | ||||
| -rw-r--r-- | cpu/mpc85xx/cpu_init.c | 13 | ||||
| -rw-r--r-- | cpu/mpc85xx/ddr-gen3.c | 6 | ||||
| -rw-r--r-- | cpu/mpc85xx/fdt.c | 73 | ||||
| -rw-r--r-- | cpu/mpc85xx/mp.c | 26 | ||||
| -rw-r--r-- | cpu/mpc85xx/mp.h | 4 | ||||
| -rw-r--r-- | cpu/mpc85xx/release.S | 16 | ||||
| -rw-r--r-- | cpu/mpc85xx/start.S | 51 |
9 files changed, 166 insertions, 26 deletions
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 99d88a8..8809302 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -49,6 +49,7 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_MPC8569) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 5b72fe5..ef976a4 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -61,6 +61,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8567, 8567_E), CPU_TYPE_ENTRY(8568, 8568), CPU_TYPE_ENTRY(8568, 8568_E), + CPU_TYPE_ENTRY(8569, 8569), + CPU_TYPE_ENTRY(8569, 8569_E), CPU_TYPE_ENTRY(8572, 8572), CPU_TYPE_ENTRY(8572, 8572_E), CPU_TYPE_ENTRY(P2020, P2020), diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 0b7c609..c98dd8d 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -345,6 +345,19 @@ int cpu_init_r(void) asm("msync;isync"); puts("enabled\n"); } +#elif defined(CONFIG_BACKSIDE_L2_CACHE) + u32 l2cfg0 = mfspr(SPRN_L2CFG0); + + /* invalidate the L2 cache */ + mtspr(SPRN_L2CSR0, L2CSR0_L2FI); + while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI) + ; + + /* enable the cache */ + mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); + + if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) + printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); #else puts("disabled\n"); #endif diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index 99c325a..8ac3d5f 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -98,10 +98,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #endif /* - * 200 painful micro-seconds must elapse between + * 500 painful micro-seconds must elapse between * the DDR clock setup and the DDR config enable. + * DDR2 need 200 us, and DDR3 need 500 us from spec, + * we choose the max, that is 500 us for all of case. */ - udelay(200); + udelay(500); asm volatile("sync;isync"); /* Let the controller go */ diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 1fae47c..26a8f48 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -39,13 +39,8 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) { int off; ulong spin_tbl_addr = get_spin_addr(); - u32 bootpg, id = get_my_id(); - - /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ - if ((u64)gd->ram_size > 0xfffff000) - bootpg = 0xfffff000; - else - bootpg = gd->ram_size - 4096; + u32 bootpg = determine_mp_bootpg(); + u32 id = get_my_id(); off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { @@ -80,7 +75,9 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #endif -#ifdef CONFIG_L2_CACHE +#define ft_fixup_l3cache(x, y) + +#if defined(CONFIG_L2_CACHE) /* return size in kilobytes */ static inline u32 l2cache_size(void) { @@ -157,6 +154,66 @@ static inline void ft_fixup_l2cache(void *blob) fdt_setprop_cell(blob, off, "cache-sets", num_sets); fdt_setprop_cell(blob, off, "cache-level", 2); fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf)); + + /* we dont bother w/L3 since no platform of this type has one */ +} +#elif defined(CONFIG_BACKSIDE_L2_CACHE) +static inline void ft_fixup_l2cache(void *blob) +{ + int off, l2_off, l3_off = -1; + u32 *ph; + u32 l2cfg0 = mfspr(SPRN_L2CFG0); + u32 size, line_size, num_ways, num_sets; + + size = (l2cfg0 & 0x3fff) * 64 * 1024; + num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; + line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; + num_sets = size / (line_size * num_ways); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + + while (off != -FDT_ERR_NOTFOUND) { + ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); + + if (ph == NULL) { + debug("no next-level-cache property\n"); + goto next; + } + + l2_off = fdt_node_offset_by_phandle(blob, *ph); + if (l2_off < 0) { + printf("%s: %s\n", __func__, fdt_strerror(off)); + goto next; + } + + fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); + fdt_setprop_cell(blob, l2_off, "cache-size", size); + fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); + fdt_setprop_cell(blob, l2_off, "cache-level", 2); + fdt_setprop(blob, l2_off, "compatible", "cache", 6); + + if (l3_off < 0) { + ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); + + if (ph == NULL) { + debug("no next-level-cache property\n"); + goto next; + } + l3_off = *ph; + } +next: + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + if (l3_off > 0) { + l3_off = fdt_node_offset_by_phandle(blob, l3_off); + if (l3_off < 0) { + printf("%s: %s\n", __func__, fdt_strerror(off)); + return ; + } + ft_fixup_l3cache(blob, l3_off); + } } #else #define ft_fixup_l2cache(x) diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 3338c1a..76f02a4 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -38,6 +38,7 @@ int cpu_reset(int nr) { volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); out_be32(&pic->pir, 1 << nr); + /* the dummy read works around an errata on early 85xx MP PICs */ (void)in_be32(&pic->pir); out_be32(&pic->pir, 0x0); @@ -112,6 +113,15 @@ int cpu_release(int nr, int argc, char *argv[]) return 0; } +u32 determine_mp_bootpg(void) +{ + /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ + if ((u64)gd->ram_size > 0xfffff000) + return (0xfffff000); + + return (gd->ram_size - 4096); +} + ulong get_spin_addr(void) { extern ulong __secondary_start_page; @@ -188,13 +198,7 @@ static void pq3_mp_up(unsigned long bootpg) void cpu_mp_lmb_reserve(struct lmb *lmb) { - u32 bootpg; - - /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ - if ((u64)gd->ram_size > 0xfffff000) - bootpg = 0xfffff000; - else - bootpg = gd->ram_size - 4096; + u32 bootpg = determine_mp_bootpg(); lmb_reserve(lmb, bootpg, 4096); } @@ -203,13 +207,7 @@ void setup_mp(void) { extern ulong __secondary_start_page; ulong fixup = (ulong)&__secondary_start_page; - u32 bootpg; - - /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ - if ((u64)gd->ram_size > 0xfffff000) - bootpg = 0xfffff000; - else - bootpg = gd->ram_size - 4096; + u32 bootpg = determine_mp_bootpg(); memcpy((void *)bootpg, (void *)fixup, 4096); flush_cache(bootpg, 4096); diff --git a/cpu/mpc85xx/mp.h b/cpu/mpc85xx/mp.h index 4329286..2c2929e 100644 --- a/cpu/mpc85xx/mp.h +++ b/cpu/mpc85xx/mp.h @@ -1,10 +1,10 @@ #ifndef __MPC85XX_MP_H_ #define __MPC85XX_MP_H_ +#include <asm/mp.h> + ulong get_spin_addr(void); -void setup_mp(void); u32 get_my_id(void); -void cpu_mp_lmb_reserve(struct lmb *lmb); #define BOOT_ENTRY_ADDR_UPPER 0 #define BOOT_ENTRY_ADDR_LOWER 1 diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 54c936c..fbefc2c 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -76,6 +76,22 @@ __secondary_start_page: slwi r8,r4,5 add r10,r3,r8 +#ifdef CONFIG_BACKSIDE_L2_CACHE + /* Enable/invalidate the L2 cache */ + msync + lis r3,L2CSR0_L2FI@h + mtspr SPRN_L2CSR0,r3 +1: + mfspr r3,SPRN_L2CSR0 + andis. r1,r3,L2CSR0_L2FI@h + bne 1b + + lis r3,CONFIG_SYS_INIT_L2CSR0@h + ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l + mtspr SPRN_L2CSR0,r3 + isync +#endif + #define EPAPR_MAGIC (0x45504150) #define ENTRY_ADDR_UPPER 0 #define ENTRY_ADDR_LOWER 4 diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 80f9677..4f7236f 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -161,7 +161,9 @@ _start_e500: #if defined(CONFIG_ENABLE_36BIT_PHYS) ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ #endif +#ifndef CONFIG_E500MC ori r0,r0,HID0_TBEN@l /* Enable Timebase */ +#endif mtspr HID0,r0 #ifndef CONFIG_E500MC @@ -184,6 +186,55 @@ _start_e500: mtspr DBCR0,r0 #endif +#ifdef CONFIG_MPC8569 +#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) +#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) + + /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to + * use address space which is more than 12bits, and it must be done in + * the 4K boot page. So we set this bit here. + */ + + /* create a temp mapping TLB0[0] for LBCR */ + lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l + + lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l + + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@l + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + isync + msync + tlbwe + + /* Set LBCR register */ + lis r4,CONFIG_SYS_LBCR_ADDR@h + ori r4,r4,CONFIG_SYS_LBCR_ADDR@l + + lis r5,CONFIG_SYS_LBC_LBCR@h + ori r5,r5,CONFIG_SYS_LBC_LBCR@l + stw r5,0(r4) + isync + + /* invalidate this temp TLB */ + lis r4,CONFIG_SYS_LBC_ADDR@h + ori r4,r4,CONFIG_SYS_LBC_ADDR@l + tlbivax 0,r4 + isync + +#endif /* CONFIG_MPC8569 */ + /* create a temp mapping in AS=1 to the 4M boot window */ lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l |