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-rw-r--r--cpu/mpc85xx/config.mk2
-rw-r--r--cpu/mpc85xx/fdt.c18
-rw-r--r--cpu/mpc85xx/mp.c32
-rw-r--r--cpu/mpc85xx/speed.c23
-rw-r--r--cpu/mpc85xx/start.S44
5 files changed, 73 insertions, 46 deletions
diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk
index 84651b8..408184a 100644
--- a/cpu/mpc85xx/config.mk
+++ b/cpu/mpc85xx/config.mk
@@ -21,7 +21,7 @@
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+PLATFORM_RELFLAGS += -fPIC -meabi
PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index af0e78e..1d11ab4 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -331,6 +331,23 @@ static void ft_fixup_dpaa_clks(void *blob)
#define ft_fixup_dpaa_clks(x)
#endif
+#ifdef CONFIG_QE
+static void ft_fixup_qe_snum(void *blob)
+{
+ unsigned int svr;
+
+ svr = mfspr(SPRN_SVR);
+ if (SVR_SOC_VER(svr) == SVR_8569_E) {
+ if(IS_SVR_REV(svr, 1, 0))
+ do_fixup_by_compat_u32(blob, "fsl,qe",
+ "fsl,qe-num-snums", 46, 1);
+ else
+ do_fixup_by_compat_u32(blob, "fsl,qe",
+ "fsl,qe-num-snums", 76, 1);
+ }
+}
+#endif
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
int off;
@@ -367,6 +384,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"bus-frequency", gd->lbc_clk, 1);
#ifdef CONFIG_QE
ft_qe_setup(blob);
+ ft_fixup_qe_snum(blob);
#endif
#ifdef CONFIG_SYS_NS16550
diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index 6530cb1..826bf32 100644
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -68,6 +68,36 @@ int cpu_status(int nr)
return 0;
}
+#ifdef CONFIG_FSL_CORENET
+int cpu_disable(int nr)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->coredisrl, 1 << nr);
+
+ return 0;
+}
+#else
+int cpu_disable(int nr)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ switch (nr) {
+ case 0:
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
+ break;
+ case 1:
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
+ break;
+ default:
+ printf("Invalid cpu number for disable %d\n", nr);
+ return 1;
+ }
+
+ return 0;
+}
+#endif
+
static u8 boot_entry_map[4] = {
0,
BOOT_ENTRY_PIR,
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 2103e2e..268edbc 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -80,8 +80,8 @@ void get_sys_info (sys_info_t * sysInfo)
freqCC_PLL[2] = sysclk;
freqCC_PLL[3] = sysclk;
- sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf;
- sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf);
+ sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f);
freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
@@ -103,21 +103,21 @@ void get_sys_info (sys_info_t * sysInfo)
#ifdef CONFIG_SYS_DPAA_PME
if (rcw_tmp & PME_CLK_SEL)
- sysInfo->freqPME = sysInfo->freqSystemBus / 2;
- else
sysInfo->freqPME = freqCC_PLL[2] / 2;
+ else
+ sysInfo->freqPME = sysInfo->freqSystemBus / 2;
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
if (rcw_tmp & FM1_CLK_SEL)
- sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
- else
sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
+ else
+ sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
#if (CONFIG_SYS_NUM_FMAN) == 2
if (rcw_tmp & FM2_CLK_SEL)
- sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
- else
sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
+ else
+ sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
#endif
#endif
@@ -170,7 +170,12 @@ void get_sys_info (sys_info_t * sysInfo)
}
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
+#if defined(CONFIG_FSL_CORENET)
+ /* If this is corenet based SoC, bit-representation
+ * for four times the clock divider values.
+ */
+ lcrr_div *= 4;
+#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
/*
* Yes, the entire PQ38 family use the same
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 7e60e67..386fa81 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -51,7 +51,7 @@
/*
* Set up GOT: Global Offset Table
*
- * Use r14 to access the GOT
+ * Use r12 to access the GOT
*/
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
@@ -415,28 +415,15 @@ Alignment:
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
- li r20,MSR_KERNEL
- rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
- lwz r6,GOT(transfer_to_handler)
- mtlr r6
- blrl
-.L_Alignment:
- .long AlignmentException - _start + _START_OFFSET
- .long int_return - _start + _START_OFFSET
+ EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
/* Program check exception */
. = 0x0700
ProgramCheck:
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
- li r20,MSR_KERNEL
- rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
- lwz r6,GOT(transfer_to_handler)
- mtlr r6
- blrl
-.L_ProgramCheck:
- .long ProgramCheckException - _start + _START_OFFSET
- .long int_return - _start + _START_OFFSET
+ EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
+ MSR_KERNEL, COPY_EE)
/* No FPU on MPC85xx. This exception is not supposed to happen.
*/
@@ -884,6 +871,7 @@ relocate_code:
mr r9,r4 /* Save copy of Init Data pointer */
mr r10,r5 /* Save copy of Destination Address */
+ GET_GOT
mr r3,r5 /* Destination Address */
lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
@@ -901,7 +889,7 @@ relocate_code:
sub r15,r10,r4
/* First our own GOT */
- add r14,r14,r15
+ add r12,r12,r15
/* the the one used by the C code */
add r30,r30,r15
@@ -971,7 +959,7 @@ relocate_code:
in_ram:
/*
- * Relocation Function, r14 point to got2+0x8000
+ * Relocation Function, r12 point to got2+0x8000
*
* Adjust got2 pointers, no need to check for 0, this code
* already puts a few entries in the table.
@@ -1037,6 +1025,8 @@ clear_bss:
*/
.globl trap_init
trap_init:
+ mflr r4 /* save link register */
+ GET_GOT
lwz r7,GOT(_start_of_vectors)
lwz r8,GOT(_end_of_vectors)
@@ -1044,8 +1034,6 @@ trap_init:
cmplw 0,r7,r8
bgelr /* return if r7>=r8 - just in case */
-
- mflr r4 /* save link register */
1:
lwz r0,0(r7)
stw r0,0(r9)
@@ -1089,20 +1077,6 @@ trap_init:
mtlr r4 /* restore link register */
blr
- /*
- * Function: relocate entries for one exception vector
- */
-trap_reloc:
- lwz r0,0(r7) /* hdlr ... */
- add r0,r0,r3 /* ... += dest_addr */
- stw r0,0(r7)
-
- lwz r0,4(r7) /* int_return ... */
- add r0,r0,r3 /* ... += dest_addr */
- stw r0,4(r7)
-
- blr
-
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
generated by cgit v1.1 at 2024-12-19 07:40:31 +0000