3 files changed, 4 insertions, 80 deletions

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index d88c564..28c6119 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -264,53 +264,6 @@ reset_85xx_watchdog(void)
 }
 #endif	/* CONFIG_WATCHDOG */
 
-#if defined(CONFIG_DDR_ECC)
-void dma_init(void) {
-	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
-	volatile fsl_dma_t *dma = &dma_base->dma[0];
-
-	dma->satr = 0x00040000;
-	dma->datr = 0x00040000;
-	dma->sr = 0xffffffff; /* clear any errors */
-	asm("sync; isync; msync");
-	return;
-}
-
-uint dma_check(void) {
-	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
-	volatile fsl_dma_t *dma = &dma_base->dma[0];
-	volatile uint status = dma->sr;
-
-	/* While the channel is busy, spin */
-	while((status & 4) == 4) {
-		status = dma->sr;
-	}
-
-	/* clear MR[CS] channel start bit */
-	dma->mr &= 0x00000001;
-	asm("sync;isync;msync");
-
-	if (status != 0) {
-		printf ("DMA Error: status = %x\n", status);
-	}
-	return status;
-}
-
-int dma_xfer(void *dest, uint count, void *src) {
-	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
-	volatile fsl_dma_t *dma = &dma_base->dma[0];
-
-	dma->dar = (uint) dest;
-	dma->sar = (uint) src;
-	dma->bcr = count;
-	dma->mr = 0xf000004;
-	asm("sync;isync;msync");
-	dma->mr = 0xf000005;
-	asm("sync;isync;msync");
-	return dma_check();
-}
-#endif
-
 /*
  * Configures a UPM. The function requires the respective MxMR to be set
  * before calling this function. "size" is the number or entries, not a sizeof.
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index c98dd8d..41de694 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -261,7 +261,9 @@ void cpu_init_f (void)
 #if defined(CONFIG_MPC8536)
 	fsl_serdes_init();
 #endif
-
+#if defined(CONFIG_FSL_DMA)
+	dma_init();
+#endif
 }
 
 
diff --git a/cpu/mpc85xx/ddr-gen1.c b/cpu/mpc85xx/ddr-gen1.c
index e24c9af..54437dd 100644
--- a/cpu/mpc85xx/ddr-gen1.c
+++ b/cpu/mpc85xx/ddr-gen1.c
@@ -66,10 +66,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 }
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void dma_init(void);
-extern uint dma_check(void);
-extern int dma_xfer(void *dest, uint count, void *src);
-
 /*
  * Initialize all of memory for ECC, then enable errors.
  */
@@ -77,36 +73,9 @@ extern int dma_xfer(void *dest, uint count, void *src);
 void
 ddr_enable_ecc(unsigned int dram_size)
 {
-	uint *p = 0;
-	uint i = 0;
 	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
-	dma_init();
-
-	for (*p = 0; p < (uint *)(8 * 1024); p++) {
-		if (((unsigned int)p & 0x1f) == 0) {
-			ppcDcbz((unsigned long) p);
-		}
-		*p = (unsigned int)CONFIG_MEM_INIT_VALUE;
-		if (((unsigned int)p & 0x1c) == 0x1c) {
-			ppcDcbf((unsigned long) p);
-		}
-	}
-
-	dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
-	dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
-	dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
-	dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
-	dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
-	dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
-	dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
-	dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
-	dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
-	dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
-
-	for (i = 1; i < dram_size / 0x800000; i++) {
-		dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
-	}
+	dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
 
 	/*
 	 * Enable errors for ECC.