diff options
Diffstat (limited to 'cpu/mpc85xx')
| -rw-r--r-- | cpu/mpc85xx/Makefile | 1 | ||||
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 2 | ||||
| -rw-r--r-- | cpu/mpc85xx/start.S | 49 |
3 files changed, 52 insertions, 0 deletions
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 99d88a8..8809302 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -49,6 +49,7 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_MPC8569) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 5b72fe5..ef976a4 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -61,6 +61,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8567, 8567_E), CPU_TYPE_ENTRY(8568, 8568), CPU_TYPE_ENTRY(8568, 8568_E), + CPU_TYPE_ENTRY(8569, 8569), + CPU_TYPE_ENTRY(8569, 8569_E), CPU_TYPE_ENTRY(8572, 8572), CPU_TYPE_ENTRY(8572, 8572_E), CPU_TYPE_ENTRY(P2020, P2020), diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 89eea8c..4f7236f 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -186,6 +186,55 @@ _start_e500: mtspr DBCR0,r0 #endif +#ifdef CONFIG_MPC8569 +#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) +#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) + + /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to + * use address space which is more than 12bits, and it must be done in + * the 4K boot page. So we set this bit here. + */ + + /* create a temp mapping TLB0[0] for LBCR */ + lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l + + lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l + + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@l + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + isync + msync + tlbwe + + /* Set LBCR register */ + lis r4,CONFIG_SYS_LBCR_ADDR@h + ori r4,r4,CONFIG_SYS_LBCR_ADDR@l + + lis r5,CONFIG_SYS_LBC_LBCR@h + ori r5,r5,CONFIG_SYS_LBC_LBCR@l + stw r5,0(r4) + isync + + /* invalidate this temp TLB */ + lis r4,CONFIG_SYS_LBC_ADDR@h + ori r4,r4,CONFIG_SYS_LBC_ADDR@l + tlbivax 0,r4 + isync + +#endif /* CONFIG_MPC8569 */ + /* create a temp mapping in AS=1 to the 4M boot window */ lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l |