summaryrefslogtreecommitdiff
path: root/cpu/mpc85xx/cpu.c
diff options
context:
space:
mode:
Diffstat (limited to 'cpu/mpc85xx/cpu.c')
-rw-r--r--cpu/mpc85xx/cpu.c60
1 files changed, 28 insertions, 32 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index ef976a4..d88c564 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -40,6 +40,8 @@ DECLARE_GLOBAL_DATA_PTR;
struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8533, 8533),
CPU_TYPE_ENTRY(8533, 8533_E),
+ CPU_TYPE_ENTRY(8535, 8535),
+ CPU_TYPE_ENTRY(8535, 8535_E),
CPU_TYPE_ENTRY(8536, 8536),
CPU_TYPE_ENTRY(8536, 8536_E),
CPU_TYPE_ENTRY(8540, 8540),
@@ -184,6 +186,10 @@ int checkcpu (void)
printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
#endif
+#ifdef CONFIG_QE
+ printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
+#endif
+
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
return 0;
@@ -260,26 +266,28 @@ reset_85xx_watchdog(void)
#if defined(CONFIG_DDR_ECC)
void dma_init(void) {
- volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ volatile fsl_dma_t *dma = &dma_base->dma[0];
- dma->satr0 = 0x02c40000;
- dma->datr0 = 0x02c40000;
- dma->sr0 = 0xfffffff; /* clear any errors */
+ dma->satr = 0x00040000;
+ dma->datr = 0x00040000;
+ dma->sr = 0xffffffff; /* clear any errors */
asm("sync; isync; msync");
return;
}
uint dma_check(void) {
- volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
- volatile uint status = dma->sr0;
+ volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ volatile fsl_dma_t *dma = &dma_base->dma[0];
+ volatile uint status = dma->sr;
/* While the channel is busy, spin */
while((status & 4) == 4) {
- status = dma->sr0;
+ status = dma->sr;
}
- /* clear MR0[CS] channel start bit */
- dma->mr0 &= 0x00000001;
+ /* clear MR[CS] channel start bit */
+ dma->mr &= 0x00000001;
asm("sync;isync;msync");
if (status != 0) {
@@ -289,14 +297,15 @@ uint dma_check(void) {
}
int dma_xfer(void *dest, uint count, void *src) {
- volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ volatile fsl_dma_t *dma = &dma_base->dma[0];
- dma->dar0 = (uint) dest;
- dma->sar0 = (uint) src;
- dma->bcr0 = count;
- dma->mr0 = 0xf000004;
+ dma->dar = (uint) dest;
+ dma->sar = (uint) src;
+ dma->bcr = count;
+ dma->mr = 0xf000004;
asm("sync;isync;msync");
- dma->mr0 = 0xf000005;
+ dma->mr = 0xf000005;
asm("sync;isync;msync");
return dma_check();
}
@@ -377,24 +386,11 @@ int cpu_eth_init(bd_t *bis)
#if defined(CONFIG_ETHER_ON_FCC)
fec_initialize(bis);
#endif
-#if defined(CONFIG_UEC_ETH1)
- uec_initialize(0);
-#endif
-#if defined(CONFIG_UEC_ETH2)
- uec_initialize(1);
-#endif
-#if defined(CONFIG_UEC_ETH3)
- uec_initialize(2);
-#endif
-#if defined(CONFIG_UEC_ETH4)
- uec_initialize(3);
-#endif
-#if defined(CONFIG_UEC_ETH5)
- uec_initialize(4);
-#endif
-#if defined(CONFIG_UEC_ETH6)
- uec_initialize(5);
+
+#if defined(CONFIG_UEC_ETH)
+ uec_standard_init(bis);
#endif
+
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
tsec_standard_init(bis);
#endif