summaryrefslogtreecommitdiff
path: root/cpu/mpc83xx
diff options
context:
space:
mode:
Diffstat (limited to 'cpu/mpc83xx')
-rw-r--r--cpu/mpc83xx/cpu.c66
-rw-r--r--cpu/mpc83xx/cpu_init.c338
-rw-r--r--cpu/mpc83xx/ecc.c4
-rw-r--r--cpu/mpc83xx/fdt.c9
-rw-r--r--cpu/mpc83xx/interrupts.c4
-rw-r--r--cpu/mpc83xx/nand_init.c40
-rw-r--r--cpu/mpc83xx/pci.c10
-rw-r--r--cpu/mpc83xx/qe_io.c2
-rw-r--r--cpu/mpc83xx/serdes.c4
-rw-r--r--cpu/mpc83xx/spd_sdram.c32
-rw-r--r--cpu/mpc83xx/speed.c44
-rw-r--r--cpu/mpc83xx/start.S318
-rw-r--r--cpu/mpc83xx/traps.c4
-rw-r--r--cpu/mpc83xx/u-boot.lds1
14 files changed, 528 insertions, 348 deletions
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 52e4476..587fca3 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -32,6 +32,8 @@
#include <mpc83xx.h>
#include <asm/processor.h>
#include <libfdt.h>
+#include <tsec.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -66,7 +68,7 @@ int checkcpu(void)
CPU_TYPE_ENTRY(8379),
};
- immr = (immap_t *)CFG_IMMR;
+ immr = (immap_t *)CONFIG_SYS_IMMR;
puts("CPU: ");
@@ -123,8 +125,8 @@ int checkcpu(void)
* The 'dummy' variable is used to increment the MAD. 'dummy' is
* supposed to be a pointer to the memory of the device being
* programmed by the UPM. The data in the MDR is written into
- * memory and the MAD is incremented every time there's a read
- * from 'dummy'. Unfortunately, the current prototype for this
+ * memory and the MAD is incremented every time there's a write
+ * to 'dummy'. Unfortunately, the current prototype for this
* function doesn't allow for passing the address of this
* device, and changing the prototype will break a number lots
* of other code, so we need to use a round-about way of finding
@@ -146,9 +148,8 @@ int checkcpu(void)
*/
void upmconfig (uint upm, uint *table, uint size)
{
-#if defined(CONFIG_MPC834X)
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile lbus83xx_t *lbus = &immap->lbus;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ volatile fsl_lbus_t *lbus = &immap->lbus;
volatile uchar *dummy = NULL;
const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
@@ -173,16 +174,13 @@ void upmconfig (uint upm, uint *table, uint size)
for (i = 0; i < size; i++) {
lbus->mdr = table[i];
__asm__ __volatile__ ("sync");
- *dummy; /* Write the value to memory and increment MAD */
+ *dummy = 0; /* Write the value to memory and increment MAD */
__asm__ __volatile__ ("sync");
+ while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
}
/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
*mxmr &= 0xCFFFFFC0;
-#else
- printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
- hang();
-#endif
}
@@ -194,7 +192,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
ulong addr;
#endif
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#ifdef MPC83xx_RESET
/* Interrupts and MMU off */
@@ -233,7 +231,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
- addr = CFG_RESET_ADDRESS;
+ addr = CONFIG_SYS_RESET_ADDRESS;
printf("resetting the board.");
printf("\n");
@@ -264,7 +262,7 @@ void watchdog_reset (void)
int re_enable = disable_interrupts();
/* Reset the 83xx watchdog */
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
immr->wdt.swsrr = 0x556c;
immr->wdt.swsrr = 0xaa39;
@@ -276,7 +274,7 @@ void watchdog_reset (void)
#if defined(CONFIG_DDR_ECC)
void dma_init(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile dma83xx_t *dma = &immap->dma;
volatile u32 status = swab32(dma->dmasr0);
volatile u32 dmamr0 = swab32(dma->dmamr0);
@@ -307,7 +305,7 @@ void dma_init(void)
uint dma_check(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile dma83xx_t *dma = &immap->dma;
volatile u32 status = swab32(dma->dmasr0);
volatile u32 byte_count = swab32(dma->dmabcr0);
@@ -326,7 +324,7 @@ uint dma_check(void)
int dma_xfer(void *dest, u32 count, void *src)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile dma83xx_t *dma = &immap->dma;
volatile u32 dmamr0;
@@ -358,22 +356,32 @@ int dma_xfer(void *dest, u32 count, void *src)
}
#endif /*CONFIG_DDR_ECC*/
-#ifdef CONFIG_TSEC_ENET
-/* Default initializations for TSEC controllers. To override,
- * create a board-specific function called:
- * int board_eth_init(bd_t *bis)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
*/
-
-extern int tsec_initialize(bd_t * bis, int index, char *devname);
-
int cpu_eth_init(bd_t *bis)
{
-#if defined(CONFIG_TSEC1)
- tsec_initialize(bis, 0, CONFIG_TSEC1_NAME);
+#if defined(CONFIG_UEC_ETH1)
+ uec_initialize(0);
+#endif
+#if defined(CONFIG_UEC_ETH2)
+ uec_initialize(1);
#endif
-#if defined(CONFIG_TSEC2)
- tsec_initialize(bis, 1, CONFIG_TSEC2_NAME);
+#if defined(CONFIG_UEC_ETH3)
+ uec_initialize(2);
+#endif
+#if defined(CONFIG_UEC_ETH4)
+ uec_initialize(3);
+#endif
+#if defined(CONFIG_UEC_ETH5)
+ uec_initialize(4);
+#endif
+#if defined(CONFIG_UEC_ETH6)
+ uec_initialize(5);
+#endif
+#if defined(CONFIG_TSEC_ENET)
+ tsec_standard_init(bis);
#endif
return 0;
}
-#endif
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 67c9e57..491c2e5 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -60,113 +60,117 @@ static void config_qe_ioports(void)
void cpu_init_f (volatile immap_t * im)
{
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
/* system performance tweaking */
-#ifdef CFG_ACR_PIPE_DEP
+#ifdef CONFIG_SYS_ACR_PIPE_DEP
/* Arbiter pipeline depth */
im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
- (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+ (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
#endif
-#ifdef CFG_ACR_RPTCNT
+#ifdef CONFIG_SYS_ACR_RPTCNT
/* Arbiter repeat count */
im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
- (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
+ (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
#endif
-#ifdef CFG_SPCR_OPT
+#ifdef CONFIG_SYS_SPCR_OPT
/* Optimize transactions between CSB and other devices */
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
- (CFG_SPCR_OPT << SPCR_OPT_SHIFT);
+ (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
#endif
-#ifdef CFG_SPCR_TSECEP
+#ifdef CONFIG_SYS_SPCR_TSECEP
/* all eTSEC's Emergency priority */
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
- (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
+ (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
#endif
-#ifdef CFG_SPCR_TSEC1EP
+#ifdef CONFIG_SYS_SPCR_TSEC1EP
/* TSEC1 Emergency priority */
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
- (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
+ (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
#endif
-#ifdef CFG_SPCR_TSEC2EP
+#ifdef CONFIG_SYS_SPCR_TSEC2EP
/* TSEC2 Emergency priority */
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
- (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
+ (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
#endif
-#ifdef CFG_SCCR_ENCCM
+#ifdef CONFIG_SYS_SCCR_ENCCM
/* Encryption clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
- (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
+ (CONFIG_SYS_SCCR_ENCCM << SCCR_PCICM_SHIFT);
#endif
-#ifdef CFG_SCCR_PCICM
+#ifdef CONFIG_SYS_SCCR_PCICM
/* PCI & DMA clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
- (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
+ (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT);
#endif
-#ifdef CFG_SCCR_TSECCM
+#ifdef CONFIG_SYS_SCCR_TSECCM
/* all TSEC's clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
- (CFG_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
+ (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
#endif
-#ifdef CFG_SCCR_TSEC1CM
+#ifdef CONFIG_SYS_SCCR_TSEC1CM
/* TSEC1 clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
- (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
+ (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
#endif
-#ifdef CFG_SCCR_TSEC2CM
+#ifdef CONFIG_SYS_SCCR_TSEC2CM
/* TSEC2 clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
- (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
+ (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
#endif
-#ifdef CFG_SCCR_TSEC1ON
+#ifdef CONFIG_SYS_SCCR_TSEC1ON
/* TSEC1 clock switch */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
- (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
+ (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
#endif
-#ifdef CFG_SCCR_TSEC2ON
+#ifdef CONFIG_SYS_SCCR_TSEC2ON
/* TSEC2 clock switch */
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
- (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
+ (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
#endif
-#ifdef CFG_SCCR_USBMPHCM
+#ifdef CONFIG_SYS_SCCR_USBMPHCM
/* USB MPH clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
- (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
+ (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
#endif
-#ifdef CFG_SCCR_USBDRCM
+#ifdef CONFIG_SYS_SCCR_USBDRCM
/* USB DR clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
- (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
+ (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
#endif
-#ifdef CFG_SCCR_SATACM
+#ifdef CONFIG_SYS_SCCR_SATACM
/* SATA controller clock mode */
im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
- (CFG_SCCR_SATACM << SCCR_SATACM_SHIFT);
+ (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT);
#endif
/* RSR - Reset Status Register - clear all status (4.6.1.3) */
gd->reset_status = im->reset.rsr;
im->reset.rsr = ~(RSR_RES);
+ /* AER - Arbiter Event Register - store status */
+ gd->arbiter_event_attributes = im->arbiter.aeatr;
+ gd->arbiter_event_address = im->arbiter.aeadr;
+
/*
* RMR - Reset Mode Register
* contains checkstop reset enable (4.6.1.4)
@@ -174,30 +178,30 @@ void cpu_init_f (volatile immap_t * im)
im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
/* LCRR - Clock Ratio Register (10.3.1.16) */
- im->lbus.lcrr = CFG_LCRR;
+ im->lbus.lcrr = CONFIG_SYS_LCRR;
/* Enable Time Base & Decrimenter ( so we will have udelay() )*/
im->sysconf.spcr |= SPCR_TBEN;
/* System General Purpose Register */
-#ifdef CFG_SICRH
+#ifdef CONFIG_SYS_SICRH
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313)
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
- im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CFG_SICRH;
+ im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH;
#else
- im->sysconf.sicrh = CFG_SICRH;
+ im->sysconf.sicrh = CONFIG_SYS_SICRH;
#endif
#endif
-#ifdef CFG_SICRL
- im->sysconf.sicrl = CFG_SICRL;
+#ifdef CONFIG_SYS_SICRL
+ im->sysconf.sicrl = CONFIG_SYS_SICRL;
#endif
/* DDR control driver register */
-#ifdef CFG_DDRCDR
- im->sysconf.ddrcdr = CFG_DDRCDR;
+#ifdef CONFIG_SYS_DDRCDR
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
#endif
/* Output buffer impedance register */
-#ifdef CFG_OBIR
- im->sysconf.obir = CFG_OBIR;
+#ifdef CONFIG_SYS_OBIR
+ im->sysconf.obir = CONFIG_SYS_OBIR;
#endif
#ifdef CONFIG_QE
@@ -214,88 +218,88 @@ void cpu_init_f (volatile immap_t * im)
* has been determined
*/
-#if defined(CFG_BR0_PRELIM) \
- && defined(CFG_OR0_PRELIM) \
- && defined(CFG_LBLAWBAR0_PRELIM) \
- && defined(CFG_LBLAWAR0_PRELIM)
- im->lbus.bank[0].br = CFG_BR0_PRELIM;
- im->lbus.bank[0].or = CFG_OR0_PRELIM;
- im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
- im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
+#if defined(CONFIG_SYS_BR0_PRELIM) \
+ && defined(CONFIG_SYS_OR0_PRELIM) \
+ && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
+ && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
+ im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
+ im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
+ im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
+ im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
#else
-#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
+#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
#endif
-#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
- im->lbus.bank[1].br = CFG_BR1_PRELIM;
- im->lbus.bank[1].or = CFG_OR1_PRELIM;
+#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
+ im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
+ im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM)
- im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
- im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
+ im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
+ im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
#endif
-#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
- im->lbus.bank[2].br = CFG_BR2_PRELIM;
- im->lbus.bank[2].or = CFG_OR2_PRELIM;
+#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
+ im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
+ im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM)
- im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
- im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
+ im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
+ im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
#endif
-#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
- im->lbus.bank[3].br = CFG_BR3_PRELIM;
- im->lbus.bank[3].or = CFG_OR3_PRELIM;
+#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
+ im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
+ im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM)
- im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
- im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
+ im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
+ im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
#endif
-#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
- im->lbus.bank[4].br = CFG_BR4_PRELIM;
- im->lbus.bank[4].or = CFG_OR4_PRELIM;
+#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
+ im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
+ im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM)
- im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
- im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
+ im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
+ im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
#endif
-#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
- im->lbus.bank[5].br = CFG_BR5_PRELIM;
- im->lbus.bank[5].or = CFG_OR5_PRELIM;
+#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
+ im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
+ im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM)
- im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
- im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
+ im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
+ im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
#endif
-#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
- im->lbus.bank[6].br = CFG_BR6_PRELIM;
- im->lbus.bank[6].or = CFG_OR6_PRELIM;
+#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
+ im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
+ im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM)
- im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
- im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
+ im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
+ im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
#endif
-#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
- im->lbus.bank[7].br = CFG_BR7_PRELIM;
- im->lbus.bank[7].or = CFG_OR7_PRELIM;
+#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
+ im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
+ im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
#endif
-#if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM)
- im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
- im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
+#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
+ im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
+ im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
#endif
-#ifdef CFG_GPIO1_PRELIM
- im->gpio[0].dir = CFG_GPIO1_DIR;
- im->gpio[0].dat = CFG_GPIO1_DAT;
+#ifdef CONFIG_SYS_GPIO1_PRELIM
+ im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
+ im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
#endif
-#ifdef CFG_GPIO2_PRELIM
- im->gpio[1].dir = CFG_GPIO2_DIR;
- im->gpio[1].dat = CFG_GPIO2_DAT;
+#ifdef CONFIG_SYS_GPIO2_PRELIM
+ im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
+ im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
}
int cpu_init_r (void)
{
#ifdef CONFIG_QE
- uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */
+ uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
qe_init(qe_base);
qe_reset();
#endif
@@ -303,6 +307,130 @@ int cpu_init_r (void)
}
/*
+ * Print out the bus arbiter event
+ */
+#if defined(CONFIG_DISPLAY_AER_FULL)
+static int print_83xx_arb_event(int force)
+{
+ static char* event[] = {
+ "Address Time Out",
+ "Data Time Out",
+ "Address Only Transfer Type",
+ "External Control Word Transfer Type",
+ "Reserved Transfer Type",
+ "Transfer Error",
+ "reserved",
+ "reserved"
+ };
+ static char* master[] = {
+ "e300 Core Data Transaction",
+ "reserved",
+ "e300 Core Instruction Fetch",
+ "reserved",
+ "TSEC1",
+ "TSEC2",
+ "USB MPH",
+ "USB DR",
+ "Encryption Core",
+ "I2C Boot Sequencer",
+ "JTAG",
+ "reserved",
+ "eSDHC",
+ "PCI1",
+ "PCI2",
+ "DMA",
+ "QUICC Engine 00",
+ "QUICC Engine 01",
+ "QUICC Engine 10",
+ "QUICC Engine 11",
+ "reserved",
+ "reserved",
+ "reserved",
+ "reserved",
+ "SATA1",
+ "SATA2",
+ "SATA3",
+ "SATA4",
+ "reserved",
+ "PCI Express 1",
+ "PCI Express 2",
+ "TDM-DMAC"
+ };
+ static char *transfer[] = {
+ "Address-only, Clean Block",
+ "Address-only, lwarx reservation set",
+ "Single-beat or Burst write",
+ "reserved",
+ "Address-only, Flush Block",
+ "reserved",
+ "Burst write",
+ "reserved",
+ "Address-only, sync",
+ "Address-only, tlbsync",
+ "Single-beat or Burst read",
+ "Single-beat or Burst read",
+ "Address-only, Kill Block",
+ "Address-only, icbi",
+ "Burst read",
+ "reserved",
+ "Address-only, eieio",
+ "reserved",
+ "Single-beat write",
+ "reserved",
+ "ecowx - Illegal single-beat write",
+ "reserved",
+ "reserved",
+ "reserved",
+ "Address-only, TLB Invalidate",
+ "reserved",
+ "Single-beat or Burst read",
+ "reserved",
+ "eciwx - Illegal single-beat read",
+ "reserved",
+ "Burst read",
+ "reserved"
+ };
+
+ int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
+ >> AEATR_EVENT_SHIFT;
+ int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
+ >> AEATR_MSTR_ID_SHIFT;
+ int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
+ >> AEATR_TBST_SHIFT;
+ int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
+ >> AEATR_TSIZE_SHIFT;
+ int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
+ >> AEATR_TTYPE_SHIFT;
+
+ if (!force && !gd->arbiter_event_address)
+ return 0;
+
+ puts("Arbiter Event Status:\n");
+ printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address);
+ printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
+ printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
+ printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
+ tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
+ printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
+
+ return gd->arbiter_event_address;
+}
+
+#elif defined(CONFIG_DISPLAY_AER_BRIEF)
+
+static int print_83xx_arb_event(int force)
+{
+ if (!force && !gd->arbiter_event_address)
+ return 0;
+
+ printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
+ gd->arbiter_event_attributes, gd->arbiter_event_address);
+
+ return gd->arbiter_event_address;
+}
+#endif /* CONFIG_DISPLAY_AER_xxxx */
+
+/*
* Figure out the cause of the reset
*/
int prt_83xx_rsr(void)
@@ -334,6 +462,12 @@ int prt_83xx_rsr(void)
printf("%s%s", sep, bits[i].desc);
sep = ", ";
}
- puts("\n\n");
+ puts("\n");
+
+#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
+ print_83xx_arb_event(rsr & RSR_BMRS);
+#endif
+ puts("\n");
+
return 0;
}
diff --git a/cpu/mpc83xx/ecc.c b/cpu/mpc83xx/ecc.c
index 5137ab6..5ab169f 100644
--- a/cpu/mpc83xx/ecc.c
+++ b/cpu/mpc83xx/ecc.c
@@ -20,7 +20,7 @@
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
void ecc_print_status(void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
printf("\nECC mode: %s\n\n",
@@ -100,7 +100,7 @@ void ecc_print_status(void)
int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
volatile u32 val;
u64 *addr;
diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c
index 39bd9dc..f890775 100644
--- a/cpu/mpc83xx/fdt.c
+++ b/cpu/mpc83xx/fdt.c
@@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
void ft_cpu_setup(void *blob, bd_t *bd)
{
- immap_t *immr = (immap_t *)CFG_IMMR;
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
int spridr = immr->sysconf.spridr;
/*
@@ -52,7 +52,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_crypto_node(blob, 0x0204);
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
- defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
+ defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
fdt_fixup_ethernet(blob);
#endif
@@ -76,9 +77,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_qe_setup(blob);
#endif
-#ifdef CFG_NS16550
+#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "ns16550",
- "clock-frequency", CFG_NS16550_CLK, 1);
+ "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c
index 98ed21c..faffbaf 100644
--- a/cpu/mpc83xx/interrupts.c
+++ b/cpu/mpc83xx/interrupts.c
@@ -38,9 +38,9 @@ struct irq_action {
int interrupt_init_cpu (unsigned *decrementer_count)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- *decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
+ *decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ;
/* Enable e300 time base */
diff --git a/cpu/mpc83xx/nand_init.c b/cpu/mpc83xx/nand_init.c
index e92f230..38e141a 100644
--- a/cpu/mpc83xx/nand_init.c
+++ b/cpu/mpc83xx/nand_init.c
@@ -37,7 +37,7 @@ void cpu_init_f (volatile immap_t * im)
int i;
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
for (i = 0; i < sizeof(gd_t); i++)
@@ -45,34 +45,34 @@ void cpu_init_f (volatile immap_t * im)
/* system performance tweaking */
-#ifdef CFG_ACR_PIPE_DEP
+#ifdef CONFIG_SYS_ACR_PIPE_DEP
/* Arbiter pipeline depth */
im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
- (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+ (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
#endif
-#ifdef CFG_ACR_RPTCNT
+#ifdef CONFIG_SYS_ACR_RPTCNT
/* Arbiter repeat count */
im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
- (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
+ (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
#endif
-#ifdef CFG_SPCR_OPT
+#ifdef CONFIG_SYS_SPCR_OPT
/* Optimize transactions between CSB and other devices */
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
- (CFG_SPCR_OPT << SPCR_OPT_SHIFT);
+ (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
#endif
/* Enable Time Base & Decrimenter (so we will have udelay()) */
im->sysconf.spcr |= SPCR_TBEN;
/* DDR control driver register */
-#ifdef CFG_DDRCDR
- im->sysconf.ddrcdr = CFG_DDRCDR;
+#ifdef CONFIG_SYS_DDRCDR
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
#endif
/* Output buffer impedance register */
-#ifdef CFG_OBIR
- im->sysconf.obir = CFG_OBIR;
+#ifdef CONFIG_SYS_OBIR
+ im->sysconf.obir = CONFIG_SYS_OBIR;
#endif
/*
@@ -84,16 +84,16 @@ void cpu_init_f (volatile immap_t * im)
* has been determined
*/
-#if defined(CFG_NAND_BR_PRELIM) \
- && defined(CFG_NAND_OR_PRELIM) \
- && defined(CFG_NAND_LBLAWBAR_PRELIM) \
- && defined(CFG_NAND_LBLAWAR_PRELIM)
- im->lbus.bank[0].br = CFG_NAND_BR_PRELIM;
- im->lbus.bank[0].or = CFG_NAND_OR_PRELIM;
- im->sysconf.lblaw[0].bar = CFG_NAND_LBLAWBAR_PRELIM;
- im->sysconf.lblaw[0].ar = CFG_NAND_LBLAWAR_PRELIM;
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) \
+ && defined(CONFIG_SYS_NAND_OR_PRELIM) \
+ && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
+ && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
+ im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM;
+ im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM;
+ im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
+ im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
#else
-#error CFG_NAND_BR_PRELIM, CFG_NAND_OR_PRELIM, CFG_NAND_LBLAWBAR_PRELIM & CFG_NAND_LBLAWAR_PRELIM must be defined
+#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
#endif
}
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
index c3ec5f8..ab0760b 100644
--- a/cpu/mpc83xx/pci.c
+++ b/cpu/mpc83xx/pci.c
@@ -42,7 +42,7 @@ static int pci_num_buses;
static void pci_init_bus(int bus, struct pci_region *reg)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile pot83xx_t *pot = immr->ios.pot;
volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
struct pci_controller *hose = &pci_hose[bus];
@@ -83,7 +83,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
pci_ctrl->pibar1 = 0;
pci_ctrl->piebar1 = 0;
pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+ PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
i = hose->region_count++;
hose->regions[i].bus_start = 0;
@@ -94,8 +94,8 @@ static void pci_init_bus(int bus, struct pci_region *reg)
hose->first_busno = 0;
hose->last_busno = 0xff;
- pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80,
- CFG_IMMR + 0x8304 + bus * 0x80);
+ pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
+ CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
pci_register_hose(hose);
@@ -133,7 +133,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
*/
void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
int i;
if (num_buses > MAX_BUSES) {
diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c
index ce91a07..db94f00 100644
--- a/cpu/mpc83xx/qe_io.c
+++ b/cpu/mpc83xx/qe_io.c
@@ -33,7 +33,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
u32 pin_2bit_assign;
u32 pin_1bit_mask;
u32 tmp_val;
- volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
/* Caculate pin location and 2bit mask and dir */
diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c
index 020c4c8..3936796 100644
--- a/cpu/mpc83xx/serdes.c
+++ b/cpu/mpc83xx/serdes.c
@@ -42,9 +42,9 @@
#define FSL_SRDSRSTCTL_RST 0x80000000
#define FSL_SRDSRSTCTL_SATA_RESET 0xf
-void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd)
+void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
{
- void *regs = (void *)CFG_IMMR + offset;
+ void *regs = (void *)CONFIG_SYS_IMMR + offset;
u32 tmp;
/* 1.0V corevdd */
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 76f2474..42a4e67 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
void board_add_ram_info(int use_default)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
char buf[32];
@@ -57,9 +57,9 @@ void board_add_ram_info(int use_default)
printf(", %s MHz)", strmhz(buf, gd->mem_clk));
-#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
+#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
puts("\nSDRAM: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
+ print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
#endif
}
@@ -71,8 +71,8 @@ extern uint dma_check(void);
extern int dma_xfer(void *dest, uint count, void *src);
#endif
-#ifndef CFG_READ_SPD
-#define CFG_READ_SPD i2c_read
+#ifndef CONFIG_SYS_READ_SPD
+#define CONFIG_SYS_READ_SPD i2c_read
#endif
/*
@@ -129,7 +129,7 @@ static void spd_debug(spd_eeprom_t *spd)
long int spd_sdram()
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
spd_eeprom_t spd;
@@ -158,7 +158,7 @@ long int spd_sdram()
unsigned int pvr = get_pvr();
/* Read SPD parameters with I2C */
- CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
+ CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
#ifdef SPD_DEBUG
spd_debug(&spd);
#endif
@@ -194,12 +194,12 @@ long int spd_sdram()
return 0;
}
-#ifdef CFG_DDRCDR_VALUE
+#ifdef CONFIG_SYS_DDRCDR_VALUE
/*
* Adjust DDR II IO voltage biasing. It just makes it work.
*/
if(spd.mem_type == SPD_MEMTYPE_DDR2) {
- immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+ immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
}
udelay(50000);
#endif
@@ -214,7 +214,7 @@ long int spd_sdram()
}
/* Setup DDR chip select register */
-#ifdef CFG_83XX_DDR_USES_CS0
+#ifdef CONFIG_SYS_83XX_DDR_USES_CS0
ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
ddr->cs_config[0] = ( 1 << 31
| (odt_rd_cfg << 20)
@@ -274,7 +274,7 @@ long int spd_sdram()
/*
* Set up LAWBAR for all of DDR.
*/
- ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+ ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
debug("DDR:bar=0x%08x\n", ecm->bar);
debug("DDR:ar=0x%08x\n", ecm->ar);
@@ -314,7 +314,7 @@ long int spd_sdram()
+ (spd.clk_cycle & 0x0f));
max_data_rate = max_bus_clk * 2;
- debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
+ debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
ddrc_clk = gd->mem_clk / 1000000;
effective_data_rate = 0;
@@ -401,7 +401,7 @@ long int spd_sdram()
}
}
- debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate);
+ debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
/*
@@ -724,8 +724,8 @@ long int spd_sdram()
debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
}
-#ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
- ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
#endif
debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
@@ -842,7 +842,7 @@ static __inline__ unsigned long get_tbms (void)
/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
void ddr_enable_ecc(unsigned int dram_size)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ddr83xx_t *ddr= &immap->ddr;
unsigned long t_start, t_end;
register u64 *p;
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 76c569d..bf9bf36 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -90,7 +90,7 @@ corecnf_t corecnf_tab[] = {
*/
int get_clocks(void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 pci_sync_in;
u8 spmf;
u8 clkin_div;
@@ -499,44 +499,46 @@ ulong get_bus_freq(ulong dummy)
int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
+ char buf[32];
+
printf("Clock configuration:\n");
- printf(" Core: %4d MHz\n", gd->core_clk / 1000000);
- printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
+ printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk));
+ printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
- printf(" QE: %4d MHz\n", gd->qe_clk / 1000000);
- printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000);
+ printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk));
+ printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk));
#endif
- printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
- printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
- printf(" DDR: %4ld MHz\n", gd->mem_clk / 1000000);
+ printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
+ printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk));
+ printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
#if defined(CONFIG_MPC8360)
- printf(" DDR Secondary: %4d MHz\n", gd->mem_sec_clk / 1000000);
+ printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
#endif
- printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
- printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
+ printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk));
+ printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
#if !defined(CONFIG_MPC832X)
- printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
+ printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
#endif
#if defined(CONFIG_MPC8315)
- printf(" TDM: %4d MHz\n", gd->tdm_clk / 1000000);
+ printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk));
#endif
#if defined(CONFIG_MPC837X)
- printf(" SDHC: %4d MHz\n", gd->sdhc_clk / 1000000);
+ printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
#endif
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
- printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
- printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
- printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000);
+ printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
+ printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
+ printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
#endif
#if defined(CONFIG_MPC834X)
- printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000);
+ printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
#endif
#if defined(CONFIG_MPC837X)
- printf(" PCIEXP1: %4d MHz\n", gd->pciexp1_clk / 1000000);
- printf(" PCIEXP2: %4d MHz\n", gd->pciexp2_clk / 1000000);
+ printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
+ printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
- printf(" SATA: %4d MHz\n", gd->sata_clk / 1000000);
+ printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk));
#endif
return 0;
}
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index 16ed494..792b2c8 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -29,6 +29,7 @@
#include <config.h>
#include <mpc83xx.h>
+#include <timestamp.h>
#include <version.h>
#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
@@ -57,8 +58,8 @@
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
#endif
-#if !defined(CONFIG_NAND_SPL) && !defined(CFG_RAMBOOT)
-#define CFG_FLASHBOOT
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_SYS_FLASHBOOT
#endif
/*
@@ -93,8 +94,8 @@
.fill 8,1,(((w)>> 8)&0xff); \
.fill 8,1,(((w) )&0xff)
- _HRCW_TABLE_ENTRY(CFG_HRCW_LOW)
- _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
+ _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
+ _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
/*
* Magic number and version string - put it after the HRCW since it
@@ -105,16 +106,16 @@
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii " ", CONFIG_IDENT_STRING, "\0"
#ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined
-#endif /* CFG_DEFAULT_IMMR */
-#ifndef CFG_IMMR
-#define CFG_IMMR CONFIG_DEFAULT_IMMR
-#endif /* CFG_IMMR */
+#endif /* CONFIG_SYS_DEFAULT_IMMR */
+#ifndef CONFIG_SYS_IMMR
+#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
+#endif /* CONFIG_SYS_IMMR */
/*
* After configuration, a system reset exception is executed using the
@@ -160,24 +161,36 @@ boot_cold: /* time t 3 */
nop
boot_warm: /* time t 5 */
mfmsr r5 /* save msr contents */
- lis r3, CFG_IMMR@h
- ori r3, r3, CFG_IMMR@l
+ lis r3, CONFIG_SYS_IMMR@h
+ ori r3, r3, CONFIG_SYS_IMMR@l
stw r3, IMMRBAR(r4)
/* Initialise the E300 processor core */
/*------------------------------------------*/
+#ifdef CONFIG_NAND_SPL
+ /* The FCM begins execution after only the first page
+ * is loaded. Wait for the rest before branching
+ * to another flash page.
+ */
+ addi r7, r3, 0x50b0
+1: dcbi 0, r7
+ lwz r6, 0(r7)
+ andi. r6, r6, 1
+ beq 1b
+#endif
+
bl init_e300_core
-#ifdef CFG_FLASHBOOT
+#ifdef CONFIG_SYS_FLASHBOOT
/* Inflate flash location so it appears everywhere, calculate */
/* the absolute address in final location of the FLASH, jump */
/* there and deflate the flash size back to minimal size */
/*------------------------------------------------------------*/
bl map_flash_by_law1
- lis r4, (CFG_MONITOR_BASE)@h
- ori r4, r4, (CFG_MONITOR_BASE)@l
+ lis r4, (CONFIG_SYS_MONITOR_BASE)@h
+ ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r5
blr
@@ -185,7 +198,7 @@ in_flash:
#if 1 /* Remapping flash with LAW0. */
bl remap_flash_by_law0
#endif
-#endif /* CFG_FLASHBOOT */
+#endif /* CONFIG_SYS_FLASHBOOT */
/* setup the bats */
bl setup_bats
@@ -208,18 +221,18 @@ in_flash:
bl enable_addr_trans
sync
- /* enable and invalidate the data cache */
+ /* enable the data cache */
bl dcache_enable
sync
-#ifdef CFG_INIT_RAM_LOCK
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
bl lock_ram_in_cache
sync
#endif
/* set up the stack pointer in our newly created
* cache-ram (r1) */
- lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
- ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+ lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
+ ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
@@ -234,7 +247,7 @@ in_flash:
GET_GOT /* initialize GOT access */
/* r3: IMMR */
- lis r3, CFG_IMMR@h
+ lis r3, CONFIG_SYS_IMMR@h
/* run low-level CPU init code (in Flash)*/
bl cpu_init_f
@@ -456,11 +469,11 @@ init_e300_core: /* time t 10 */
mtspr SRR1, r3 /* Make SRR1 match MSR */
- lis r3, CFG_IMMR@h
+ lis r3, CONFIG_SYS_IMMR@h
#if defined(CONFIG_WATCHDOG)
/* Initialise the Wathcdog values and reset it (if req) */
/*------------------------------------------------------*/
- lis r4, CFG_WATCHDOG_VALUE
+ lis r4, CONFIG_SYS_WATCHDOG_VALUE
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
stw r4, SWCRR(r3)
@@ -483,22 +496,34 @@ init_e300_core: /* time t 10 */
1:
#endif /* CONFIG_WATCHDOG */
+#if defined(CONFIG_MASK_AER_AO)
+ /* Write the Arbiter Event Enable to mask Address Only traps. */
+ /* This prevents the dcbz instruction from being trapped when */
+ /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
+ /* COHERENCY bit is set in the WIMG bits, which is often */
+ /* needed for PCI operation. */
+ lwz r4, 0x0808(r3)
+ rlwinm r0, r4, 0, ~AER_AO
+ stw r0, 0x0808(r3)
+#endif /* CONFIG_MASK_AER_AO */
+
/* Initialize the Hardware Implementation-dependent Registers */
/* HID0 also contains cache control */
+ /* - force invalidation of data and instruction caches */
/*------------------------------------------------------*/
- lis r3, CFG_HID0_INIT@h
- ori r3, r3, CFG_HID0_INIT@l
+ lis r3, CONFIG_SYS_HID0_INIT@h
+ ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
SYNC
mtspr HID0, r3
- lis r3, CFG_HID0_FINAL@h
- ori r3, r3, CFG_HID0_FINAL@l
+ lis r3, CONFIG_SYS_HID0_FINAL@h
+ ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
SYNC
mtspr HID0, r3
- lis r3, CFG_HID2@h
- ori r3, r3, CFG_HID2@l
+ lis r3, CONFIG_SYS_HID2@h
+ ori r3, r3, CONFIG_SYS_HID2@l
SYNC
mtspr HID2, r3
@@ -512,131 +537,131 @@ setup_bats:
addis r0, r0, 0x0000
/* IBAT 0 */
- addis r4, r0, CFG_IBAT0L@h
- ori r4, r4, CFG_IBAT0L@l
- addis r3, r0, CFG_IBAT0U@h
- ori r3, r3, CFG_IBAT0U@l
+ addis r4, r0, CONFIG_SYS_IBAT0L@h
+ ori r4, r4, CONFIG_SYS_IBAT0L@l
+ addis r3, r0, CONFIG_SYS_IBAT0U@h
+ ori r3, r3, CONFIG_SYS_IBAT0U@l
mtspr IBAT0L, r4
mtspr IBAT0U, r3
/* DBAT 0 */
- addis r4, r0, CFG_DBAT0L@h
- ori r4, r4, CFG_DBAT0L@l
- addis r3, r0, CFG_DBAT0U@h
- ori r3, r3, CFG_DBAT0U@l
+ addis r4, r0, CONFIG_SYS_DBAT0L@h
+ ori r4, r4, CONFIG_SYS_DBAT0L@l
+ addis r3, r0, CONFIG_SYS_DBAT0U@h
+ ori r3, r3, CONFIG_SYS_DBAT0U@l
mtspr DBAT0L, r4
mtspr DBAT0U, r3
/* IBAT 1 */
- addis r4, r0, CFG_IBAT1L@h
- ori r4, r4, CFG_IBAT1L@l
- addis r3, r0, CFG_IBAT1U@h
- ori r3, r3, CFG_IBAT1U@l
+ addis r4, r0, CONFIG_SYS_IBAT1L@h
+ ori r4, r4, CONFIG_SYS_IBAT1L@l
+ addis r3, r0, CONFIG_SYS_IBAT1U@h
+ ori r3, r3, CONFIG_SYS_IBAT1U@l
mtspr IBAT1L, r4
mtspr IBAT1U, r3
/* DBAT 1 */
- addis r4, r0, CFG_DBAT1L@h
- ori r4, r4, CFG_DBAT1L@l
- addis r3, r0, CFG_DBAT1U@h
- ori r3, r3, CFG_DBAT1U@l
+ addis r4, r0, CONFIG_SYS_DBAT1L@h
+ ori r4, r4, CONFIG_SYS_DBAT1L@l
+ addis r3, r0, CONFIG_SYS_DBAT1U@h
+ ori r3, r3, CONFIG_SYS_DBAT1U@l
mtspr DBAT1L, r4
mtspr DBAT1U, r3
/* IBAT 2 */
- addis r4, r0, CFG_IBAT2L@h
- ori r4, r4, CFG_IBAT2L@l
- addis r3, r0, CFG_IBAT2U@h
- ori r3, r3, CFG_IBAT2U@l
+ addis r4, r0, CONFIG_SYS_IBAT2L@h
+ ori r4, r4, CONFIG_SYS_IBAT2L@l
+ addis r3, r0, CONFIG_SYS_IBAT2U@h
+ ori r3, r3, CONFIG_SYS_IBAT2U@l
mtspr IBAT2L, r4
mtspr IBAT2U, r3
/* DBAT 2 */
- addis r4, r0, CFG_DBAT2L@h
- ori r4, r4, CFG_DBAT2L@l
- addis r3, r0, CFG_DBAT2U@h
- ori r3, r3, CFG_DBAT2U@l
+ addis r4, r0, CONFIG_SYS_DBAT2L@h
+ ori r4, r4, CONFIG_SYS_DBAT2L@l
+ addis r3, r0, CONFIG_SYS_DBAT2U@h
+ ori r3, r3, CONFIG_SYS_DBAT2U@l
mtspr DBAT2L, r4
mtspr DBAT2U, r3
/* IBAT 3 */
- addis r4, r0, CFG_IBAT3L@h
- ori r4, r4, CFG_IBAT3L@l
- addis r3, r0, CFG_IBAT3U@h
- ori r3, r3, CFG_IBAT3U@l
+ addis r4, r0, CONFIG_SYS_IBAT3L@h
+ ori r4, r4, CONFIG_SYS_IBAT3L@l
+ addis r3, r0, CONFIG_SYS_IBAT3U@h
+ ori r3, r3, CONFIG_SYS_IBAT3U@l
mtspr IBAT3L, r4
mtspr IBAT3U, r3
/* DBAT 3 */
- addis r4, r0, CFG_DBAT3L@h
- ori r4, r4, CFG_DBAT3L@l
- addis r3, r0, CFG_DBAT3U@h
- ori r3, r3, CFG_DBAT3U@l
+ addis r4, r0, CONFIG_SYS_DBAT3L@h
+ ori r4, r4, CONFIG_SYS_DBAT3L@l
+ addis r3, r0, CONFIG_SYS_DBAT3U@h
+ ori r3, r3, CONFIG_SYS_DBAT3U@l
mtspr DBAT3L, r4
mtspr DBAT3U, r3
#ifdef CONFIG_HIGH_BATS
/* IBAT 4 */
- addis r4, r0, CFG_IBAT4L@h
- ori r4, r4, CFG_IBAT4L@l
- addis r3, r0, CFG_IBAT4U@h
- ori r3, r3, CFG_IBAT4U@l
+ addis r4, r0, CONFIG_SYS_IBAT4L@h
+ ori r4, r4, CONFIG_SYS_IBAT4L@l
+ addis r3, r0, CONFIG_SYS_IBAT4U@h
+ ori r3, r3, CONFIG_SYS_IBAT4U@l
mtspr IBAT4L, r4
mtspr IBAT4U, r3
/* DBAT 4 */
- addis r4, r0, CFG_DBAT4L@h
- ori r4, r4, CFG_DBAT4L@l
- addis r3, r0, CFG_DBAT4U@h
- ori r3, r3, CFG_DBAT4U@l
+ addis r4, r0, CONFIG_SYS_DBAT4L@h
+ ori r4, r4, CONFIG_SYS_DBAT4L@l
+ addis r3, r0, CONFIG_SYS_DBAT4U@h
+ ori r3, r3, CONFIG_SYS_DBAT4U@l
mtspr DBAT4L, r4
mtspr DBAT4U, r3
/* IBAT 5 */
- addis r4, r0, CFG_IBAT5L@h
- ori r4, r4, CFG_IBAT5L@l
- addis r3, r0, CFG_IBAT5U@h
- ori r3, r3, CFG_IBAT5U@l
+ addis r4, r0, CONFIG_SYS_IBAT5L@h
+ ori r4, r4, CONFIG_SYS_IBAT5L@l
+ addis r3, r0, CONFIG_SYS_IBAT5U@h
+ ori r3, r3, CONFIG_SYS_IBAT5U@l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
/* DBAT 5 */
- addis r4, r0, CFG_DBAT5L@h
- ori r4, r4, CFG_DBAT5L@l
- addis r3, r0, CFG_DBAT5U@h
- ori r3, r3, CFG_DBAT5U@l
+ addis r4, r0, CONFIG_SYS_DBAT5L@h
+ ori r4, r4, CONFIG_SYS_DBAT5L@l
+ addis r3, r0, CONFIG_SYS_DBAT5U@h
+ ori r3, r3, CONFIG_SYS_DBAT5U@l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
/* IBAT 6 */
- addis r4, r0, CFG_IBAT6L@h
- ori r4, r4, CFG_IBAT6L@l
- addis r3, r0, CFG_IBAT6U@h
- ori r3, r3, CFG_IBAT6U@l
+ addis r4, r0, CONFIG_SYS_IBAT6L@h
+ ori r4, r4, CONFIG_SYS_IBAT6L@l
+ addis r3, r0, CONFIG_SYS_IBAT6U@h
+ ori r3, r3, CONFIG_SYS_IBAT6U@l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
/* DBAT 6 */
- addis r4, r0, CFG_DBAT6L@h
- ori r4, r4, CFG_DBAT6L@l
- addis r3, r0, CFG_DBAT6U@h
- ori r3, r3, CFG_DBAT6U@l
+ addis r4, r0, CONFIG_SYS_DBAT6L@h
+ ori r4, r4, CONFIG_SYS_DBAT6L@l
+ addis r3, r0, CONFIG_SYS_DBAT6U@h
+ ori r3, r3, CONFIG_SYS_DBAT6U@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
/* IBAT 7 */
- addis r4, r0, CFG_IBAT7L@h
- ori r4, r4, CFG_IBAT7L@l
- addis r3, r0, CFG_IBAT7U@h
- ori r3, r3, CFG_IBAT7U@l
+ addis r4, r0, CONFIG_SYS_IBAT7L@h
+ ori r4, r4, CONFIG_SYS_IBAT7L@l
+ addis r3, r0, CONFIG_SYS_IBAT7U@h
+ ori r3, r3, CONFIG_SYS_IBAT7U@l
mtspr IBAT7L, r4
mtspr IBAT7U, r3
/* DBAT 7 */
- addis r4, r0, CFG_DBAT7L@h
- ori r4, r4, CFG_DBAT7L@l
- addis r3, r0, CFG_DBAT7U@h
- ori r3, r3, CFG_DBAT7U@l
+ addis r4, r0, CONFIG_SYS_DBAT7L@h
+ ori r4, r4, CONFIG_SYS_DBAT7L@l
+ addis r3, r0, CONFIG_SYS_DBAT7U@h
+ ori r3, r3, CONFIG_SYS_DBAT7U@l
mtspr DBAT7L, r4
mtspr DBAT7U, r3
#endif
@@ -703,8 +728,7 @@ disable_addr_trans:
icache_enable:
mfspr r3, HID0
ori r3, r3, HID0_ICE
- lis r4, 0
- ori r4, r4, HID0_ILOCK
+ li r4, HID0_ICFI|HID0_ILOCK
andc r3, r3, r4
ori r4, r3, HID0_ICFI
isync
@@ -717,13 +741,10 @@ icache_enable:
icache_disable:
mfspr r3, HID0
lis r4, 0
- ori r4, r4, HID0_ICE|HID0_ILOCK
+ ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
andc r3, r3, r4
- ori r4, r3, HID0_ICFI
isync
- mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
- isync
- mtspr HID0, r3 /* clears invalidate */
+ mtspr HID0, r3 /* clears invalidate, enable and lock */
blr
.globl icache_status
@@ -737,25 +758,24 @@ dcache_enable:
mfspr r3, HID0
li r5, HID0_DCFI|HID0_DLOCK
andc r3, r3, r5
- mtspr HID0, r3 /* no invalidate, unlock */
ori r3, r3, HID0_DCE
- ori r5, r3, HID0_DCFI
- mtspr HID0, r5 /* enable + invalidate */
- mtspr HID0, r3 /* enable */
sync
+ mtspr HID0, r3 /* enable, no invalidate */
blr
.globl dcache_disable
dcache_disable:
+ mflr r4
+ bl flush_dcache /* uses r3 and r5 */
mfspr r3, HID0
- lis r4, 0
- ori r4, r4, HID0_DCE|HID0_DLOCK
- andc r3, r3, r4
- ori r4, r3, HID0_DCI
+ li r5, HID0_DCE|HID0_DLOCK
+ andc r3, r3, r5
+ ori r5, r3, HID0_DCFI
sync
- mtspr HID0, r4 /* sets invalidate, clears enable and lock */
+ mtspr HID0, r5 /* sets invalidate, clears enable and lock */
sync
mtspr HID0, r3 /* clears invalidate */
+ mtlr r4
blr
.globl dcache_status
@@ -764,6 +784,18 @@ dcache_status:
rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
blr
+ .globl flush_dcache
+flush_dcache:
+ lis r3, 0
+ lis r5, CONFIG_SYS_CACHELINE_SIZE
+1: cmp 0, 1, r3, r5
+ bge 2f
+ lwz r5, 0(r3)
+ lis r5, CONFIG_SYS_CACHELINE_SIZE
+ addi r3, r3, 0x4
+ b 1b
+2: blr
+
.globl get_pvr
get_pvr:
mfspr r3, PVR
@@ -801,16 +833,16 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__bss_start)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE)
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
* + Destination Address
*
* Offset:
@@ -1054,15 +1086,15 @@ trap_reloc:
blr
#endif /* !CONFIG_NAND_SPL */
-#ifdef CFG_INIT_RAM_LOCK
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
lock_ram_in_cache:
/* Allocate Initial RAM in data cache.
*/
- lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
- li r2, ((CFG_INIT_RAM_END & ~31) + \
- (CFG_INIT_RAM_ADDR & 31) + 31) / 32
- mtctr r2
+ lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+ li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r4
1:
dcbz r0, r3
addi r3, r3, 32
@@ -1070,7 +1102,7 @@ lock_ram_in_cache:
/* Lock the data cache */
mfspr r0, HID0
- ori r0, r0, 0x1000
+ ori r0, r0, HID0_DLOCK
sync
mtspr HID0, r0
sync
@@ -1080,10 +1112,11 @@ lock_ram_in_cache:
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
- lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
- li r2,512
- mtctr r2
+ lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+ li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
+ (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r4
1: icbi r0, r3
dcbi r0, r3
addi r3, r3, 32
@@ -1096,19 +1129,20 @@ unlock_ram_in_cache:
li r5, HID0_DLOCK|HID0_DCFI
andc r3, r3, r5 /* no invalidate, unlock */
ori r5, r3, HID0_DCFI /* invalidate, unlock */
+ sync
mtspr HID0, r5 /* invalidate, unlock */
- mtspr HID0, r3 /* no invalidate, unlock */
sync
+ mtspr HID0, r3 /* no invalidate, unlock */
blr
#endif /* !CONFIG_NAND_SPL */
-#endif /* CFG_INIT_RAM_LOCK */
+#endif /* CONFIG_SYS_INIT_RAM_LOCK */
-#ifdef CFG_FLASHBOOT
+#ifdef CONFIG_SYS_FLASHBOOT
map_flash_by_law1:
/* When booting from ROM (Flash or EPROM), clear the */
/* Address Mask in OR0 so ROM appears everywhere */
/*----------------------------------------------------*/
- lis r3, (CFG_IMMR)@h /* r3 <= CFG_IMMR */
+ lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
lwz r4, OR0@l(r3)
li r5, 0x7fff /* r5 <= 0x00007FFFF */
and r4, r4, r5
@@ -1130,14 +1164,14 @@ map_flash_by_law1:
* LBIU Local Access Widow 0 will not cover this memory space. So, we
* need another window to map in it.
*/
- lis r4, (CFG_FLASH_BASE)@h
- ori r4, r4, (CFG_FLASH_BASE)@l
- stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */
+ lis r4, (CONFIG_SYS_FLASH_BASE)@h
+ ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
+ stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
- /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR1 */
+ /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
lis r4, (0x80000012)@h
ori r4, r4, (0x80000012)@l
- li r5, CFG_FLASH_SIZE
+ li r5, CONFIG_SYS_FLASH_SIZE
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
addi r4, r4, 1
bne 1b
@@ -1154,24 +1188,24 @@ remap_flash_by_law0:
lwz r4, BR0(r3)
li r5, 0x7FFF
and r4, r4, r5
- lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h
- ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l
+ lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
+ ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
or r5, r5, r4
- stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
+ stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
lwz r4, OR0(r3)
- lis r5, ~((CFG_FLASH_SIZE << 4) - 1)
+ lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
or r4, r4, r5
stw r4, OR0(r3)
- lis r4, (CFG_FLASH_BASE)@h
- ori r4, r4, (CFG_FLASH_BASE)@l
- stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */
+ lis r4, (CONFIG_SYS_FLASH_BASE)@h
+ ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
+ stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
- /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR0 */
+ /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
lis r4, (0x80000012)@h
ori r4, r4, (0x80000012)@l
- li r5, CFG_FLASH_SIZE
+ li r5, CONFIG_SYS_FLASH_SIZE
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
addi r4, r4, 1
bne 1b
@@ -1182,4 +1216,4 @@ remap_flash_by_law0:
stw r4, LBLAWBAR1(r3)
stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
blr
-#endif /* CFG_FLASHBOOT */
+#endif /* CONFIG_SYS_FLASHBOOT */
diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c
index dfd6c03..3b09a62 100644
--- a/cpu/mpc83xx/traps.c
+++ b/cpu/mpc83xx/traps.c
@@ -100,7 +100,7 @@ _exception(int signr, struct pt_regs *regs)
void dump_pci (void)
{
/*
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
printf ("PCI: err status %x err mask %x err ctrl %x\n",
le32_to_cpu (immap->im_pci.pci_esr),
le32_to_cpu (immap->im_pci.pci_emr),
@@ -124,7 +124,7 @@ MachineCheckException(struct pt_regs *regs)
*/
#ifdef CONFIG_PCI
#if 0
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
#ifdef DEBUG
dump_pci();
#endif
diff --git a/cpu/mpc83xx/u-boot.lds b/cpu/mpc83xx/u-boot.lds
index 99ad675..3a08f64 100644
--- a/cpu/mpc83xx/u-boot.lds
+++ b/cpu/mpc83xx/u-boot.lds
@@ -116,6 +116,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
generated by cgit v1.1 at 2024-11-18 20:51:19 +0000